WWW.IJITECH.ORG ISSN 2321-8665 Vol.04,Issue.01, January-2016, Pages:0077-0082 Implementation of Data Encoding and Decoding Techniques for Energy Consumption Reduction in NoC GORANTLA CHAITHANYA 1, VENKATA LAKSHMI. J 2 1 PG Scholar, Dept of ECE, Newton s Engineering College, JNTUK, AP, India, E-mail: gorantla434@gmail.com. 2 Assistant Professor, Dept of ECE, Newton s Engineering College, JNTUK, AP, India, E-mail: janamalalakshmi@gmail.com. Abstract: The technology increases in the present world even though, some of the power dissipation problems are diminishing the technology in the field of NoC. This power dissipation was mainly seen in the other elements of the communication subsystem, which are routers and network interfaces. In this project, we are developing the data encoding and decoding schemes to reduce the power dissipated by the links of a NoC. The proposed design was implemented using verilog HDL. Which allow saving us for saving power dissipation and energy consumption without any affect on performance degradation. In this project, we are proposing three different schemes to reduce the power in the links of the NoC. Here in this project we are reducing the coupling switching activity and the normal switching activity to reduce the total power dissipation in the links of the NoC by using different encoding schemes. By these proposed techniques, the consecutive bits are taken care not to have opposite values so that coupling switching activity is reduced. Similarly, the bits passed through the particular links are encoded in such a way that toggling (opposite previous and present values) of the bit values in that particular links is prevented. In this way normal switching activity is reduced. Keywords: Network On Chip (Noc), Coupling Switching Activity And The Normal Switching Activity, Power Dissipation. I. INTRODUCTION Every technology has facing some problems like power dissipation, energy problems etc. In VLSI technology the wire densities increases to support every small transistor geometries and then it leads to energy and power problems. By increasing the delay between on chip unit will get high latency of cross-chip communication can still limit the total performance. By using on-chip packet-switched micronetwork of interconnects are generally known as Networkon-Chip (NoC) architecture, we satisfied scalable bandwidth requirement. The traditional large-scale multi-processors and distributed computing network leads to get the basic idea to the NoC-based system implementation. In order to meet typical SoC of network interconnection like switching logic and the packet definition should be light-weighted to get easy implementation solutions. Another way to exceed such a limitation of communication and overcome wiring delay in future. As mentioned before the basic concept of such kind of interconnections is from the modern computer network evolution. By applying network-like communication which inserts some routers in-between each communication object, the required wiring can be shortened. Therefore, switchbased interconnection mechanism provides a lot of scalability and freedom from the limitation of complex wiring. Replacement of SoC busses by NoCs will follow the same path of data communications when the economics prove that the NoC either reduces SoC manufacturing cost, SoC time to market, SoC time to volume, and SoC design risk or increases SoC performance. According to the NoC approach has a clear advantage over traditional busses and most notably system throughput. And hierarchies of crossbars or multilayered busses have characteristics somewhere in between traditional busses and NoC, however they still fall far short of the NoC with respect to performance and complexity.the success of the NoC design depends on the research of the interfaces between processing elements of NoC and interconnection fabric. The interconnection of a SoC established procedures has some weak points in those respects of slow bus response time, scalability problem, and energy, bandwidth limitations. Bus interconnection composed of a large number of components in a network interface can cause slow interface time though the influence of sharing the bus. In addition the interconnection has a defect, which is power consumption is high on the score of connecting all objects in the communication. Moreover it is impossible to increase the number of connection of the elements infinitely by reason of the limitation of bandwidth in a bus. In fact, the communication subsystem increasingly impacts the traditional design objectives, including cost, performance, power dissipation, energy consumption etc. A. Existing system and its Drawbacks Mainly data encoding techniques are classified into two groups. In the first group, encoding techniques are concentrates on lowering the power due to self switching activity of individual bus lines. While ignoring power dissipation due to their coupling switching activity. In this group, bus invert (BI) and INC-XOR were proposed in the Copyright @ 2016 IJIT. All rights reserved.
case of random data patterns are transmitted through these lines. On the other hand, T0, working-zone encoding and T0-XOR were suggested for the case of correlated data patterns. Here we were also proposed Application-specific proposals. This group of encoding is not suitable to be applied for deep sub micron meter technology nodes. Where the coupling capacitance comprises major part of the total interconnect capacitance of the link. Drawbacks of present existing system are: Increase the chip area Increasing line-to-line spacing More power consumption GORANTLA CHAITHANYA, VENKATA LAKSHMI. J fact that Type I transitions show different behaviors in the case of odd and even inverts and make the inversion which leads to the higher power saving. TABLE I: Effect of Odd Inversion Based On Change of Transition Types II. PROPOSED METHODOLOGY We focus on techniques aimed at reducing the power dissipated by the network links and also by routers and network interfaces (NIs) and their contribution is expected to increase as per the present technology. In particular, we were present a set of data encoding schemes operating at flit level and on an end-to-end base, which can allows us to minimize both the switching activity and the coupling switching activity. The proposed encoding schemes are presented and discussed at both the algorithmic level and assessed by means of simulation on synthetic and real traffic scenarios. The analysis considers into account several aspects and metrics of the system design, including silicon area, power dissipation and energy consumption. The results shown that by using the proposed encoding schemes the power and energy can be saved without any significant degradation in performance and with area overhead in the NI. Energy consumption and power dissipation are today recognized as the most important design optimization objectives. In this paper, we present two encoding schemes. In Scheme II, both Types I and II transitions are taken into account for deciding between half and full invert, which is depending up on the amount of switching reduction. Finally, in Scheme III, we consider the fact that Type I transitions show different behaviors in the case of odd and even inverts and make the inversion which leads to the higher power saving. The basic idea of the proposed approach is encoding the flits before they are injected into the network with the goal of minimizing the self-switching activity and the coupling switching activity in the links traversed by the flits. In fact, self-switching activity and coupling switching activity are responsible for link power dissipation. Our aim is to covert Type-I and Type-II to Type-III and Type-IV bit combinations as far as possible. This is because, Type-III and Type-IV combinations result in less coupling switching and normal switching activities. Wormhole flow control, also called wormhole switching or wormhole routing is a system of simple flow control in computer networking based on known fixed links. Where it is a subset of flow control method called Flit-Buffer Flow Control. In this project, we present two encoding schemes. Scheme II, both Types I and II transitions are taken into account for deciding between half and full invert, depending up on the amount of switching reduction. Finally, in Scheme III, we consider the The basic idea of the proposed approach is encoding the flits before they are injected into the network with the goal of minimizing the self-switching activity and the coupling switching activity in the links traversed by the flits. In fact, self-switching activity and coupling switching activity are responsible for link power dissipation. A. Scheme 2: Encoder and Decoder Design In the proposed encoding scheme II, we are making use of both odd and full inversion. The full inversion operation converts Type II transitions to Type IV transitions. This scheme compares the current data with the previous one to decide whether the odd, full, or no inversion can give rise to the link power reduction. Fig.1. Proposed encoder architecture for scheme 2.
Implementation of Data Encoding and Decoding Techniques for Energy Consumption Reduction in NoC In this encoder, in addition to the Ty block in the Scheme I encoder, we have the T2 and T **4 blocks which determine if the inversion based on the transition types T2 and T**4 should be taken place for the link power reduction. Then the second stage is formed by a set of 1s blocks which count the number of 1s in their inputs. The output of these blocks having the width of log 2 w. The output of the top 1s block determines the number of transitions that odd inverting of pair bits leads to the link power reduction. The middle 1 s block identifies the number of transitions whose full inverting of pair bits leads to the link power reduction. Finally, the bottom 1 s block specifies the number of transitions whose full inverting of pair bits leads to the Fig.5. Ones Module. increased link power. Based on the number of 1 s for each transition type, Module A decides if an odd invert or full invert action should be performed for the power reduction. In this project, we design our design for the internal modules of the scheme 2 encoder like module-a and T2, Ty, T4** and ones counter. The design diagrams of these modules are shown below Figs.1 to 6. Fig.6. Module-A. Fig.2. Ty module. This module determines if the odd, even, full, or no invert action corresponding to the outputs 10, 01, 11, or 00, respectively, should be performed. The outputs 01, 11, and 10 show that whether respectively, are satisfied. In this project, Module C was designed based on the conditions given. The output of the encoder is given as input to the decoder. Mainly the designing of this encoder and decoder is to reduce the normal switching activity and the coupling switching activity in the links of the network on chip. The operation performed in the decoder is to determine which action has been taken in the encoder. If two inversion bits were used, the overhead of the decoder hardware could be substantially reduced. The internal diagram of the scheme 2 decoder was as shown in the below fig.7. Fig.3. T2 Module. Fig.4. T4** Module. Fig.7. Decoder of Scheme II.
B. Scheme 3: Encoder And Decoder Design In the proposed encoding Scheme III, we add even inversion to Scheme II. Because of the reason is that odd inversion converts some of Type I (T 1) transitions to Type II transitions. As can be observed from Table given above, if the flit is even inverted, the transitions indicated as T 1/ T 1 in the table are converted to Type IV/Type III transitions. Therefore, the even inversion may reduce the link power dissipation as well. The scheme compares the current data with the previous one to decide whether odd, even, full, or no inversion of the current data can give rise to the link power reduction. TABLE II: Effect of Even Inversion on Change of Transition Types GORANTLA CHAITHANYA, VENKATA LAKSHMI. J The wth bit of the previously encoded body flit is indicated by inv which shows if it was even, odd, or full inverted (inv = 1) or left as it was (inv = 0). The first stage of the encoder determines the transition types while the second stage is formed by a set of 1s blocks which count the number of ones in their inputs. In the first stage, we have added the Te blocks which determine if any of the transition types of T2, T **1, and T **1 is detected for each pair of their input bits. For these transition types, the even invert action yields link power reduction. Again, we have four Ones blocks to determine the number of detected transitions for each Ty, Te, T2, T **4, blocks. The output of the Ones blocks are inputs for Module C. This module determines if odd, even, full, or no invert action corresponding to the outputs 10,, 01, 11, or 00, respectively should be performed. The encoder architecture of the scheme 3 was as shown in the below fig.8. Fig.9. Module-C. The decoder architecture of scheme 3 is as shown in the below fig.10. Fig.8. Encoder architecture of the scheme3. The operating principles of this encoder are similar to those of the encoders implementing Schemes II. The proposed encoding architecture is based on the even invert condition, full invert condition and the odd invert condition is shown in the above fig.9. Fig.10. Decoder of Scheme III.
Implementation of Data Encoding and Decoding Techniques for Energy Consumption Reduction in NoC III. SIMULATION RESULTS Simulation was done on MATLAB R2013a, the results was shown that the features of all face, iris and fingerprint images are trained and tested perfectly for obtaining fake images in biometric security systems as shown in Figs.11 and 12. Fig.11. Simulation results of scheme2. Fig.12. Simulation results of scheme3. IV. CONCLUSION We have implemented two schemes proposed in the paper (namely scheme-ii and scheme-iii) to reduce coupling switching activity and normal switching activity in links of Network-on-Chips. By these proposed techniques, the consecutive bits are taken care not to have opposite values so that coupling switching activity is reduced. Similarly, the bits passed through particular links are encoded in such a way that toggling (opposite previous and present values) of the bit values in that particular links is prevented. It is the way to reduce the switching activity. Note that in the Table-I of the IEEE paper, our aim is to covert Type-I and Type-II to Type-III and Type-IV bit combinations as far as possible. This is because, Type-III and Type-IV combinations result in less coupling switching and normal switching activities. Out of the two schemes those are implemented, scheme-iii have even lesser coupling switching and normal switching activity compared to scheme-ii. This was achieved by the inclusion of even inversion module te module in the Scheme-III. By this, Type-I and Type-II bit combinations are converted in to Type-III and Type-IV bit combinations mentioned in Table 1. Whereas Scheme-II converts some Type-I bit combinations to Type-II bit combinations. So, as we discussed earlier, Scheme-III is more optimized than Scheme-II. V. REFERENCES [1]Zarandi, A.A.E.Dept. of Comput. Eng., Islamic Azad Univ., Tehran, Iran Molahosseini, A.S. ; Hosseinzadeh, M. ; Sorouri, S. ; Antao, S. ; Sousa, L. Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations in Very Large Scale Integration (VLSI) Systems, IEEE Transactions on (Volume:23, Issue: 2 ), February 2014. [2]M. S. Rahaman and M. H. Chowdhury, Crosstalk avoidance and errorcorrection coding for coupled RLC interconnects, in Proc. IEEE Int. Symp. Circuits Syst., May 2009, pp. 141 144. [3]W. Wolf, A. A. Jerraya, and G. Martin, Multiprocessor system-on-chip MPSoC technology, IEEE Trans. Comput.- Aided Design Integr. Circuits Syst., vol. 27, no. 10, pp. 1701 1713, Oct. 2008. [4]L. Benini and G. De Micheli, Networks on chips: A new SoC paradigm, Computer, vol. 35, no. 1, pp. 70 78, Jan. 2002. [5]S. E. Lee and N. Bagherzadeh, A variable frequency link for a poweraware network-on-chip (NoC), Integr. VLSI J., vol. 42, no. 4,pp. 479 485, Sep. 2009. [6]D.Yeh,L.S.Peh,S.Borkar,J.Darringer,A.Agarwal,andW.M. Hwu, Thousandcore chips roundtable, IEEE Design Test Comput., vol. 25,no. 3, pp. 272 278, May Jun. 2008. [7]A. Vittal and M. Marek-Sadowska, Crosstalk reduction for VLSI, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 16, no. 3,pp. 290 298, Mar. 1997. [8]M. Ghoneima, Y. I. Ismail, M. M. Khellah, J. W. Tschanz,and V. De, Formal derivation of optimal active shielding for low-power onchip buses, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 25,no. 5, pp. 821 836, May 2006. [9]L. Macchiarulo, E. Macii, and M. Poncino, Wire placement for crosstalk energy minimization in address buses, in Proc. Design Autom.Test Eur. Conf. Exhibit., Mar. 2002, pp. 158 162. [10]R. Ayoub and A. Orailoglu, A unified transformational approach for reductions in fault vulnerability, power, and
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