Board-Data Processing VHDL Exercises Exercise 1: Basics of VHDL Programming Stages of the Development process using FPGA s in Xilinx ISE.
Basics of VHDL VHDL (Very High Speed IC Hardware description Language) is one of the standard hardware description language used to design digital systems.
Structure of VHDL code Library Declaration Entity Architecture process process process
Structure of VHDL code Library Declaration library IEEE; use IEEE.STD_LOGIC_1164.ALL; STANDARD: Contains all basic declarations and definitions of language constructs and it is included in all VHDL specifications by default. STD_LOGIC_1164: This package is not a part of the VHDL Standard but is a standard on its own; it contains the most often used language extensions. TEXTIO: Contains declarations of basic operations on texts.
Structure of VHDL code Entity Defines the interface of the design Interface entity ANDGATE is port ( A : in STD_LOGIC; B : in STD_LOGIC; O : out STD_LOGIC); end ANDGATE
Architecture Describes the functionality of the design i.e transforming input data into output results. Functionality architecture Behavioral of ANDGATE is begin O <= A and B; end Behavioral;
Example1 library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity ANDGATE is port ( A : in STD_LOGIC; B : in STD_LOGIC; O : out STD_LOGIC); end ANDGATE architecture Behavioral of ANDGATE is begin O <= A and B; end Behavioral;
Signals
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Stages of the Development of a Digital process in FPGA s
Design Entry Design Constraints Simulation Synthesis Design Library Place & Route Download
Design Entry -> Writing the VHDL or VERILOG code
Simulation -> Identify Syntax and logic errors
-> Generate Netlist Synthesis
Place & Route -> Map, Place & Route and generate the binary file
Download -> Flash the binary file on the FPGA development board
FPGAs Kit and Development Enviroment
How to Start the Hardware Development in FPGA
1.Open the Xilinx ISE project Navigator
2. Create a New Project and save it to appropriate location and please note that don t use spaces in the destination of the project
3. Give the name of the project and click Next.
4. Select the Family, Device, Package, Simulator and Preferred Language as shown below.
5. Click Finish.
6. Now you have to Add a new vhdl file to write the code
7.Right Click the on the name of the device.
4. Select the VHDL module as Source type and name the VHDL file
8. Click Next
9. Open the VHDL file in the editor.
10. You can write your VHDL code here.
11. Write click on Synthesis option and select run.
12.If you have some error in your VHDL code it will be Red otherwise green.
13. Synthesis Process is Finished.
14. Now Pin Assignment has to be done so Click on FloorPlanning
15. Click Yes and Wait, It takes some time to open the window for floor planning (Pin Assignment)
16.Don t update the software so press Exit button to cancel the update.
17. This is place where you will map your I/O s to the actual hardware
18. Click the I/O ports Tab
19. Select the Appropriate Pins for each of the Port Signal from the Site Column by double clicking it corresponding to the Signal.
20a. When you are done with the pin Assignment, Click to save the changes and switch to the ISE design Software.
20b. Now right click on the Implement design and click run to Translate, Map, Place and Route
21. When the design is implemented successfully it will be shown up green as follows.
20. Now you have to Generate the programming File so right click on it and run.
22. If this process is successfully completed then you will have a.bit file in your project directory which will downloaded on the FPGA kit.
22. Now it s the turn of the downloading procedure so double click on Configure Target Device.
23. Double Click on Boundary Scan.
24a. Follow the instruction on the white window and select the Initialize Chain option.
24b. If board is connected and Switched On then you will have the following output
25. Now select the bit file and click open.
We are not using PROMS so click No.
26a. Click Bypass
26b.Click Ok.
27a. Right Click on the device, It will be turned Green, Now select Program.
27b.You will see a red light flashing and status bar.
28. If the program is successfully downloaded on the board then the output will appear as shown below.