Combinational Logic. Prof. Wangrok Oh. Dept. of Information Communications Eng. Chungnam National University. Prof. Wangrok Oh(CNU) 1 / 93

Combinational Logic Prof. Wangrok Oh Dept. of Information Communications Eng. Chungnam National University Prof. Wangrok Oh(CNU) / 93

Overview Introduction 2 Combinational Circuits 3 Analysis Procedure 4 Design Procedure 5 Binary Adder-Subtractor 6 Decimal Adder 7 Binary Multiplier 8 Magnitude Comparator 9 Decoders Encoders Multiplexer 2 HDL Models of Combinational Circuits Prof. Wangrok Oh(CNU) 2 / 93

Introduction Logic circuits for digital systems may be combinational or sequential Combinational logic circuit Outputs are determined from only the present combination of inputs Combinational circuit performs an operation that can be specified logically by a set of Boolean functions Sequential logic circuits Employ storage elements in addition to logic gates Outputs are a function of the inputs and the state of the storage elements Outputs depend both on present and past inputs Circuit behavior must be specified by a time sequence of inputs and internal states Prof. Wangrok Oh(CNU) Introduction 3 / 93

Combinational Circuits A combinational circuit consists of an interconnection of logic gates Chapter 4 Combinational Logic Block diagram of a combinational circuit n inputs Combinational circuit m outputs FIGURE 4. Block diagram n input of binary combinational variablescircuit come from an external source m output variables are produced by the internal combinational logic and go to an external destination destination Each are storage input and registers. output If variable the registers exists physically are included as an with analog the combinational signal gates, then the whose total values circuit are must interpreted be considered to be a sequential circuit. For n input variables, there are 2 n to be a binary signal that represents logic and logic possible combinations of the binary inputs. For each possible input In combination, many applications, there the is one source possible and destination value for each are output storage variable. registers Thus, a combinational If the circuit registers can be are specified included with with a the truth combinational table that lists gates, the then output the values for each combination total circuit of input must variables. be considered A combinational to be a sequential circuit also circuit can be described by m Boolean functions, one for each output variable. Each output function is expressed in terms of the n input variables. Prof. In Chapter Wangrok Oh(CNU), we learned about binary Combinational numbers Circuits and binary codes that represent discrete 4 / 93

Combinational Circuits For n input variables, there are 2 n possible combinations of the binary inputs A combinational circuit also can be described by Truth table m Boolean expression (One for each output variable) Each expression can be expressed with n input variables Prof. Wangrok Oh(CNU) Combinational Circuits 5 / 93

Analysis Procedure The first step in the analysis is to make sure that the given circuit is combinational and not sequential The diagram of a combinational circuit has logic gates with no feedback paths or memory elements Obtaining the Boolean function from a logic diagram Label all gate outputs that are a function of input variables 2 Determine the Boolean functions for each gate output 3 Label the gates that are a function of input variables and previously labeled gates 4 Find the Boolean functions for these gates 5 Repeat the process in step 3 and 4 until the outputs are obtained 6 By repeated substitution of previously defined functions, obtain the output Boolean functions in terms of input variables Prof. Wangrok Oh(CNU) Analysis Procedure 6 / 93

Analysis Procedure 28 Chapter 4 Combinational Logic A B C T 2 F A B C T T 3 F 2 A B A C F 2 B C FIGURE 4.2 Logic diagram for analysis example The circuit has 3 binary inputs and 2 binary outputs F 2 = AB + AC + BC If we want to pursue the investigation and determine the information transformation task achieved by this circuit, we can draw the circuit from the derived Boolean expressions and try to recognize = A + B + C T a familiar operation. The Boolean functions for F a n d F 2 implement a circuit discussed F in Section 4.5. Merely finding a Boolean representation of a circuit doesn t provide 2 = ABC insight into its behavior, but in this example we will observe that the Boolean equations and truth table for F a n d F 2 m a t c h t h o s e d e s c r i b i n g t h e Prof. Wangrok Oh(CNU) Analysis Procedure 7 / 93

Analysis Procedure Consider outputs that are a function of already defined symbols Obtain F with substitutions T 3 = F 2T F = T 3 + T 2 F = T 3 + T 2 = F 2T + ABC = (AB + AC + BC) (A + B + C) + ABC Prof. Wangrok Oh(CNU) Analysis Procedure 8 / 93

Analysis Procedure Truth table can be obtained once the Boolean functions are known Obtaining the truth table directly from the logic diagram Determine the number of input variables in the circuit 2 For n inputs, form the 2 n possible input combinations and list the binary numbers from to 2 n in a table 3 Label the outputs of selected gates with arbitrary symbols 4 Obtain the truth table for the outputs of those gates which are a function of the input variables only Section 4.4 Design Procedure 29 5 Proceed to obtain the truth table for the outputs of those gates which are Table a function 4. of previously defined values Truth Table for the Logic Diagram of Fig. 4.2 A B C F 2 F 2 T T 2 T 3 F Prof. Wangrok Oh(CNU) Analysis Procedure 9 / 93

Analysis Procedure Another way of analyzing a combinational circuit is by means of logic simulation This is not practical because the number of input patterns that might be needed to generate meaningful outputs could be very large Simulation has a very practical application in verifying that the functionality of a circuit actually matches its specification Prof. Wangrok Oh(CNU) Analysis Procedure / 93

Design Procedure Design procedure From the specifications, determine the required number of inputs and outputs and assign a symbol to each 2 Derive the truth table that defines the required relationship between inputs and outputs 3 Obtain the simplified Boolean functions for each output 4 Draw the logic diagram and verify the correctness of the design manually or by simulation Several constraints must be taken into consideration when designing integrated circuits Number of gates Number of inputs to a gate Propagation time of the signal through the gates Number of interconnections Limitations of the driving capability of each gate Prof. Wangrok Oh(CNU) Design Procedure / 93

Design Procedure Code Conversion Example Binary coded decimal (BCD) Excess-3 code Each code uses 4 bits to represent a decimal digit 4 input and 4 output variables Table 4.2 Truth Table for Code Conversion Example Input BCD Section 4.4 Design Procedure 3 Output Excess-3 Code A B C D w x y z Note that only combinations are listed 6 combinations are don t care combinations be four input variables and four output variables. We designate the four input binary Prof. Wangrok Oh(CNU) Design Procedure 2 / 93

Design Procedure 32 Chapter 4 Combinational Logic C CD AB m m m 3 m 2 AB CD C m m m 3 m 2 A m 4 m 5 m 7 m 6 m 2 m 3 m 5 m 4 X X X X m 8 m 9 m m X X B A m 4 m 5 m 7 m 6 m 2 m 3 m 5 m 4 X X X X m 8 m 9 m m X X B D z D C CD AB m m m 3 m 2 D y CD C D C CD AB m m m 3 m 2 A m 4 m 5 m 7 m 6 m 2 m 3 m 5 m 4 X X X X m 8 m 9 m m B A m 4 m 5 m 7 m 6 m 2 m 3 m 5 m 4 X X X X m 8 m 9 m m B X X X X D x B C B D BC D FIGURE 4.3 Maps for BCD-to-excess-3 code converter D w A BC BD Prof. Wangrok Oh(CNU) Design Procedure 3 / 93

Design Procedure z = D y = CD + C D = CD + (C + D) x = B C + B D + BC D = B (C + D) + BC D = B (C + D) + B(C + D) w = A + BC + BD = A + B(C + D) Implementation in sum-of-products form requires 7 AND gates and 3 OR gates Prof. Wangrok Oh(CNU) Design Procedure 4 / 93

Design Procedure Section 4.5 Binary Adder Subtractor 33 D z D C CD y (C D) C D B x A w FIGURE 4.4 Logic diagram for BCD-to-excess-3 code converter The implementation requires 4 AND gates, 4 OR gates, and one inverter implementation will require inverters for variables B, C, a n d D, and the second implementation will require inverters for variables B and D. Thus, the three-level logic Prof. Wangrok Oh(CNU) circuit requires fewer gates, all Design of which Procedure in turn require no more than two inputs. 5 / 93

Binary Adder-Subtractor The most basic arithmetic operation is the addition of two binary digits The simple addition consists of 4 possible elementary operations += / += / += / += First three operations produce a sum of one digit When both augend and addend bits are equal to, the binary sum consists of two digits The higher significant bit of this result is called a carry A combinational circuit that performs the addition of two bits is called a half adder One that performs the addition of three bits (two bits and a previous carry) is a full adder Two half adders can be employed to implement a full adder Connecting n full adders in cascade produces a binary adder for two n-bit numbers The subtraction circuit is included in a complementing circuit Prof. Wangrok Oh(CNU) Binary Adder-Subtractor 6 / 93

represents the least significant bit of the sum. S = x y + xy The simplified Boolean functions for the two outputs can be obtained directly from the truth table. The simplified sum-of-products C = xy expressions are The logic diagram of the half adder S = implemented x y + xy in sum of products is shown in Fig. 4.5(a). It can be also implemented with an exclusive-or and an AND gate as shown in Fig. 4.5(b). This form is used to show that two half adders can be used to construct a The logic diagram of the half adder implemented in sum of products is shown in Fig. 4.5(a). It can be also implemented with an exclusive-or and an AND gate as shown Half Adder in Fig. 4.5(b). This form is used to show that two half adders can be used to construct a full adder. x y C S Table 4.3 Half Adder x y C S Simplified sum-of-products expressions: x y S = x Sy + xy x C = xy x x y y S y x S C x y C x y S y (a) S xy x y (b) S x y C xy C xy Binary Adder-Subtractor Half Adder C = xy full Aadder. half adder requires 2 binary inputs and 2 binary outputs (sum and carry) Table 4.3 x FIGURE y 4.5 Implementation of half adder C C (a) S xy x y (b) S x y C xy C xy Prof. Wangrok Oh(CNU) Binary Adder-Subtractor 7 / 93

Binary Adder-Subtractor Full Adder Addition of n-bit binary numbers requires the use of a full adder After the least significant bit, addition at each position adds not only the respective bits but must also consider a possible carry bit from the previous position Full adder is a combinational circuit that forms the arithmetic sum of three bits It consists of 3 inputs and 2 outputs Two of the input variables represent the two bits to be added The third input represents the carry from the previous lower significant position The two outputs are designated by the symbols S for sum and C for carry Prof. Wangrok Oh(CNU) Binary Adder-Subtractor 8 / 93

Binary Adder-Subtractor Table 4.4 Full Adder x y z C S 36 Chapter 4 Combinational Logic yz x y x yz y m m m 3 m 2 m m m 3 m 2 x m 4 m 5 m 7 m 6 m 4 x m 5 m 7 m 6 z z S = x y z + x yz + xy z + xyz (a) S x y z x yz xy z xyz FIGURE 4.6 C = xy + xz + yz K-Maps for full adder (b) C xy xz yz Prof. Wangrok Oh(CNU) Binary Adder-Subtractor 9 / 93

FIGURE 4.6 Binary Adder-Subtractor K-Maps for full adder x y z x y z x y z x y z FIGURE 4.7 Implementation of full adder in sum-of-products form S = x y z + x yz + xy z + xyz S in Fig. 4.8. The S output from = the z (xy second + x half y) adder + z(xy is the + x exclusive-or y ) of z and the output of the first half adder, giving = z (xy + x y) + z(xy + x y) S = z { x { y2 = z xy = z + x y2 (x + y) zxy + x y2 C = z xy = z(xy + x y2 + x + y) zxy + + xyx y 2 = xy z + x yz + xyz + x y z = z(x y) + xy The carry output is C = zxy + x y2 + xy = xy z + x yz + xy Prof. Wangrok Oh(CNU) Binary Adder-Subtractor 2 / 93 x y x z y z C

Binary Adder-Subtractor Section 4.5 Binary Adder Subtractor 37 x y x y (x y) z S xy (x y) z (x y) z xy C z FIGURE 4.8 Implementation of full adder with two half adders and an OR gate Addition of n-bit numbers requires a chain of n full adders or a chain of one-half adder and n 9 full adders. In the former case, the input carry to the least significant position is fixed at. Figure 4.9 shows the interconnection of four full-adder (FA) circuits to provide a four-bit binary ripple carry adder. The augend bits of A and the addend bits of B are designated by subscript numbers from right to left, with subscript denoting the least significant bit. The carries are connected in a chain through the full adders. The Prof. Wangrok Oh(CNU) Binary Adder-Subtractor 2 / 93

Binary Adder-Subtractor Binary Adder A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers It can be constructed with full adders connected in cascade The output carry from each full adder connected to the input carry of the next full adder in the chain Addition of n-bit numbers requires a chain of n full adders or a chain of one-half adder and (n ) full adders 38 Chapter 4 Combinational Logic 4-bit binary ripple carry adder B 3 A 3 B 2 A 2 B A B A FA C 3 FA C 2 FA C FA C C 4 S 3 S 2 S S FIGURE 4.9 Four-bit adder Prof. Wangrok Oh(CNU) Binary Adder-Subtractor 22 / 93

Binary Adder-Subtractor Carry Propagation Section 4.5 Binary Adder Subtractor 39 Half adder Half adder A i B i P i P i C i S i G i P i C i G i C i C i FIGURE 4. Full adder Signal with CP i and to CG i+ shown propagates through an AND gate and an OR gate If there are 4 full adders in the adder Output carry C 4 would have 2 4 = 8 gate levels from C The carry propagation time is an important to C 4 attribute of the adder because it limits the speed For with an which n-bit two adder, numbers there are are added. 2n gate Although levels for the the adder or, carry to for that matter, any combinational propagatecircuit will from input to always output have some value at its output terminals, the outputs will The not carry be correct propagation unless the time signals is anare important given enough attribute: time to Itpropagate limits thethrough the gates connected speed of adder from the inputs to the outputs. Since all other arithmetic operations are implemented by successive additions, the time consumed during the addition process is critical. An obvious solution for reducing the carry propagation delay time is to Prof. Wangrok Oh(CNU) Binary Adder-Subtractor 23 / 93

Binary Adder-Subtractor An obvious solution for reducing the carry propagation delay time is to employ faster gates with reduced delays Physical circuits have a limit to their capability of speed There are several techniques for reducing the carry propagation time in a parallel adder The most widely used technique employs the principle of carry lookahead logic P i = A i B i G i = A ib i Output sum and carry S i = P i C i C i+ = G i + P ic i G i is called a Carry generate and it produces a carry of when both A i and B i are regardless of the input carry C i P i is called a carry propagate It determines whether a carry into stage i will propagate into stage (i + ) Prof. Wangrok Oh(CNU) Binary Adder-Subtractor 24 / 93

Binary Adder-Subtractor Boolean functions for the carry outputs of each stage C : Input carry 2 C = G + P C 3 C 2 = G + P C = G + P (G + P C ) = G + P G + P P C 4 C 3 = G 2 + P 2 C 2 = G 2 + P 2 G + P 2 P G + P 2 P P C Boolean function for each output carry is expressed in sum-of-products form Can be implemented with one level of AND gates followed by an OR gate (or by a two-level NAND) Note that this circuit can add in less time because C 3 does not have to wait for C 2 and C to propagate This gain in speed of operation is achieved at the expense of additional complexity (hardware) Prof. Wangrok Oh(CNU) Binary Adder-Subtractor 25 / 93

are propagated through the carry lookahead generator (similar to that in Fig. 4. ) and applied as inputs to the second exclusive-or gate. All output carries are generated after Binary Adder-Subtractor C 3 P 2 G 2 C 2 P G P C G C FIGURE 4. Logic diagram of carry lookahead generator Prof. Wangrok Oh(CNU) Binary Adder-Subtractor 26 / 93

Binary Adder-Subtractor Section 4.5 Binary Adder Subtractor 4 C 4 C 4 B 3 P 3 A P 3 3 G 3 C 3 S 3 B 2 A 2 P 2 P 2 C 2 S 2 G 2 B A P Carry Lookahead Generator P C S G B A P P S G C C FIGURE 4.2 Four-bit adder with carry lookahead Prof. Wangrok Oh(CNU) Binary Adder-Subtractor 27 / 93

Binary Adder-Subtractor Each sum output requires two exclusive-or gates First exclusive-or generates P i and AND gate generates G i The carries are propagated through the carry lookahead generator and applied as inputs to the second exclusive-or gate All output carries are generated after a delay through two levels of gates Prof. Wangrok Oh(CNU) Binary Adder-Subtractor 28 / 93

Binary Adder-Subtractor Binary Subtractor Subtraction of unsigned binary numbers can be done most conveniently by means of complements Subtraction (A B) can be done by taking the 2 s complement of B and adding it to A 2 s complement can be obtained by taking the s complement and adding to the least significant pair of bits s complement can be implemented with inverters can be added to the sum through the input carry Circuit for subtracting (A B) consists of an adder with inverters (A B): A + ( s complement of B) + Prof. Wangrok Oh(CNU) Binary Adder-Subtractor 29 / 93

Binary Adder-Subtractor 42 Chapter 4 Combinational Logic B 3 A 3 B 2 A 2 B A B A M C C 4 FA C 3 FA C 2 FA C FA C V S 3 S 2 S S FIGURE 4.3 Binary numbers Four-bit adder subtractor in the signed-complement (with overflow detection) system are added and subtracted by the same basic addition and subtraction rules Computers need only one common hardware to handle both types The circuit for subtracting A - B consists of an adder with inverters placed between each data input B and the corresponding input of the full adder. The input carry C must User must be equal interpret to when subtraction the results is performed. of addition/subtraction The operation thus performed differently becomes A, depending plus the on s whether complement it of isb signed, plus. This or unsigned is equal to A plus the 2 s complement of B. For unsigned numbers, that gives A - B if A Ú B or the 2 s complement of B - A2 if A 6 B. For signed numbers, the result is A - B, provided that there is no overflow. (See Section.6.) Prof. Wangrok Oh(CNU) The addition and subtraction Binary Adder-Subtractor operations can be combined into one circuit with one 3 / 93

whether the numbers are considered to be signed or unsigned. When two unsigned numbers are added, an overflow is detected from the end carry out of the most significant position. In the case of signed numbers, two details are important: the leftmost bit always represents the sign, and negative numbers are in 2 s-complement form. When two signed numbers are added, the sign bit is treated as part of the number and the end Binary Adder-Subtractor Overflow carry does not indicate an overflow. When two numbers with n digits are added and the sum is a number of (n + ) digits, we say that an overflow occurred Overflow detection of unsigned addition: End carry out of the most significant position Signed case An overflow cannot occur if one number is positive and the other is negative An overflow may occur if the two numbers added are both positive or additions in binary are shown next, together with the last two carries: both negative An overflow cannot occur after an addition if one number is positive and the other is negative, since adding a positive number to a negative number produces a result whose magnitude is smaller than the larger of the two original numbers. An overflow may occur if the two numbers added are both positive or both negative. To see how this can happen, consider the following example: Two signed binary numbers, +7 and +8, are stored in two eight-bit registers. The range of numbers that each register can accommodate is from binary +27 to binary -28. Since the sum of the two numbers is +5, it exceeds the capacity of an eight-bit register. This is also true for -7 and -8. The two carries: carries: +7-7 +8-8 +5-5 Note that Eight-bit the eight-bit resultsresult that that should should have have been been positive positive has has a negative a negative sign sign bit (i.e., the eighth bit and bit) the and eight-bit the eight-bit result result that that should should have have been been negative has hasa apositive sign bit. If, positive however, sign the carry bit out of the sign bit position is taken as the sign bit of the result, then the Annine-bit overflowanswer condition so obtained can be detected will be correct. by observing But since the the carry answer into cannot the be accommodated sign bit position within eight and bits, the carry we say out that ofan the overflow sign bithas position occurred. If these An two overflow carries condition are notcan equal, be detected an overflow by observing has occurred the carry into the sign bit position and the carry out of the sign bit position. If these two carries are not equal, an overflow has occurred. This is indicated in the examples in which the two carries are explicitly Prof. Wangrok Oh(CNU) Binary Adder-Subtractor 3 / 93

Decimal Adder Binary addition: it is sufficient to consider a pair of bits with a carry Decimal adder requires a minimum of 9 inputs and 5 outputs Input: Two 4-bit input and -bit carry-in Output: 4-bit output and -bit carry-out There is a wide variety of possible decimal adder circuits depending on the code used to represent the decimal digits Prof. Wangrok Oh(CNU) Decimal Adder 32 / 93

Decimal Adder BCD Adder Arithmetic addition of two decimal digits in BCD Section 4.6 Decimal Adder 45 Each input digit does not exceed 9 Sum cannot be greater than 9 (9+9+) Table 4.5 Derivation of BCD Adder Binary Sum BCD Sum Decimal K Z 8 Z 4 Z 2 Z C S 8 S 4 S 2 S 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 Prof. Wangrok Oh(CNU) Decimal Adder 33 / 93

Decimal Adder When the binary sum is equal to or less than, the corresponding BCD number is identical No conversion is needed When the binary sum is greater than We obtain an invalid BCD representation Addition of binary 6 () to the binary sum converts it to the correct BCD representation and produces an output carry as required Correction is needed when the binary sum has an output carry K = and when the binary sum is in the range from to Condition for a correction and an output carry can be expressed by the Boolean function C = K + Z 8Z 4 + Z 8Z 2 When C =, it is necessary to add to the binary sum and provide an output carry for the next stage Prof. Wangrok Oh(CNU) Decimal Adder 34 / 93

Decimal 46 Adder Chapter 4 Combinational Logic Addend Augend Carry out K 4-bit binary adder Carry in Z 8 Z 4 Z 2 Z Output carry 4-bit binary adder S 8 S 4 S 2 S FIGURE 4.4 Prof. Wangrok Oh(CNU) Block diagram of a BCD adder Decimal Adder 35 / 93

Binary Multiplier Binary number multiplication is performed in the same way as decimal number multiplication Section 4.7 Binary Multiplier 47 B B A B B A A A B A B A B A B C 3 C 2 C C A B B HA HA FIGURE 4.5 Two-bit by two-bit binary multiplier C 3 C 2 C C Prof. Wangrok Oh(CNU) Binary Multiplier 36 / 93

Binary Multiplier Binary multiplier with more bits can be constructed in a similar fashion J-bit multiplier and K-bit multiplicand (J K) AND gates (J ) K-bit adders Product output will be a binary number with (J + K)-bits Prof. Wangrok Oh(CNU) Binary Multiplier 37 / 93

Binary Multiplier 48 Chapter 4 Combinational Logic A B 3 B 2 B B A B 3 B 2 B B Addend Augend 4-bit adder Sum and output carry A 2 B 3 B 2 B B Addend Augend 4-bit adder Sum and output carry C 6 C 5 C 4 C 3 C 2 C C FIGURE 4.6 Four-bit by three-bit binary multiplier Prof. Wangrok Oh(CNU) Binary Multiplier 38 / 93

Magnitude Comparator A magnitude comparator is a combinational circuit that compares two numbers A and B and determines their relative magnitudes Circuit for comparing two n-bit numbers has 2 2n entries in the truth table and becomes too complex Fortunately, a comparator circuit possesses a certain amount of regularity Two numbers A and B with 4 digits each A = A 3 A 2 A A B = B 3 B 2 B B Equality of each pair of bits (A i = B i ) can be expressed with an exclusive-nor x i = A i B i + A ib i To determine whether A is greater or less than B, we inspect the relative magnitudes of pairs of significant digits starting from the most significant position Prof. Wangrok Oh(CNU) Magnitude Comparator 39 / 93

Magnitude Comparator If the two digits of a pair are equal, we compare the next lower significant pair of digits The comparison continues until a pair of unequal digits is reached If the corresponding digit of A is and that of B is : A > B If the corresponding digit of A is and that of B is : A < B (A > B) = A 3 B 3 + x 3 A 2 B 2 + x 3 x 2 A B + x 3 x 2 x A B (A < B) = A 3B 3 + x 3 A 2B 2 + x 3 x 2 A B + x 3 x 2 x A B Prof. Wangrok Oh(CNU) Magnitude Comparator 4 / 93

Magnitude 5 Chapter Comparator 4 Combinational Logic A 3 x 3 B 3 A 2 x 2 B 2 (A B) A x B A x (A B) B (A B) FIGURE 4.7 Four-bit magnitude comparator Prof. Wangrok Oh(CNU) Magnitude Comparator 4 / 93

Decoders A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2 n unique output lines Decoders presented here are called n-to-m-line decoders m 2 n The name decoder is also used in conjunction with other code converters such as a BCD-to-seven-segment decoder Example: 3-to-8 line decoder The three inputs are decoded into eight outputs Each output represents one of the minterms of the three input variables A particular application of this decoder is binary-to-octal conversion 3-to-8 line decoder can be used for decoding any 3-bit code to provide eight outputs, one for each element of the code Prof. Wangrok Oh(CNU) Decoders 42 / 93

Decoders ber, and the outputs represent the eight digits of a number in the octal number system. However, a three-to-eight-line decoder can be used for decoding any three-bit code to provide eight outputs, one for each element of the code. D x y z z D x y z D 2 x yz y D 3 x yz x D 4 xy z D 5 xy z D 6 xyz D 7 xyz FIGURE 4.8 Three-to-eight-line decoder Prof. Wangrok Oh(CNU) Decoders 43 / 93

Decoders 52 Chapter 4 Combinational Logic Table 4.6 Truth Table of a Three-to-Eight-Line Decoder Inputs Outputs x y z D D D 2 D 3 D 4 D 5 D 6 D 7 For each possible input combination, there are 7 outputs equal to and only one equal to The operation of the decoder may be clarified by the truth table listed in Table 4.6. For each possible input combination, there are seven outputs that are equal to and only one that is equal to. The output whose value is equal to represents the minterm equivalent of the binary number currently available in the input lines. Some decoders are constructed with NAND gates. Since a NAND gate produces the AND operation with an inverted output, it becomes more economical to generate the decoder minterms in their complemented form. Furthermore, decoders include one or more enable inputs to control the circuit operation. A two-to-four-line decoder with an enable input constructed with NAND gates is shown in Fig. 4.9. The circuit operates with complemented outputs and a complement enable input. The decoder is enabled when E is equal to (i.e., active-low enable). As indicated by the truth table, only one The output whose value is equal to represents the minterm equivalent of the binary number currently available in the input lines Some decoders are constructed with NAND gates NAND produces the AND operation with an inverted output Some decoders include one or more enable inputs to control the circuit operation Prof. Wangrok Oh(CNU) Decoders 44 / 93 D

Decoders Example (2-to-4 line decoder constructed with NAND) D A B D D 2 E A B D D D 2 D 3 X X E D 3 Demultiplexer Circuit that receives information from a single line and directs it to one of 2 n possible output lines The selection of a specific output is controlled by the bit combination of n selection lines Prof. Wangrok Oh(CNU) Decoders 45 / 93

Decoders with enable inputs can be connected together to form a larger decoder circuit. Figure 4.2 shows two 3-to-8-line decoders with enable inputs connected to form a 4-to-6-line decoder. When w, the top decoder is enabled and the other is disabled The bottom decoder outputs are all s, and the top eight outputs generate minterm to. When w, the enable conditions are reversed: The bottom decoder Decoder with enable input can function as a demultiplexer outputs generate minterms to, while the outputs of the top decoder are al s. This Decoder example with demonstrates an enable: the Decoder-demultiplexer usefulness of enable inputs in decoders and other Decoders with enable inputs can be connected together to form a larger decoder Decoders x y z w 3 8 decoder E D to D 7 3 8 decoder E D 8 to D 5 FIGURE 4.2 4 * 6 decoder constructed with two 3 * 8 decoders Prof. Wangrok Oh(CNU) Decoders 46 / 93

Decoders Combinational Logic Implementation Decoder provides the 2 n minterms of n input variables Each output of the decoder is associated with a unique pattern of input bits Any Boolean function can be expressed in sum-of-minterms form Decoder that generates the minterms of the function together with an external OR gate provides a hardware implementation of the function Any combinational circuit with n inputs and m outputs can be implemented with an n-to-2 n -line decoder and m OR gates Prof. Wangrok Oh(CNU) Decoders 47 / 93

Decoders Example (Full Adder) S(x, y, z) = (, 2, 4, 7) C(x, y, z) = (3, 5, 6, 7) There are 3 inputs and eight minterms We need a three-to-eight-line decoder Prof. Wangrok Oh(CNU) Decoders 48 / 93

minterms for x, y, and z. The OR gate for output S forms the logical sum of minterms, Decoders 2, 4, and 7. The OR gate for output C forms the logical sum of minterms 3, 5, 6, and 7. x 2 2 2 S y 2 3 8 decoder 3 4 z 2 5 6 C 7 FIGURE 4.2 Implementation Function with of a full a long adder list with of a minterms decoder Requiring an OR gate with a large number of inputs Function having k midterms can be expressed in its complemented form with 2 n k midterms If the number of midterms is greater than 2 n /2 F can be expressed with fewer midterms Use a NOR gate to sum the minterms of F Output of the NOR gate complements the sum and generates the normal output F! Prof. Wangrok Oh(CNU) Decoders 49 / 93

Decoders If NAND gates are used for the decoder External gates must be NAND gates instead of OR gates Two-level NAND gate circuit implements a sum-of-minterms and is equivalent to a two-level AND-OR circuit Prof. Wangrok Oh(CNU) Decoders 5 / 93

Encoders The encoder can be implemented with OR gates whose inputs are determined directly from the truth table. Output z is equal to when the input octal digit is, 3, 5, or 7. Output y is for octal digits 2, 3, 6, or 7, and output x is for digits 4, 5, 6, or 7. These conditions can be expressed by the following Boolean output functions: z = D + D 3 + D 5 + D 7 y = D Encoder: Digital circuit performs 2 + D the 3 + D inverse 6 + D 7 operation of a decoder Encoder has 2 n x = D 4 + D 5 + D 6 + D 7 (or fewer) input lines and n output lines The encoder can be implemented with three OR gates. The output lines generate the binary code corresponding to the input value Example: Table Octal-to-binary 4.7 encoder Truth Table of an Octal-to-Binary Encoder Inputs Outputs D D D 2 D 3 D 4 D 5 D 6 D 7 x y z Encoder can be implemented with OR gates z = D +D 3+D 5+D 7 y = D 2+D 3+D 6+D 7 x = D 4+D 5+D 6+D 7 Prof. Wangrok Oh(CNU) Encoders 5 / 93

Encoders has a third output designated by V ; this is a valid bit indicator that is set to when one or more inputs are equal to. If all inputs are, there is no valid input and V is equal to. The other two outputs are not inspected when V equals and are specified as don t-care conditions. Note that whereas X s in output columns represent don t-care conditions, the X s in the input columns are useful for representing a truth table in condensed form. Instead of listing all 6 minterms of four variables, the truth table uses an X to represent Limitations either If two or inputs. For example, are active X simultaneously, represents the two the minterms output produces and. an undefined combination Output with all s is generated when all the inputs are but this output is the same as when D is equal to Priority Encoder inputs are, and so on down the priority levels. Encoder circuit that includes the priority function If two or more inputs are equal to at the same time, the input having the highest Table priority 4.8 will be taken According to Table 4.8, the higher the subscript number, the higher the priority of the input. Input D 3 has the highest priority, so, regardless of the values of the other inputs, when this input is, the output for xy is (binary 3). D 2 has the next priority level. The output is if D 2 =, provided that D 3 =, regardless of the values of the other two lower priority inputs. The output for D is generated only if higher priority Truth Table of a Priority Encoder Inputs Outputs D D D 2 D 3 x y V X X X X X X X X Prof. Wangrok Oh(CNU) Encoders 52 / 93

D 3 D 3 x D Encoders 2 D 3 y D 3 D D 2 FIGURE 4.22 Section 4. Encoders 57 Maps for a priority encoder D 2 D 2 D 3 D 2 D 3 D D D D The maps for simplifying outputs x and y are shown in Fig. 4.22. The minterms for the m m m 3 m 2 m m m 3 m 2 two functions X are derived from Table 4.8. Although the table X has only five rows, when each X in a row is replaced first by and then by, we obtain all 6 possible input combinations. For example, the fourth row in the table, with inputs XX, represents 6 m 4 m 5 m 7 m 6 m 4 m 5 m 7 m the four minterms,,, and. The simplified Boolean expressions for the priority D m m m m D encoder are 2 obtained 3 5 from the 4 maps. The condition for output m 2 V m 3 is an mor 5 function m 4 of all the input variables. The priority encoder is implemented in Fig. 4.23 according to the following D m 8 Boolean m 9 functions: m m D m 8 m 9 m m X x = D 2 + D 3 D 3 y = D 3 + D D 2 D 3 x D 2 D 3 V = D + D + D 2 + D 3 y D 3 D D 2 FIGURE 4.22 Maps for a priority encoder D 3 y The maps D 2 for simplifying outputs x and y are shown in Fig. 4.22. The minterms for the two functions are derived from Table 4.8. Although the table has only five rows, when each X in Da row is replaced first by and then by, we obtain all 6 possible input combinations. For example, the fourth row in the table, with inputs XX, represents the four minterms,,, and. The simplified Boolean expressions for x the priority encoder are obtained from the maps. The condition for output V is an OR function of all the input variables. The priority encoder is implemented in Fig. 4.23 according to the following Boolean functions: V D x = D 2 + D 3 FIGURE 4.23 y = D 3 + D D Four-input priority encoder 2 Prof. Wangrok Oh(CNU) Encoders 53 / 93 D 2

Multiplexer to select a particular AND gate. The outputs of the AND gates are applied to a single OR gate that provides the one-line output. The function table lists the input that is passed to the output for each combination of the binary selection values. To demonstrate the operation of the circuit, consider the case when S S =. The AND gate associated with input I 2 has two of its inputs equal to and the third input connected to I 2. The other three AND gates have at least one input equal to, which makes their outputs equal to. The output of the OR gate is now equal to the value of I Multiplexer: Combinational circuit selects one of many 2, providing a path input lines from the selected input to the output. A multiplexer is also called a data selector, since and directs it selects it toone a of single many inputs output and steers linethe binary information to the output line. The AND gates and inverters in the multiplexer resemble a decoder circuit, and indeed, Selection they decode is controlled by a set of selection lines Normally, 2 n the selection input lines. In general, a 2 n -to--line multiplexer is constructed from an n -to-2 input n decoder lines by adding and 2 n input selection lines to it, lines one to each AND gate. The outputs of the AND gates are applied to a single OR gate. The size of a multiplexer is specified by Two-to-one-line multiplexer I I Y I MUX Y I S (a) Logic diagram S (b) Block diagram FIGURE 4.24 Two-to-one-line multiplexer Multiplexer acts like an electronic switch that selects one of two sources Multiplexer is often labeled MUX in block diagrams Prof. Wangrok Oh(CNU) Multiplexer 54 / 93

Multiplexer Four-to-one-line multiplexer Section 4. Multiplexers 59 I I Y I 2 I 3 S S Y S S (a) Logic diagram I I I 2 I 3 (b) Function table FIGURE 4.25 Prof. Wangrok Four-to-one-line Oh(CNU) multiplexer Multiplexer 55 / 93

Multiplexer Multiplexer is also called a data selector Multiple-bit 6 Chapter selection 4 Combinational logic Logic A Y A Y A 2 Y 2 A 3 Y 3 B B B 2 E S Output Y X all s select A select B Function table B 3 S (select) E (enable) FIGURE 4.26 Prof. Wangrok Oh(CNU) Quadruple two-to-one-line multiplexer Multiplexer 56 / 93

Multiplexer Boolean Function Implementation Decoder can be used to implement Boolean functions by employing external OR gates (Refer to P. 47-5) Multiplexer is essentially a decoder that includes the OR gate within the unit Minterms are generated in a multiplexer by the circuit associated with the selection inputs Individual minterms can be selected by the data inputs Boolean function of n variables can be implemented with a multiplexer that has n selection inputs and 2 n data inputs Actually, n variables Boolean function can be implemented with an (n ) selection input multiplexer The first n variables of the function are connected to the selection inputs of the multiplexer The remaining single variable of the function is used for the data inputs Prof. Wangrok Oh(CNU) Multiplexer 57 / 93

ables in the table are applied to the selection inputs of the multiplexer. For each combination of the selection variables, we evaluate the output as a function of the last variable. This function can be,, the variable, or the complement of the variable. These values are then applied to the data inputs in the proper order. As a second example, consider the implementation of the Boolean function Multiplexer Example (F (x, y, z) = (, 2, 6, 7)) F (A, B, C, D) = (, 3, 4,, 2, 3, 4, 5) This function is implemented with a multiplexer with three selection inputs as shown in Fig. 4.28. Note that the first variable A must be connected to selection input S 2 so that A, B, and C correspond to selection inputs S 2, S, and S, respectively. The values for the This function of three variables can be implemented with a four-to-one-line multiplexer 4 MUX x y z F F z y x S S F z F F z z 2 3 F (a) Truth table FIGURE 4.27 Implementing a Boolean function with a multiplexer (b) Multiplexer implementation Prof. Wangrok Oh(CNU) Multiplexer 58 / 93

Multiplexer General Procedure Make a truth table for a Boolean function 2 First (n ) variables in the table are applied to the selection inputs 3 For each combination of the selection variables, we evaluate the output as a function of the last variable This function can be,, the variable, or the complement of the variable 4 These values are then applied to the data inputs in the proper order Prof. Wangrok Oh(CNU) Multiplexer 59 / 93

Multiplexer Example (F (A, B, C, D) = (, 3, 4,, 2, 3, 4, 5)) This function is implemented with a multiplexer with three selection inputs 62 Chapter 4 Combinational Logic data inputs are determined from the truth table listed in the figure. The corresponding S S S 2 2 3 4 5 6 7 8 MUX F C B A D A B C D F F D F D F D F F F D F F FIGURE 4.28 Implementing a four-input function with a multiplexer Prof. Wangrok Oh(CNU) Multiplexer 6 / 93

Multiplexer Tree-State Gates Three-state gate: Digital circuits that exhibit three states (, and High-impedance state) High-impedance state Logic behaves like an open circuit which means that the output appears to be disconnected Circuit has no logic significance Circuit connected to the output of the three-state gate is not affected by the inputs to the gate Three-state buffer gate Section 4. Multiplexers 63 Normal input A Output Y A if C High-impedance if C Control input C FIGURE 4.29 The high-impedance state provides a special feature not available in Graphic symbol for a three-state buffer other gates Several three-state gate outputs can be connected with wires to form a common line without endangering loading input is effects, the output is disabled and the gate goes to a high-impedance state, regardless of the value in the normal input. The high-impedance state of a three-state gate provides a special feature not available in other gates. Because of this feature, a large number o Prof. Wangrok Oh(CNU) Multiplexer 6 / 93

Multiplexer buffers and an inverter. The two outputs are connected together to form a single output line. (Note that this type of connection cannot be made with gates that do not have three-state outputs.) When the select input is, the upper buffer is enabled by its control input and the lower buffer is disabled. Output Y is then equal to input A. When the select input is, the lower buffer is enabled and Y is equal to B. The construction of a four-to-one-line multiplexer is shown in Fig. 4.3(b). The outputs of 4 three-state buffers are connected together to form a single output line. The control inputs to the buffers determine which one of the four normal inputs I through Construction of multiplexers with three-state buffers I Y I I 2 A Y I 3 B Select Select Enable S S EN 2 4 decoder 2 3 (a) 2-to--line mux FIGURE 4.3 Multiplexers with three-state gates (b) 4-to--line mux Prof. Wangrok Oh(CNU) Multiplexer 62 / 93

HDL Models of Combinational Circuits Module is the basic building block for modeling hardware with the Verilog HDL The logic of a module can be described in any one (or a combination) of the following modeling styles Gate-level modeling using instantiations of predefined and user-defined primitive gates Describing a circuit by specifying its gates and how they are connected with each other 2 Dataflow modeling using continuous assignments with the keyword assign Used mostly for describing the Boolean equations of combinational logic 3 Behavioral modeling using procedural assignments with the keyword always Used to describe combinational and sequential circuits at a higher level of abstraction 4 Switch-level modeling Prof. Wangrok Oh(CNU) HDL Models of Combinational Circuits 63 / 93

HDL Models of Combinational Circuits Gate-Level Modeling Gate-level modeling provides a textual description of a schematic diagram Verilog HDL includes 2 basic gates as predefined primitives Four of the primitive gates are of the three-state type and, nand, or, nor, xor, xnor, not and buf Logic of each gate is based on a four-valued system Logic value Logic value Unknown: Denoted by x High impedance: Denoted by z Four-valued logic truth tables for the and, or, xor and not primitive Prof. Wangrok Oh(CNU) HDL Models of Combinational Circuits 64 / 93

HDL Models 66 Chapter of4 Combinational Logic Circuits Table 4.9 Truth Table for Predefined Primitive Gates and x z or x z x x x x x x x x x x x x z x x x z x x x xor x z not input output x x x x x x x x x x x z x x x x z x Truth table for the other four gates is the same except that the outputs instantiate are the complemented gate. Think of instantiation as the HDL counterpart of placing and connecting parts on a circuit board. When We now a primitive present two gate examples is listed of gate-level in a module, modeling. we Both say examples that it use isidentifiers instantiated having multiple inbit the widths, module called vectors. The syntax specifying a vector includes within Insquare general, brackets component two numbers instantiations separated with a are colon. statements The following that Verilog reference statements specify two vectors: lower level components in the design, essentially creating unique copies output (or[: instances) 3] D; of those components in the higher level module wire [7: ] SUM; The first statement declares an output vector D with four bits, through 3. The second declares a wire vector SUM with eight bits numbered 7 through. ( Note : The first (left- Prof. Wangrok Oh(CNU) HDL Models of Combinational Circuits 65 / 93

HDL Models of Combinational Circuits Module that uses a gate in its description is said to instantiate the gate Think of instantiation as the HDL counterpart of placing and connecting parts on a circuit board Specifying a vector output [:3] D; 2 wire [7:] SUM ; Statement in Line declares an output vector D with four bits, through 3 Statement in Line 2 declares a wire vector SUM with eight bits numbered 7 through Note that the first (left- most) number (array index) listed is always the most significant bit of the vector The individual bits are specified within square brackets: D[2] specifies bit 2 of D It is also possible to address parts (contiguous bits) of vectors: SUM[2:] specifies the three least significant bits of vector SUM Prof. Wangrok Oh(CNU) HDL Models of Combinational Circuits 66 / 93

HDL Models of Combinational Circuits // Gate - level description of 2- to -4 - line decoder 2 // See Fig. 4-9. Note : The figure uses symbol E, but the 3 // Verilog model uses enable to clearly indicate functionality. 4 5 module decoder_2x4_gates (D, A, B, enable ); 6 output [:3] D; 7 input A, B; 8 input enable ; 9 wire A_not, B_not, enable_not ; not G ( A_not, A), 2 G2 ( B_not, B), 3 G3 ( enable_not, enable ); 4 nand 5 G4 ( D[], A_not, B_not, enable_not ), 6 G5 ( D[], A_not, B, enable_not ), 7 G6 ( D[2], A, B_not, enable_not ), 8 G7 ( D[3], A, B, enable_not ); 9 endmodule Prof. Wangrok Oh(CNU) HDL Models of Combinational Circuits 67 / 93

HDL Models of Combinational Circuits D A B D D 2 E A B D D D 2 D 3 X X E D 3 Two or more modules can be combined to build a hierarchical description of a design Two basic types of design methodologies Top down 2 Bottom up Top-down design: Top-level block is defined and then the subblocks necessary to build the top-level block are identified Prof. Wangrok Oh(CNU) HDL Models of Combinational Circuits 68 / 93

HDL Models of Combinational Circuits Bottom-up design: Building blocks are first identified and then combined to build the top-level block // Gate - level description of 4- bit 2 // ripple - carry adder 3 // Description of half adder 4 5 module half_adder ( output S, C, input x, y); 6 // Instantiate primitive gates 7 xor (S, x, y); 8 and (C, x, y); 9 endmodule module full_adder ( output S, C, input x, y, z); 2 wire S, C, C2; 3 4 // Instantiate half adders 5 half_adder HA ( S, C, x, y); 6 half_adder HA2 (S, C2, S, z); 7 or G (C, C2, C); 8 endmodule 9 2 // Description of 4- bit adder ( see Fig 4-9) Prof. Wangrok Oh(CNU) HDL Models of Combinational Circuits 69 / 93

HDL Models of Combinational Circuits 2 module ripple_carry_4_bit_adder ( output [3:] Sum, output C4, input [3:] A, B, input C); 22 wire C, C2, C3; // Intermediate carries 23 // Instantiate chain of full adders 24 full_adder FA ( Sum [], C, A[], B[], C), 25 FA ( Sum [], C2, A[], B[], C), 26 FA2 ( Sum [2], C3, A[2], B[2], C2), 27 FA3 ( Sum [3], C4, A[3], B[3], C3); 28 endmodule Module definition cannot be inserted into the text between the module and endmodule of another module Prof. Wangrok Oh(CNU) HDL Models of Combinational Circuits 7 / 93

As mentioned in Section 4., a three-state gate has a control input that can place the gate into a high-impedance state. The high-impedance state is symbolized by z in Verilog. There are four types of three-state gates, as shown in Fig. 4.32. The bufif gate behaves like a normal buffer if control =. The output goes to a high-impedance state z when control =. The bufif gate behaves in a similar fashion, except that the high-impedance Tree-state occurs Gates when control =. The two notif gates operate in a similar manner, except that the output is the complement of the input when the gate is not in a high-impedance state. Three-state The gates are gate instantiated has a control with the input statement that can place the gate into a high-impedance state gate name output, input, control2; The high-impedance state is symbolized by z in Verilog Four types of three-state gates HDL Models of Combinational Circuits in out in out control bufif control bufif in out in out control control notif notif FIGURE 4.32 Three-state The outputs gates of three-state gates can be connected together to form a common output line Verilog HDL uses the keyword tri Prof. Wangrok Oh(CNU) HDL Models of Combinational Circuits 7 / 93

endmodule HDL Models of Combinational Circuits The 2 three-state buffers have the same output. In order to show that they have a common connection, it is necessary to declare m_out with the keyword tri. Keywords wire and tri are examples of a set of data types called nets, which represent connections between hardware elements. In simulation, their value is determined by a // Mux with three - state output continuous assignment 2 modulestatement mux_tri or by ( m_out the device, A, whose B, select output ); they represent. The word net is not a keyword, 3 output but represents m_out ; a class of data types, such as wir e, wor, wand, tri, supply, and supply. 4 input The wire A, declaration B, select is used ; most frequently. In fact, if an identifier is used, but not 5 declared, tri the language m_out ; specifies that it will be interpreted (by default) as a wire. The net 6 wor models the hardware implementation of the wired-or configuration 7 (emitter-coupled logic). bufif The ( wand m_out models, A, the select wired-and ); configuration (open-collector 8 bufif ( m_out, B, select ); technology; see Fig. 3.26 ). The nets supply a n d supply re p re s e n t p o w e r s u p p l y a n d 9 endmodule ground, respectively. They are used to hardwire an input of a device to either or. A m_out B select FIGURE 4.33 Keywords wire and tri are examples of a set of data types called nets Two-to-one-line multiplexer with three-state buffers which represent connections between hardware elements Prof. Wangrok Oh(CNU) HDL Models of Combinational Circuits 72 / 93