MICROPROCESSORS The 8086/8088, 80186/80286, 80386/80486 and the Pentium Family Nilesh B. Bahadure Reader Department of Electronics and Telecommunication Engineering Bhilai Institute of Technology, Durg PHI Learning Private Limited New Delhi-110001 2010
MICROPROCESSORS: The 8086/8088, 80186/80286, 80386/80486 and the Pentium Family Nilesh B. Bahadure 2010 by PHI Learning Private Limited, New Delhi. All rights reserved. No part of this book may be reproduced in any form, by mimeograph or any other means, without permission in writing from the publisher. ISBN-978-81-203-3942-2 The export rights of this book are vested solely with the publisher. Published by Asoke K. Ghosh, PHI Learning Private Limited, M-97, Connaught Circus, New Delhi-110001 and Printed by Baba Barkha Nath Printers, Bahadurgarh, Haryana-124507.
To My Parents Smt. Kamal B. Bahadure and Shri Bhaskarrao M. Bahadure and to my wife Shilpa N. Bahadure
Contents Preface... xix 1. Introduction... 1 5 1.1 History of Computers 1 1.2 Block Diagram of a Microcomputer 2 1.3 Microprocessors: History and Information 3 1.4Intel 80 86 Evolutions 5 2. Architecture and Functional Block Diagram of Microprocessor 8086... 6 41 2.1 Features of 16-Bit HMOS Microprocessor 6 2.2 Pin Configuration of Microprocessor 8086 7 2.2.1 Common Pins 8 2.2.2 Minimum Mode Pins of Microprocessor 8086 12 2.2.3 Maximum Mode Pins of Microprocessor 8086 15 2.3 Architecture of Microprocessor 8086 17 2.3.1 General Purpose Registers 19 2.3.2 Operand Register or Temporary Registers 20 2.3.3 Arithmetic Logic Unit (ALU) 20 2.3.4Flag Registers 20 2.4Instruction Queue and Pipelining 23 2.5 Segmentation of Memory Used with 8086 24 2.6 Methods of Generating Physical Address in Microprocessor 8086 26 v
vi Contents 2.7 Memory Pointers 27 2.7.1 IP (Instruction Pointer) Register 27 2.7.2 SP (Stack Pointer) Register 28 2.7.3 BP (Base Pointer) Register 28 2.7.4BX (Base), SI (Source Index) and DI (Destination Index) registers 29 2.7.5 Use of SI and DI in String Instruction 29 2.8 Default and Specified Segment Registers of Memory Pointers 31 2.9 Addressing Modes of Microprocessor 8086 31 2.10 8088 8-bit Microprocessor 37 2.10.1 Pin Configuration of 8088 Microprocessor 37 2.10.2 Architecture of Microprocessor 8088 38 2.10.3 Differences between Microprocessor 8086 and 8088 39 Review Questions 40 3. Instruction Sets and Programming of Microprocessor 8086... 42 123 3.1 Introduction 42 3.2 Data Transfer Instructions 43 3.2.1 MOV D, S (Move Source Data into Destination) 43 3.2.2 XCHG D, S (Exchange the Content of Destination and Source) 45 3.2.3 LAHF (Load AH Register with 8 LSBs of Flag Register) 45 3.2.4SAHF (Store Register AH into 8 LSBs of Flag Register) 45 3.2.5 LDS R, Mem [Load DS (Data Memory Segment) and Given Register R (16 bit Register) with Memory Contents] 46 3.2.6 LES R, Mem [Load ES (Data Memory Segment) and Given Register R (16-bit Register) with Memory Contents] 47 3.2.7 LEA R, EA Source (Load Effective Address of Memory into Given Register R) 47 3.2.8 XLAT/XLATB (Translate/Translate Byte) 48 3.3 Stack Instructions 50 3.3.1 Initialization of Stack Memory Segment 50 3.3.2 Saving Useful Data of Register into Stack Memory Location 50 3.3.3 Transferring Back Data from Stack Memory Location to Corresponding Destination Instruction Used is POP D (16 bits) 52 3.4Input and Output Instructions 54 3.4.1 IN AL/AX, 8-bit Port Address/DX 54 3.4.2 OUT 8-bit Port Address/DX, AL/AX 55 3.5 Arithmetic Instructions 56 3.5.1 ADD D, S (Add Destination and Source Data) 56 3.5.2 ADC D, S (Add Destination and Source Data with Carry) 57 3.5.3 DAA 58 3.5.4AAA (ASCII Adjust after Addition) 59 3.5.5 SUB D, S (Subtract Source Data from the Destination Data) 61
Contents vii 3.5.6 SBB D, S (Subtract the Content of Source with Borrow from the Content of Destination) 61 3.5.7 DAS (Decimal Adjust after Subtraction) 62 3.5.8 AAS (ASCII Adjusts after Subtraction) 63 3.5.9 CMP D, S (Compare Destination and Source Data) 64 3.5.10 INC D (Increment the Content of Destination) 65 3.5.11 DEC D (Decrement the Content of Destination) 66 3.5.12 NEG D [Negate (Negative) Contents of Destination] 67 3.5.13 CBW (Convert Sign Byte into Sign Word) 67 3.5.14CWD (Convert Sign Word into Sign Double Word) 68 3.6 Multiplication Instructions 68 3.6.1 Unsigned Number Multiplication 68 3.6.2 Signed Number Multiplication 70 3.7 Division Instructions 72 3.7.1 Unsigned Number Division 72 3.7.2 Signed Number Division 74 3.8 Logical Instructions 77 3.8.1 AND D, S (AND Destination and Source Data) 78 3.8.2 TEST D, S (AND Destination and Source Data) 79 3.8.3 OR D, S (OR Destination and Source Data) 79 3.8.4XOR D, S (XOR Destination and Source Data) 80 3.8.5 ROL D, Count (Rotate Left Destination without Carry) 81 3.8.6 RCL D, Count (Rotate Left Destination with Carry) 82 3.8.7 ROR D, Count (Rotate Right Destination without Carry) 82 3.8.8 RCR D, Count (Rotate Right Destination through Carry) 83 3.8.9 SAL/SHL D, Count (Shift Arithmetic Left/Shift Logical Left Destination Data and Put Zeros in the LSBs) 83 3.8.10 SHR D, Count (Shift Logical Right Destination Data and Put Zeros into MSBs) 85 3.8.11 SAR D, Count (Shift Arithmetic Right Destination Data and Put MSBs Bit into MSBs Itself) 86 3.8.12 NOT D (Note Destination Data) 87 3.9 Flags Controlling Instructions 88 3.9.1 STC (Set Carry Flag) 88 3.9.2 STD (Set Direction Flag) 88 3.9.3 STI (Set Interrupt Flag) 88 3.9.4CLC (Clear Carry Flag) 88 3.9.5 CLD (Clear Direction Flag) 88 3.9.6 CLI (Clear Interrupt Flag) 89 3.9.7 CMC (Complements the Carry Flag) 89 3.10 String Instructions 90 3.10.1 REP (Unconditional Repeat) 90 3.10.2 REPZ/REPE (Repeat if Result is Zero/Repeat if Equal) 90 3.10.3 REPNZ/REPNE (Repeat if Result is not Zero/Repeat if not Equal) 91 3.10.4Loop Label 92
viii Contents 3.10.5 LOOPZ/LOOPE LABEL (Loop If Result is Zero/Loop If Equal) 93 3.10.6 LOOPNZ/LOOPNE LABEL (Loop If Result is not Zero/Loop If not Equal) 94 3.10.7 MOVSB/MOVSW (Move String Byte/Move String Word) 95 3.10.8 LODSB/LODSW (Load String Byte in Register AL or String Word into Register AX) 98 3.10.9 STOSB/STOSW (Store String Byte or Store String Word) 102 3.10.10 SCASB/SCASW (Scan a String Byte or a String Word) 105 3.10.11 CMPSB/CMPSW (Compare String Byte or Compare String Word) 107 3.11 Branching Instructions 110 3.11.1 Addressing Modes of Branching Instructions 112 3.11.2 Types of Branching Instructions 114 3.12 External Syncronization and Machnine Control Instructions 120 3.12.1 NOP (No Operation) 120 3.12.2 HLT (Halt Processing) 120 3.12.3 WAIT (Wait for Test Signal or Interrupt Signal) 120 3.12.4LOCK (Lock the Bus Signals) 120 3.12.5 ESC (Escape) 121 Review Questions 122 4. Assembly Language Programming of Microprocessor 8086...124 154 4.1 Introduction to the Programming Languages 124 4.1.1 Machine Language or Low-level Language 124 4.1.2 Hexadecimal Language 125 4.1.3 Assembly Language 125 4.1.4 High-level Language 126 4.2 Assembler Directives or (Pseudoinstructions) 126 4.2.1 DB (Define Byte) 126 4.2.2 DW (Define Word) 127 4.2.3 DD (Define Double Word) 128 4.2.4 DQ (Define Quad Word) 128 4.2.5 DT (Define Ten Bytes) 129 4.2.6 ASSUME 129 4.2.7 SEGMENT and ENDS 130 4.2.8 ORG (Originate) 130 4.2.9 END 131 4.2.10 EQU 132 4.2.11 Short, Near, Far 132 4.2.12 LABEL 132 4.2.13 LENGTH 132 4.2.14 PROC and ENDP 133 4.2.15 USES 133 4.2.16 PTR 133 4.2.17 EVEN or ALIGN2 134
Contents ix 4.2.18 ALIGN4 134 4.2.19 PUBLIC and EXTRN 134 4.2.20 OFFSET 135 4.3 Programming 135 Review Questions 153 5. Interrupts of Microprocessor 8086...155 160 5.1 Basics of Interrupts 155 5.2 Software Interrupt of Microprocessor 8086 156 5.2.1 Vector Interrupt Table (VIT) or Interrupt Vector Table (IVT) 157 5.2.2 Classification of INTn Instruction 158 5.3 Hardware Interrupts of Microprocessor 8086 159 5.3.1 NMI 159 5.3.2 INTR 160 5.4Differences between Software and Hardware Interrupt 160 Review Questions 160 6. Memory Interfacing with Microprocessors 8086 and 8088...161 219 6.1 Semiconductor Memory Fundamentals 161 6.2 Memory Types 162 6.3 RAM Memory Types 162 6.4Standard EPROM ICs 163 6.5 Standard SRAM ICs 163 6.6 Standard DRAM ICs 164 6.7 Memory Structure and Its Requirement 165 6.7.1 Physical Structure of Practical Memory ICs 166 6.8 Basic Concepts of Memory Interfacing 166 6.9 Memory Decoding 167 6.9.1 Absolute or Full Decoding 167 6.9.2 Linear or Partial Decoding 168 6.10 Supporting Circuits Used for the Interfacing 168 6.10.1 8284 Clock Generator 168 6.10.2 8288 Bus Controller 172 6.10.3 8289 Bus Arbiter 176 6.10.48282 Latch 182 6.10.5 74LS138 3-to-8 Line Decode/Demultiplexer 182 6.10.6 Programmable Array Logic (PAL) or Programmable Logic Array (PLA) 183 6.11 Available Programmable Arrays Logics (PALs) 187 6.12 Memory Mapping with Microprocessor 8088 188 6.13 Memory Mapping with Microprocessor 8086 200 Review Questions 219
x Contents 7. Timing Diagram of Microprocessor 8086...220 233 7.1 Minimum and Maximum Modes of Operation 220 7.2 Bus Operation 222 7.3 I/O Addressing 224 7.4ALE (Address Latch Enable) 224 7.5 Timing Diagram of Opcode Fetch, Memory/IO Read, Memory/IO Write in Minimum and Maximum Modes 225 7.5.1 Timing Diagram or Bus Cycle or Machine Cycle of Read (Memory/IO) of Minimum Mode (or) Opcode Fetch/Memory Read/IO Read Machine Cycle of 8086 in Minimum Mode 225 7.5.2 Timing Diagram or Bus Cycle or Machnine Cycle of Read (Memory/IO) of Minimum Mode with One Wait State 226 7.5.3 Opcode Fetch/Memory Read/IO Read Machine Cycle of 8086 in Maximum Mode 227 7.5.4 Memory Write/IO Write Machine Cycle of 8086 in Minimum Mode 229 7.5.5 Memory Write/IO Write Machine Cycle of 8086 in Minimum Mode with One Wait State 230 7.5.6 Memory/IO Write Machine Cycle of 8086 in Maximum Mode Bus Write Cycle (Memory or I/O) 230 7.5.7 Interrupt Acknowledge Machine Cycle 231 Review Questions 233 8. Numeric Data Processor 8087...234 265 8.1 Features of 8087 Math Coprocessor 234 8.2 Architecture of 8087 Math Coprocessor 235 8.3 Pin Configuration of 8087 Math Coprocessor 236 8.4Status Register of 8087 Math Coprocessor 241 8.5 Tag Word Register of 8087 Coprocessor 243 8.6 Control Register of 8087 Math Coprocessor 243 8.7 Interfacing of 8087 Coprocessor with 8086/8088 Microprocessor 245 8.8 Synchronization or Cooperation of Coprocessor 8087 with Main Host Processor 8086/8088 247 8.8.1 Program Execution of 8086 and 8087 247 8.8.2 Data Transfer between 8087 and Memory 247 8.8.3 Operation of Coprocessor when Request Signal RQ is Given by Some Other Local Bus Master 248 8.8.4Operation of Busy and Test Pins or Wait Operation 248 8.9 Instruction Sets of 8087 Coprocessor 249 8.9.1 Data Transfer Instructions 249 8.9.2 Constant Data Transfer Instruction 250 8.9.3 Arithmetic Instructions 251 8.9.4Comparison Instruction 254 8.9.5 Transcendental Instructions 256 8.9.6 Processor Control Instructions 256
Microprocessors : The 8086/8088,80186/80286,80386/80486 And The Pentium Family 25% OFF Publisher : PHI Learning ISBN : 97881203394 22 Author : BAHADURE, NILESH B. Type the URL : http://www.kopykitab.com/product/7335 Get this ebook