COMPUTER ORGANIZATION AND DESIGN

COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 1 Computer Abstractions and Technology

Course Information Prerequisite: CprE 288 Course Description: (3-2) Cr. 4. Introduction to computer organization, evaluating performance of computer systems, instruction set design. Assembly level programming: arithmetic operations, control flow instructions, procedure calls, stack management. Processor design. Datapath and control, scalar pipelines, introduction to memory and I/O systems. Chapter 1 Computer Abstractions and Technology 2

Course Information Lectures: MWF 9:00-9:50, Gilman 1352 Class attendance is not required but encouraged Weekly lab, Coover 2050 There are ten lab sections, 2 hours each The first lab starts next week (Aug 28) Lab 1 will be posted within next 1-2 days The labs will be pre-posted; subject to changes Chapter 1 Computer Abstractions and Technology 3

Syllabus Course syllabus is posted online http://class.ee.iastate.edu/cpre381/syllabu s.asp Class website http://class.ee.iastate.edu/cpre381/ Or Google CPRE 381 Chapter 1 Computer Abstractions and Technology 4

Course Goals To learn the principles of computer architecture using solid engineering fundamentals and quantitative cost/performance tradeoffs. To understand the performance, cost and power aspects of computer systems. To comprehend the design of instruction set architecture, computer arithmetic, CPUs, memories, and storage and I/Os. Chapter 1 Computer Abstractions and Technology 5

Course Goals For future software designers, to understand how the basic hardware techniques work in a system. For future hardware designers, to understand how new hardware designs may affect software systems. Chapter 1 Computer Abstractions and Technology 6

Learning Objectives By the end of this course, you should be able to Quantitatively analyze the performance/power optimization of computer systems and understand the Amdahl's Law Program in MIPS assembly language and understand how C program is translated into MIPS assembly code Design integer arithmetic and logic units, and understand how floating-point units work Chapter 1 Computer Abstractions and Technology 7

Learning Objectives (Continue) Design single-cycle processor including its control and datapath Design in-order processor pipeline with handling of control and data hazards Understand cache and main memory systems Understand storage systems and I/O Chapter 1 Computer Abstractions and Technology 8

Textbook, Ref, and On-Line Textbook Computer Organization and Design: The Hardware/Software Interface, 5th edition, D. A. Patterson and J. L. Hennessy, Morgan Kaufmann Publishers, Inc., 2013 Reference Books: VHDL Tutorial, Peter J. Ashenden, on the companion CD of the textbook. The Designer's Guide to VHDL, 2nd Edition, Peter J. Ashenden, Morgan Kaufman Publishers.

Textbook, Ref, and On-Line Class website http://class.ee.iastate.edu/cpre381/ Check regularly for readings, lecture notes, lab assignments and course announcements Textbook companion site http://www.elsevierdirect.com/v2/companion.js p?isbn=9780124077263 The CD contents are posted online

Textbook, Ref, and On-Line Canvas Homework assignments and submission Online discussions All grades Chapter 1 Computer Abstractions and Technology 11

Instructors and TAs Instructor: Akhilesh Tyagi Office: 2210 Coover Office Hours:TBA, by appointment Contact: tyagi@iastate.edu Teaching assistants Ala Ghazo alghazo@iastate.edu Shaikh-Mohammed, Ashraf ashraf@iastate.edu Chandramoorthy, Sunantha Rini sunantha@iastate.edu Matt Kelley, mkelly2@iastate.edu Aggarwal, Jevay jaggar@iastate.edu Zhao, Zhenyu <zzyjason@iastate.edu> Office hours TBD

Grading Homework 11% Labs and Mini-projects 35% Midterm Exam I 18% (Oct 8) Midterm Exam II 18% (Nov 12) Midterm III/Final Exam 18% (Dec 11 7:30AM)

Labs and Projects Lab location: Coover 2050 You will work with partner(s) There will be four lab assignments and three mini-projects Labs will be done using VHDL A VHDL tutorial is provided on the textbook CD For e-book users, CD contents are available online Lab attendance is mandatory: No attendance, zero point fail the course The last mini-project will be due in the dead week

My Expectations of you Commitment to learn put in requisite effort Seek help when having trouble Honesty do not submit someone else s work as your own Maintain respectful environment in the classroom and lab No unrelated conversations Do not make comments/conversations to make any group uncomfortable gender, racial, ethnic, national origin Chapter 1 Computer Abstractions and Technology 15

My Expectations of me Make an effort to understand your learning styles and adapt to it Be available Be respectful provide conducive learning environment Be fair in all my dealings with you Chapter 1 Computer Abstractions and Technology 16

The Computer Revolution Progress in computer technology Underpinned by Moore s Law Makes novel applications feasible Computers in automobiles Cell phones Human genome project World Wide Web Search Engines Computers are pervasive 1.1 Introduction Chapter 1 Computer Abstractions and Technology 17

CPU Performance Performance = highest SPECInt by year; from Hennessy & Patterson [2018]. 5

Classes of Computers Personal computers General purpose, variety of software Subject to cost/performance tradeoff Server computers Network based High capacity, performance, reliability Range from small servers to building sized Chapter 1 Computer Abstractions and Technology 19

Classes of Computers Supercomputers High-end scientific and engineering calculations Highest capability but represent a small fraction of the overall computer market Embedded computers Hidden as components of systems Stringent power/performance/cost constraints Chapter 1 Computer Abstractions and Technology 20

The PostPC Era 1.54 billion in 2017 262 million in 2017 millions Chapter 1 Computer Abstractions and Technology 21

The PostPC Era Personal Mobile Device (PMD) Battery operated Connects to the Internet Hundreds of dollars Smart phones, tablets, electronic glasses Cloud computing Warehouse Scale Computers (WSC) Software as a Service (SaaS) Portion of software run on a PMD and a portion run in the Cloud Amazon and Google Chapter 1 Computer Abstractions and Technology 22

What You Will Learn How programs are translated into the machine language And how the hardware executes them The hardware/software interface What determines program performance And how it can be improved How hardware designers improve performance What is parallel processing Chapter 1 Computer Abstractions and Technology 23

Understanding Performance Algorithm Determines number of operations executed Programming language, compiler, architecture Determine number of machine instructions executed per operation Processor and memory system Determine how fast instructions are executed I/O system (including OS) Determines how fast I/O operations are executed Chapter 1 Computer Abstractions and Technology 24

Eight Great Ideas Design for Moore s Law Use abstraction to simplify design Make the common case fast Performance via parallelism Performance via pipelining Performance via prediction Hierarchy of memories 1.2 Eight Great Ideas in Computer Architecture Dependability via redundancy Chapter 1 Computer Abstractions and Technology 25

Below Your Program Application software Written in high-level language System software Compiler: translates HLL code to machine code Operating System: service code Handling input/output Managing memory and storage Scheduling tasks & sharing resources Hardware Processor, memory, I/O controllers 1.3 Below Your Program Chapter 1 Computer Abstractions and Technology 26

Levels of Program Code High-level language Level of abstraction closer to problem domain Provides for productivity and portability Assembly language Textual representation of instructions Hardware representation Binary digits (bits) Encoded instructions and data Chapter 1 Computer Abstractions and Technology 27

Components of a Computer The BIG Picture Same components for all kinds of computer Desktop, server, embedded Input/output includes User-interface devices Display, keyboard, mouse Storage devices Hard disk, CD/DVD, flash Network adapters For communicating with other computers 1.4 Under the Covers Chapter 1 Computer Abstractions and Technology 28

Touchscreen PostPC device Supersedes keyboard and mouse Resistive and Capacitive types Most tablets, smart phones use capacitive Capacitive allows multiple touches simultaneously Chapter 1 Computer Abstractions and Technology 29

Through the Looking Glass LCD screen: picture elements (pixels) Mirrors content of frame buffer memory Chapter 1 Computer Abstractions and Technology 30

Opening the Box Capacitive multitouch LCD screen 3.8 V, 25 Watt-hour battery Computer board Chapter 1 Computer Abstractions and Technology 31

Inside the Processor (CPU) Datapath: performs operations on data Control: sequences datapath, memory,... Cache memory Small fast SRAM memory for immediate access to data Chapter 1 Computer Abstractions and Technology 32

Inside the Processor Apple A5 Chapter 1 Computer Abstractions and Technology 33

Abstractions The BIG Picture Abstraction helps us deal with complexity Hide lower-level detail Instruction set architecture (ISA) The hardware/software interface Application binary interface The ISA plus system software interface Implementation The details underlying and interface Chapter 1 Computer Abstractions and Technology 34

A Safe Place for Data Volatile main memory Loses instructions and data when power off Non-volatile secondary memory Magnetic disk Flash memory Optical disk (CDROM, DVD) Chapter 1 Computer Abstractions and Technology 35

Networks Communication, resource sharing, nonlocal access Local area network (LAN): Ethernet Wide area network (WAN): the Internet Wireless network: WiFi, Bluetooth Chapter 1 Computer Abstractions and Technology 36

Technology Trends Electronics technology continues to evolve Increased capacity and performance Reduced cost DRAM capacity Year Technology Relative performance/cost 1951 Vacuum tube 1 1965 Transistor 35 1975 Integrated circuit (IC) 900 1995 Very large scale IC (VLSI) 2,400,000 2013 Ultra large scale IC 250,000,000,000 1.5 Technologies for Building Processors and Memory Chapter 1 Computer Abstractions and Technology 37

Semiconductor Technology Silicon: semiconductor Add materials to transform properties: Conductors Insulators Switch Chapter 1 Computer Abstractions and Technology 38

Manufacturing ICs Yield: proportion of working dies per wafer Chapter 1 Computer Abstractions and Technology 39

Intel Core i7 Wafer 300mm wafer, 280 chips, 32nm technology Each chip is 20.7 x 10.5 mm Chapter 1 Computer Abstractions and Technology 40

Integrated Circuit Cost Cost per die = Cost per wafer Dies per wafer Yield Dies per wafer Wafer area Die area Yield = (1+ (Defects per 1 area Die area/2)) 2 Nonlinear relation to area and defect rate Wafer cost and area are fixed Defect rate determined by manufacturing process Die area determined by architecture and circuit design Chapter 1 Computer Abstractions and Technology 41

Defining Performance Which airplane has the best performance? 1.6 Performance Boeing 777 Boeing 777 Boeing 747 BAC/Sud Concorde Douglas DC-8-50 Boeing 747 BAC/Sud Concorde Douglas DC- 8-50 0 100 200 300 400 500 Passenger Capacity 0 2000 4000 6000 8000 10000 Cruising Range (miles) Boeing 777 Boeing 777 Boeing 747 BAC/Sud Concorde Douglas DC-8-50 Boeing 747 BAC/Sud Concorde Douglas DC- 8-50 0 500 1000 1500 Cruising Speed (mph) 0 100000 200000 300000 400000 Passengers x mph Chapter 1 Computer Abstractions and Technology 42

Response Time and Throughput Response time How long it takes to do a task Throughput Total work done per unit time e.g., tasks/transactions/ per hour How are response time and throughput affected by Replacing the processor with a faster version? Adding more processors? We ll focus on response time for now Chapter 1 Computer Abstractions and Technology 43

Relative Performance Define Performance = 1/Execution Time X is n time faster than Y Performance Performance X Y = Execution time Y Execution time X = n Example: time taken to run a program 10s on A, 15s on B Execution Time B / Execution Time A = 15s / 10s = 1.5 So A is 1.5 times faster than B Chapter 1 Computer Abstractions and Technology 44

Measuring Execution Time Elapsed time Total response time, including all aspects Processing, I/O, OS overhead, idle time Determines system performance CPU time Time spent processing a given job Discounts I/O time, other jobs shares Comprises user CPU time and system CPU time Different programs are affected differently by CPU and system performance Chapter 1 Computer Abstractions and Technology 45

CPU Clocking Operation of digital hardware governed by a constant-rate clock Clock (cycles) Data transfer and computation Update state Clock period Clock period: duration of a clock cycle e.g., 250ps = 0.25ns = 250 10 12 s Clock frequency (rate): cycles per second e.g., 4.0GHz = 4000MHz = 4.0 10 9 Hz Chapter 1 Computer Abstractions and Technology 46

CPU Time CPU Time = CPU Clock Cycles Clock Cycle Time = CPU Clock Cycles Clock Rate Performance improved by Reducing number of clock cycles Increasing clock rate Hardware designer must often trade off clock rate against cycle count Chapter 1 Computer Abstractions and Technology 47

CPU Time Example Computer A: 2GHz clock, 10s CPU time Designing Computer B Aim for 6s CPU time Can do faster clock, but causes 1.2 clock cycles How fast must Computer B clock be? Clock Rate B = Clock Cycles CPU Time B B = 1.2 Clock Cycles 6s A Clock Cycles A = CPU Time A Clock Rate A = 10s 2GHz = 20 10 9 Clock Rate B = 1.2 20 10 6s 9 = 24 10 6s 9 = 4GHz Chapter 1 Computer Abstractions and Technology 48

Instruction Count and CPI Clock Cycles = Instruction Count Cycles per Instruction CPU Time = Instruction Count CPI Clock Cycle Time Instruction Count CPI = Clock Rate Instruction Count for a program Determined by program, ISA and compiler Average cycles per instruction Determined by CPU hardware If different instructions have different CPI Average CPI affected by instruction mix Chapter 1 Computer Abstractions and Technology 49

CPI Example Computer A: Cycle Time = 250ps, CPI = 2.0 Computer B: Cycle Time = 500ps, CPI = 1.2 Same ISA Which is faster, and by how much? CPU Time A CPU Time B CPU Time B CPU Time A = Instruction Count CPI A = I 2.0 250ps = I 500ps = Instruction Count CPI B = I 1.2 500ps = I 600ps I 600ps = I 500ps = 1.2 Cycle Time A Cycle Time B A is faster by this much Chapter 1 Computer Abstractions and Technology 50

CPI in More Detail If different instruction classes take different numbers of cycles Clock Cycles = n i= 1 (CPIi Instruction Counti) Weighted average CPI CPI = Clock Cycles Instruction Count = n i= 1 CPI i Instruction Counti Instruction Count Relative frequency Chapter 1 Computer Abstractions and Technology 51

CPI Example Alternative compiled code sequences using instructions in classes A, B, C Class A B C CPI for class 1 2 3 IC in sequence 1 2 1 2 IC in sequence 2 4 1 1 Sequence 1: IC = 5 Clock Cycles = 2 1 + 1 2 + 2 3 = 10 Avg. CPI = 10/5 = 2.0 Sequence 2: IC = 6 Clock Cycles = 4 1 + 1 2 + 1 3 = 9 Avg. CPI = 9/6 = 1.5 Chapter 1 Computer Abstractions and Technology 52

Performance Summary The BIG Picture Instructions Clock cycles CPU Time = Program Instruction Seconds Clock cycle Performance depends on Algorithm: affects IC, possibly CPI Programming language: affects IC, CPI Compiler: affects IC, CPI Instruction set architecture: affects IC, CPI, T c Chapter 1 Computer Abstractions and Technology 53

Power Trends 1.7 The Power Wall In CMOS IC technology Power = Capacitive load Voltage 2 Frequency 40 5V 1V 1000 Chapter 1 Computer Abstractions and Technology 54

Reducing Power Suppose a new CPU has 85% of capacitive load of old CPU 15% voltage and 15% frequency reduction 2 P Cold 0.85 (Vold 0.85) Fold 0.85 4 = = 0.85 2 P C V F new = old The power wall old We can t reduce voltage further We can t remove more heat old How else can we improve performance? old 0.52 Chapter 1 Computer Abstractions and Technology 55

Uniprocessor Performance Constrained by power, instruction-level parallelism, memory latency 1.8 The Sea Change: The Switch to Multiprocessors Chapter 1 Computer Abstractions and Technology 56

Multiprocessors Multicore microprocessors More than one processor per chip Requires explicitly parallel programming Compare with instruction level parallelism Hardware executes multiple instructions at once Hidden from the programmer Hard to do Programming for performance Load balancing Optimizing communication and synchronization Chapter 1 Computer Abstractions and Technology 57

SPEC CPU Benchmark Programs used to measure performance Supposedly typical of actual workload Standard Performance Evaluation Corp (SPEC) Develops benchmarks for CPU, I/O, Web, SPEC CPU2006 Elapsed time to execute a selection of programs Negligible I/O, so focuses on CPU performance Normalize relative to reference machine Summarize as geometric mean of performance ratios CINT2006 (integer) and CFP2006 (floating-point) n n Execution time ratio i i= 1 Chapter 1 Computer Abstractions and Technology 58

CINT2006 for Intel Core i7 920 Chapter 1 Computer Abstractions and Technology 59

SPEC Power Benchmark Power consumption of server at different workload levels Performance: ssj_ops/sec Power: Watts (Joules/sec) Overall ssj_ops per Watt 10 10 ssj_ops i power i= 0 = i= 0 i Chapter 1 Computer Abstractions and Technology 60

SPECpower_ssj2008 for Xeon X5650 Chapter 1 Computer Abstractions and Technology 61

Pitfall: Amdahl s Law Improving an aspect of a computer and expecting a proportional improvement in overall performance T improvement affected T improved = + factor unaffected Example: multiply accounts for 80s/100s How much improvement in multiply performance to get 5 overall? 80 20 = + 20 Can t be done! n T 1.10 Fallacies and Pitfalls Corollary: make the common case fast Chapter 1 Computer Abstractions and Technology 62

Amdahl s Law We know about performance: defining, measuring, and summarizing How to maximize performance gains from the beginning in our design? Principle: Make the Common Case Fast!

Amdahl s Law Predict overall speedup from local speedup by an enhancement, provided the frequency of enhancement use is known. Local speedup is related to design and optimization objectives, like to double CPU frequency, to reduce cache latency by half

Amdahl s Law Execution time new = Execution Time Fraction old ( ) enhanced 1 Fraction + enhanced Speedupenhance Speedup = overall = ( 1- Fraction ) Execution time Execution time enhanced 1 + old new Fraction Speedup enhanced enhanced

Amdahl's Law 12 10 speedup 8 6 4 Series1 2 0 0 0.2 0.4 0.6 0.8 1 f

Fallacy: Low Power at Idle Look back at i7 power benchmark At 100% load: 258W At 50% load: 170W (66%) At 10% load: 121W (47%) Google data center Mostly operates at 10% 50% load At 100% load less than 1% of the time Consider designing processors to make power proportional to load Chapter 1 Computer Abstractions and Technology 67

Pitfall: MIPS as a Performance Metric MIPS: Millions of Instructions Per Second Doesn t account for Differences in ISAs between computers Differences in complexity between instructions MIPS = = Instruction count Execution time 10 Instruction count Instruction count CPI 10 Clock rate 6 6 Clock rate = 6 CPI 10 CPI varies between programs on a given CPU Chapter 1 Computer Abstractions and Technology 68

Concluding Remarks Cost/performance is improving Due to underlying technology development Hierarchical layers of abstraction In both hardware and software Instruction set architecture The hardware/software interface Execution time: the best performance measure Power is a limiting factor Use parallelism to improve performance 1.9 Concluding Remarks Chapter 1 Computer Abstractions and Technology 69