ECE251: Thursday September 27

ECE251: Thursday September 27 Exceptions: Interrupts and Resets Chapter in text and Lab #6. READ ALL this material! This will NOT be on the mid-term exam. Lab Practical Exam #1 Homework # due today at 4:00 Mid-term exam on October 4, next Thursday. Review Tues. Be ready with questions! Practical Exam #1 on week of October 8 in lab Lecture # 1

Previous Homework Question 1. Write an assembly language program that calls a subroutine which replaces all ASCII digits (0-9) of a string with the # symbol. Memory location of the string is passed on the top of the stack. The string is terminated with the null symbol, value =0. Str DCB Te5t Str1ng 0 and 1, #0 main LDR, =Str PUSH {} BL Digit_replace... Lecture # 2

New Topic: Exceptions & Interrupts Exception: A break in normal program flow execution is interrupted by some event, usually external to the CPU. Common Examples of Exceptions: Reset: Power up or warm start NMI: Non-maskable interrupt usually an external NMI signal Memory Management Fault: memory protection violation Usage Fault: undefined instruction, SVCall: Supervisory call SysTick: System Timer (we will cover this in lecture/lab) Interrupt (IRQ): Typically created by peripherals External I/O device (e.g. keyboard, printer) Internal event (e.g. op code fault, timer) See TM4C Data Sheet, Section 2.5 Lecture #

Fundamental Concepts of Interrupts What is an interrupt? A special event that requires the CPU to stop normal program execution and perform some action (service) related to the event. Examples of interrupts include I/O completion and real-time interrupt. Functions of Interrupts - Coordinates I/O activities and prevents CPU from being tied up checking on these activities (polling) - Reminds the CPU to perform routine tasks (real-time interrupt) - Provides a graceful way to exit from errors Interrupt Maskability - Interrupts that can be ignored by the CPU are called maskable interrupts. A maskable interrupt must be enabled before it can interrupt the CPU. An interrupt is enabled by setting an enable flag. - Interrupts that are never ignored by the CPU are called nonmaskable interrupts and include things like special NMI hardware Lecture # 4

Interrupts vs. Polling Polling: Monitoring, waiting for flag to set Program is tied up waiting for flag Inefficient use of processor Easily programmed Interrupt: Processor tells program when event has occurred Program can be executing other tasks Processor can perform activities real-time Analogy: Waiting for incoming phone call. See following slide Lecture # 5

Polling vs. Interrupt Polling: You pick up the phone every few seconds to check whether you are getting a call. Interrupt: Do whatever you need to do and pick up the phone when it rings (or vibrates or ). Lecture # 6

Interrupt Processing Hardware Busy Done Busy Main Thread Interrupt Thread Hardware needs service Saves execution state ISR provides service Restores execution state time Lecture # 7

Interrupt Conditions Five conditions must be true simultaneously for an interrupt to occur: Software 1. Arm: control bit for each possible source is set or armed 2. Enable NVIC: Set NVIC_E register bit appropriately. Enable: interrupts globally enabled (I=0 in PRIMASK) 4. Level: interrupt must be less than BASEPRI (priority higher) 5. Trigger: hardware action sets source-specific flag Interrupt remains pending if trigger is set but any other condition is not true Interrupt serviced once all conditions become true Need to acknowledge interrupt Clear trigger flag or will get endless interrupts! Lecture # 8

What To Do When an Interrupt Occurs? Interrupt Service Routine (ISR): The software routine (subroutine) executed by a processor in response to an interrupt. This is similar to a normal software subroutine with important differences: Method by which system enters the subroutine (interrupt vs BL) What s saved when the subroutine is entered Instructions which complete and exit the subroutine, including restoring what was saved above. Lecture # 9

Interrupt Service Activity A complete interrupt service action includes: 0. Interrupt occurs during an instruction. Instruction is allowed to complete. 1. Saving r0-r,r,lr,pc,psr in the stack. Why do that? 2. LR set to 0xFFFFFFF9 indicating interrupt being serviced. Identifying the cause of interrupt-sets IPSR to interrupt number 4. Determining the starting address of the corresponding Interrupt Service Routine (ISR), based on the interrupt cause and Interrupt Vector Table entry (we will discuss this). 5. Executing this ISR. 6. Finally, executing BX LR, restoring register entries from stack and continuing execution of the interrupted program, exactly where it was interrupted. Lecture # 10

Interrupt Service Responsibilities Processor finishes the current instruction. Processor stores certain register contents on stack. Processor transfers control to ISR associated with that specific interrupt. ISR takes appropriate action including clearing trigger flag When complete, ISR executes BX LR instruction LR has a special meaning here! BX restores register values above BX transfers control to where it left off (next instruction, as if nothing had happened) when the interrupt event occurred Lecture # 11

Stack Activity on ISR Start and Exit Old SP Stack descends In memory. New SP SP + 0x20 SP + 0x1C SP + 0x18 SP + 0x14 SP + 0x10 SP + 0x0C SP + 0x08 SP + 0x04 SP + 0x00 xxxxxxxx xpsp PC (r15) LR (r14) r r r2 r1 r0 The processor automatically pushes these eight registers into the main stack before an interrupt handler starts The processor automatically pops these eight register out of the main stack when an interrupt hander exits using BX LR Lecture #

How does the CPU find the ISR? Interrupt Vector Starting Address of the Interrupt Service Routine. Programmer must initialize this! Interrupt Vector Table A table (in read-only memory) where all interrupt vectors are stored. Method of Determining Interrupt Vectors 1. Fetching the vector from a predefined location in the Interrupt Vector Table. See next slides. Steps of Programming for an Interrupt Step 0. Interrupt vector table entry and ISR loaded into ROM by assembler/linker/loader at location supplied by programmer Step 1. Enable the specific interrupt Step 2. Set NVIC_E register appropriately Step. Enable global Interrupts (PRIMASK = 0) Lecture # 1

Lecture # 14 Interrupt Vector Table

Startup.s to Initialize Interrupt Vector Table EXPORT Vectors Vectors DCD StackMem + Stack ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler DCD BusFault_Handler ; Bus Fault Handler DCD UsageFault_Handler ; Usage Fault Handler DCD 0,0,0,0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD DebugMon_Handler ; Debug Monitor Handler DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler DCD GPIOPortA_Handler ; GPIO Port A DCD GPIOPortB_Handler ; GPIO Port B DCD GPIOPortC_Handler ; GPIO Port C DCD GPIOPortD_Handler ; GPIO Port D DCD GPIOPortE_Handler ; GPIO Port E DCD UART0_Handler ; UART0 Rx and Tx DCD UART1_Handler ; UART1 Rx and Tx Lecture # 15

Interrupt Handling Sequence Lecture # 16

Interrupt Context Switch Assume GPIO Port C Interrupt (#18) I 0 IPSR 0 BASEPRI 0 Before interrupt I 0 RAM Context Switch Finish instruction IPSR 18 a) Push registers b) PC = {0x00000048} BASEPRI 0 c) Set IPSR = 18 d) Set LR = 0xFFFFFFF9 Use as stack pointer Stack After interrupt old old old old old 2 old LR old PC old PSR Stack Vector address for GPIO Port C Interrupt Number 18 corresponds to GPIO Port C Lecture # 17

Overhead Time for Interrupts The interrupt itself causes the saving of 8 CPU registers then branching to the ISR. Plus the execution of the BX LR instruction restoring these same 8 registers and then branching back to the executing program. Plus the execution time of instructions of the interrupt service routine. SO: Keep ISR short if input/output responsiveness or performance is critical (and it often is). Lecture # 18

Stacking & Unstacking ISRs Interrupt Signal Interrupt Handler Interrupt Exit Unstacking User Program User Program Stacking Thread Mode Handler Mode Thread Mode Time Interrupt Handler User Program Lecture # 19

Stack Pointer Registers : Main Stack Pointer. We use only this one in ECE251 PSP: Process Stack Pointer Lecture # 20

Processor Mode: Handler Mode vs Thread Mode Handler mode for processing exceptions always use (Main Stack Pointer) Thread Mode for application software uses in our system so just forget about this! When the processor is reset, the default is the thread mode. The processor enters the handler mode when an interrupt occurs and returns to thread mode when ISR completes. Your program does not need to worry about this. It happens automatically. Not sure why text writers care so much about this. Lecture # 21

Register Values in an Interrupt Service Routine LR = 0xFFFFFFF9! See next slide! SP = ISR always in hander mode. Lecture # 22

Where does processing continue when exiting an interrupt? Link Register (LR) now has two usages! With Subroutine Call, LR = address of the instruction immediately after BL In ISR, LR indicates that the stack is used to restore register from when exiting an interrupt LR value generated by processor The processor sets LR to 0xFFFFFFFF on reset. The processor sets LR to 0xFFFFFFF9 on interrupt. Lecture # 2

EXAMPLE: Interrupt Stacking & Unstacking main PROC addr = 0x08000044 MOV r,#0 addr = 0x0800001C SysTick_Handler PROC EXPORT SysTick_Handler ADD r, #1 ADD r4, #1 BX lr R4 2 (SP) 4(LR) 5(PC) 0 1 2 4 0x08001000 0x08000044 xxxxxxxx 0x200001FC 0x200001F8 0x200001F4 0x200001F0 0x200001EC 0x200001E8 0x200001E4 0x200001E0 0x200001DC 0x200001D8 0x200001D4 0x200001D0 0x200001CF Memory Lecture # 24

EXAMPLE: Interrupt Suppose SysTick Stacking interrupt & Unstacking occurs when PC = 0x08000044 main PROC addr = 0x08000044 MOV r,#0 addr = 0x0800001C SysTick_Handler PROC EXPORT SysTick_Handler ADD r, #1 ADD r4, #1 BX lr R4 2 (SP) 4(LR) 5(PC) 0 1 2 4 0x08001000 0x08000044 xxxxxxxx 0x200001FC 0x200001F8 0x200001F4 0x200001F0 0x200001EC 0x200001E8 0x200001E4 0x200001E0 0x200001DC 0x200001D8 0x200001D4 0x200001D0 0x200001CF Memory Lecture # 25

EXAMPLE: Interrupt Stacking & Unstacking STACKING main PROC addr = 0x08000044 MOV r,#0 addr = 0x0800001C SysTick_Handler PROC EXPORT SysTick_Handler ADD r, #1 ADD r4, #1 BX lr R4 2 (SP) 4(LR) 5(PC) 0 1 2 4 0xFFFFFFF9 0x0800001C PC LR 2 xxxxxxxx 0x08000044 0x08001000 0x200001FC 0x200001F8 0x200001F4 0x200001F0 0x200001EC 2 0x200001E8 1 0x200001E4 0 0x200001E0 0x200001DC 0x200001D8 0x200001E0 0x200001D4 0x200001D0 0x200001CF Memory Lecture # 26

EXAMPLE: Interrupt Stacking & Unstacking STACKING main PROC addr = 0x08000044 MOV r,#0 addr = 0x0800001C SysTick_Handler PROC EXPORT SysTick_Handler ADD r, #1 ADD r4, #1 BX lr R4 2 (SP) 4(LR) 5(PC) 0 1 2 4 0xFFFFFFF9 0x0800001C PC LR 2 xxxxxxxx 0x08000044 0x08001000 0x200001FC 0x200001F8 0x200001F4 0x200001F0 0x200001EC 2 0x200001E8 1 0x200001E4 0 0x200001E0 0x200001DC 0x200001D8 LR = 0xFFFFFFF9 to indicate is used. 0x200001E0 Memory 0x200001D4 0x200001D0 0x200001CF Lecture # 27

Interrupt: Stacking & Unstacking main PROC addr = 0x08000044 MOV r,#0 addr = 0x0800001C SysTick_Handler PROC EXPORT SysTick_Handler ADD r, #1 ADD r4, #1 BX lr R4 2 (SP) 4(LR) 5(PC) 0 1 2 4 4 0xFFFFFFF9 0x0800001C PC LR 2 xxxxxxxx 0x08000044 0x08001000 0x200001FC 0x200001F8 0x200001F4 0x200001F0 0x200001EC 2 0x200001E8 1 0x200001E4 0 0x200001E0 0x200001DC 0x200001D8 0x200001E0 0x200001D4 0x200001D0 0x200001CF Memory Lecture # 28

Interrupt: Stacking & Unstacking main PROC addr = 0x08000044 MOV r,#0 addr = 0x0800001C SysTick_Handler PROC EXPORT SysTick_Handler ADD r, #1 ADD r4, #1 BX lr R4 2 (SP) 4(LR) 5(PC) 0 1 2 4 5 0xFFFFFFF9 0x08000020 PC LR 2 xxxxxxxx 0x08000044 0x08001000 0x200001FC 0x200001F8 0x200001F4 0x200001F0 0x200001EC 2 0x200001E8 1 0x200001E4 0 0x200001E0 0x200001DC 0x200001D8 0x200001E0 0x200001D4 0x200001D0 0x200001CF Memory Lecture # 29

Interrupt: Stacking & Unstacking main PROC addr = 0x08000044 MOV r,#0 addr = 0x0800001C SysTick_Handler PROC EXPORT SysTick_Handler ADD r, #1 ADD r4, #1 BX lr R4 2 (SP) 4(LR) 5(PC) 0 1 2 4 5 0xFFFFFFF9 0x08000024 PC LR 2 xxxxxxxx 0x08000044 0x08001000 0x200001FC 0x200001F8 0x200001F4 0x200001F0 0x200001EC 2 0x200001E8 1 0x200001E4 0 0x200001E0 0x200001DC 0x200001D8 LR = 0xFFFFFFF9 to indicate is used. 0x200001E0 Memory 0x200001D4 0x200001D0 0x200001CF Lecture # 0

Interrupt: Stacking & Unstacking UNSTACKING main PROC addr = 0x08000044 MOV r,#0 addr = 0x0800001C SysTick_Handler PROC EXPORT SysTick_Handler ADD r, #1 ADD r4, #1 BX lr R4 2 (SP) 4(LR) 5(PC) 0 1 2 4 5 0xFFFFFFF9 0x08000024 PC LR 2 xxxxxxxx 0x08000044 0x08001000 0x200001FC 0x200001F8 0x200001F4 0x200001F0 0x200001EC 2 0x200001E8 1 0x200001E4 0 0x200001E0 0x200001DC 0x200001D8 LR = 0xFFFFFFF9 to indicate is used. 0x200001E0 Memory 0x200001D4 0x200001D0 0x200001CF Lecture # 1

Interrupt: Stacking & Unstacking main PROC addr = 0x08000044 MOV r,#0 addr = 0x0800001C SysTick_Handler PROC EXPORT SysTick_Handler ADD r, #1 ADD r4, #1 BX lr R4 2 (SP) 4(LR) 5(PC) 0 1 2 5 0x08001000 0x08000044 xxxxxxxx 0x200001FC 0x200001F8 0x200001F4 0x200001F0 0x200001EC 0x200001E8 0x200001E4 0x200001E0 0x200001DC 0x200001D8 Note the new value of is lost!!! Memory 0x200001D4 0x200001D0 0x200001CF Lecture # 2

Interrupt: Stacking & Unstacking main PROC addr = 0x08000044 MOV r,#0 addr = 0x0800001C SysTick_Handler PROC EXPORT SysTick_Handler ADD r, #1 ADD r4, #1 BX lr R4 2 (SP) 4(LR) 5(PC) 0 1 2 5 0x08001000 0x08000044 xxxxxxxx 0x200001FC 0x200001F8 0x200001F4 0x200001F0 0x200001EC 0x200001E8 0x200001E4 0x200001E0 0x200001DC 0x200001D8 The Main program resumes. Memory 0x200001D4 0x200001D0 0x200001CF Lecture #

Interrupt: Stacking & Unstacking main PROC addr = 0x08000044 MOV r,#0 addr = 0x0800001C SysTick_Handler PROC EXPORT SysTick_Handler ADD r4, #1 BL sine BX lr R4 2 (SP) 4(LR) 5(PC) 0 1 2 4 0x08001000 0x08000044 xxxxxxxx 0x200001FC 0x200001F8 0x200001F4 0x200001F0 0x200001EC 0x200001E8 0x200001E4 0x200001E0 0x200001DC 0x200001D8 0x200001D4 0x200001D0 0x200001CF Memory Lecture # 4

Interrupt: Stacking & Unstacking STACKING main PROC addr = 0x08000044 MOV r,#0 addr = 0x0800001C SysTick_Handler PROC EXPORT SysTick_Handler ADD r4, #1 BL sine BX lr R4 2 (SP) 4(LR) 5(PC) 0 1 2 4 0xFFFFFFF9 0x0800001C PC SP LR xxxxxxxx 0x00000002 0x08001000 0x200001FC 0x200001F8 0x200001F4 0x200001F0 0x200001EC 2 0x200001E8 1 0x200001E4 0 0x200001E0 0x200001DC 0x200001D8 LR = 0xFFFFFFF9 to indicate is used. 0x200001E0 Memory 0x200001D4 0x200001D0 0x200001CF Lecture # 5

Interrupt: Stacking & Unstacking STACKING main PROC addr = 0x08000044 MOV r,#0 addr = 0x0800001C SysTick_Handler PROC EXPORT SysTick_Handler ADD r4, #1 BL sine BX lr R4 2 (SP) 4(LR) 5(PC) 0 1 2 4 0x080000F4 0x080000F0 PC SP LR xxxxxxxx 0x00000002 0x08001000 0x200001FC 0x200001F8 0x200001F4 0x200001F0 0x200001EC 2 0x200001E8 1 0x200001E4 0 0x200001E0 0x200001DC 0x200001D8 BL sine Updates LR register 0x200001E0 Memory 0x200001D4 0x200001D0 0x200001CF Lecture # 6

Interrupt: Stacking & Unstacking STACKING main PROC addr = 0x08000044 MOV r,#0 addr = 0x0800001C SysTick_Handler PROC EXPORT SysTick_Handler ADD r4, #1 BL sine BX lr R4 2 (SP) 4(LR) 5(PC) 0 1 2 4 0x080000F4 0x080000F0 PC SP LR xxxxxxxx 0x00000002 0x08001000 0x200001FC 0x200001F8 0x200001F4 0x200001F0 0x200001EC 2 0x200001E8 1 0x200001E4 0 0x200001E0 0x200001DC 0x200001D8 BL sine Updates LR register 0x200001E0 Memory 0x200001D4 0x200001D0 0x200001CF Lecture # 7

Interrupt: Stacking & Unstacking UNSTACKING won t occur! main PROC addr = 0x08000044 MOV r,#0 addr = 0x0800001C SysTick_Handler PROC EXPORT SysTick_Handler ADD r4, #1 BL sine BX lr R4 2 (SP) 4(LR) 5(PC) 0 1 2 4 0x080000F4 0x080000F0 PC SP LR xxxxxxxx 0x00000002 0x08001000 0x200001FC 0x200001F8 0x200001F4 0x200001F0 0x200001EC 2 0x200001E8 1 0x200001E4 0 0x200001E0 0x200001DC 0x200001D8 BL sine Updates LR register 0x200001E0 Memory 0x200001D4 0x200001D0 0x200001CF Lecture # 8

Interrupt: Stacking & Unstacking main PROC addr = 0x08000044 MOV r,#0 addr = 0x0800001C SysTick_Handler PROC EXPORT SysTick_Handler PUSH {lr} ADD r4, #1 BL sine POP {lr} BX lr R4 2 (SP) 4(LR) 5(PC) 0 1 2 4 0x080000F4 0x080000F0 0x200001E0 Fix the bug! PSP Save LR of course 0x00000000 PC SP LR xxxxxxxx 0x00000002 0x08001000 0x200001FC 0x200001F8 0x200001F4 0x200001F0 0x200001EC 2 0x200001E8 1 0x200001E4 0 0x200001E0 0x200001DC 0x200001D8 0x200001D4 0x200001D0 0x200001CF Memory Lecture # 9

Lab Practical #1 Some important things to note before you come for the practical. 1.The practical is closed book, open notes and access to the class website. 2.Make sure that you have access to all your code for all the labs you have done so far. The working code with its proper understanding will help you perform the practical properly..you will be given a simple problem to solve and you need to write a working program for that problem. The practical is worth 50 points (equivalent to all of the points you can receive for half of the lab experiments). 4.Make sure to go through the basics of writing the flow chart in Appendix E posted on the web site (follow the link Lab Assignments ). The flow chart for the program will be worth 10 points. The flow chart should be written in ENGLISH. If it contains any instructions specific to any software language, you will lose 2 points. If it does not contain proper shapes for the blocks, you will lose another 2 points. 5.The practical will have one easy section (worth 0 points) and one not so easy section (worth 40 points). If you choose to work with the easy section, you can score a maximum of 40 points. If you choose to work with the not so easy section, you can score the maximum of 50 points. Lecture # 40

Lab Practical #1-continued 6. You will work on the given problem for the first 90 minutes and the TA will check off your flow chart and working program after that. If you do not get your program checked off before the end of your session, you will not receive any credit for your work. 7. If the program is not working properly, you will receive partial credit on the basis of the working status of your program. 8. TA will not help you with the code; you need to work by yourself on the code and show the final results to the TA. 9. If you understand all the code for Labs 1 4 and if you have all the code with you, you should be able to perform the practical in no more than 50 minutes. 10. Do NOT discuss your practical with any other student until all practicals have been given (Friday noon). Not adhering to this could result in your failing the course. Lecture # 41

Lab Practical #1-Example Problem: Write a program that Uses the stored text above in memory. The end of text is marked by 0x04. (HINT: Which type of memory can be initialized?) Displays the original message on the screen. Copies the string to a new spot in memory starting at 0x20000B00 and changes every occurrence of certain letters in the message Waits for 5 seconds generated using a DELAY subroutine, Displays the new message store in memory Displays the (hexadecimal) number of occurrences a character change was made. Procedure: 1. Write a flow chart for the above problem (10 points). 2. Solve the Problem above (write a program) using one of the following methods:... Lecture # 42

Review Topics for Tuesday s Lecture What material would you like to review before mid-term exam? Lecture # 4