inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures CS 61C L21 Caches II (1) Lecture 21 Caches II 24-3-1 Lecturer PSOE Dan Garcia www.cs.berkeley.edu/~ddgarcia US Buys world s biggest RAM disk. 2.5TB! 1, x the size of the RAM on your PC. They ll use it for warez^h^h^h^h^h database queries. It cost 4.7 M$! Tera-RamSan. 1, Watts! Garcia, Spring 24 UCB
Memory Address 12 Review: Direct-Mapped Cache 3 4 5 6 7 8 9 A B C D E F Memory CS 61C L21 Caches II (2) Cache Index 1 2 3 4 Byte Direct Mapped Cache Cache Location can be occupied by data from: Memory location, 4, 8, 4 blocks => any memory location that is multiple of 4 Garcia, Spring 24 UCB
Review: Issues with Direct-Mapped Since multiple memory addresses map to same cache index, how do we tell which one is in there? What if we have a block size > 1 byte? Result: divide memory address into three fields ttttttttttttttttt iiiiiiiiii oooo tag index byte to check to offset if have select within correct block block block CS 61C L21 Caches II (3) Garcia, Spring 24 UCB
Direct-Mapped Cache Terminology All fields are read as unsigned integers. Index: specifies the cache index (which row of the cache we should look in) Offset: once we ve found correct block, specifies which byte within the block we want Tag: the remaining bits after offset and index are determined; these are used to distinguish between all the memory addresses that map to the same location CS 61C L21 Caches II (4) Garcia, Spring 24 UCB
Caching Terminology When we try to read memory, 3 things can happen: 1. cache hit: cache block is valid and contains proper address, so read desired word 2. cache miss: nothing in cache in appropriate block, so fetch from memory 3. cache miss, block replacement: wrong data is in cache at appropriate block, so discard it and fetch desired data from memory (cache always copy) CS 61C L21 Caches II (5) Garcia, Spring 24 UCB
Direct-Mapped Cache Example (1/3) Suppose we have a 16KB of data in a direct-mapped cache with 4 word blocks Determine the size of the tag, index and offset fields if we re using a 32-bit architecture Offset need to specify correct byte within a block block contains 4 words = 16 bytes = 2 4 bytes need 4 bits to specify correct byte CS 61C L21 Caches II (6) Garcia, Spring 24 UCB
Direct-Mapped Cache Example (2/3) Index: (~index into an array of blocks ) need to specify correct row in cache cache contains 16 KB = 2 14 bytes block contains 2 4 bytes (4 words) # blocks/cache = bytes/cache bytes/block = 2 14 bytes/cache 2 4 bytes/block = 2 1 blocks/cache need 1 bits to specify this many rows CS 61C L21 Caches II (7) Garcia, Spring 24 UCB
Direct-Mapped Cache Example (3/3) Tag: use remaining bits as tag tag length = addr length offset - index = 32-4 - 1 bits = 18 bits so tag is leftmost 18 bits of memory address Why not full 32 bit address as tag? All bytes within block need same address (4b) Index must be same for every address within a block, so its redundant in tag check, thus can leave off to save memory (1 bits in this example) CS 61C L21 Caches II (8) Garcia, Spring 24 UCB
Accessing data in a direct mapped cache Ex.: 16KB of Memory data, directmapped, 4 word blocks Read 4 addresses 1. x14 2. x1c 3. x34 4. x814 Memory values on right: only cache/ memory level of hierarchy CS 61C L21 Caches II (9) Address (hex)value of Word 1 14 18 1C a b c d 3 34 38 3C 81 814 818 81C e f g h i j k l Garcia, Spring 24 UCB
Accessing data in a direct mapped cache 4 Addresses: x14, x1c, x34, x814 4 Addresses divided (for convenience) into Tag, Index, Byte Offset fields 1 1 1 11 11 1 1 1 1 Tag Index Offset CS 61C L21 Caches II (1) Garcia, Spring 24 UCB
16 KB Direct Mapped Cache, 16B blocks bit: determines whether anything is stored in that row (when computer initially turned on, all entries are invalid) Index Tag x-3 x4-7 x8-b xc-f 1 2 3 4 5 6 7 122 123 CS 61C L21 Caches II (11) Garcia, Spring 24 UCB
1. Read x14 1 1 Tag field Index field Offset Index Tag x-3 x4-7 x8-b xc-f 1 2 3 4 5 6 7 122 123 CS 61C L21 Caches II (12) Garcia, Spring 24 UCB
So we read block 1 (1) 1 1 Tag field Index field Offset Index Tag x-3 x4-7 x8-b xc-f 1 2 3 4 5 6 7 122 123 CS 61C L21 Caches II (13) Garcia, Spring 24 UCB
No valid data 1 1 Tag field Index field Offset Index Tag x-3 x4-7 x8-b xc-f 1 2 3 4 5 6 7 122 123 CS 61C L21 Caches II (14) Garcia, Spring 24 UCB
So load that data into cache, setting tag, valid 1 1 Tag field Index field Offset Index Tag x-3 x4-7 x8-b xc-f 1 1 a b c d 2 3 4 5 6 7 122 123 CS 61C L21 Caches II (15) Garcia, Spring 24 UCB
Read from cache at offset, return word b 1 1 Tag field Index field Offset Index Tag x-3 x4-7 x8-b xc-f 1 1 a b c d 2 3 4 5 6 7 122 123 CS 61C L21 Caches II (16) Garcia, Spring 24 UCB
2. Read x1c =..1 11 1 11 Tag field Index field Offset Index Tag x-3 x4-7 x8-b xc-f 1 1 a b c d 2 3 4 5 6 7 122 123 CS 61C L21 Caches II (17) Garcia, Spring 24 UCB
Index is 1 11 Tag field Index field Offset Index Tag x-3 x4-7 x8-b xc-f 1 1 a b c d 2 3 4 5 6 7 122 123 CS 61C L21 Caches II (18) Garcia, Spring 24 UCB
Index valid, Tag Matches 1 11 Tag field Index field Offset Index Tag x-3 x4-7 x8-b xc-f 1 1 a b c d 2 3 4 5 6 7 122 123 CS 61C L21 Caches II (19) Garcia, Spring 24 UCB
Index, Tag Matches, return d 1 11 Tag field Index field Offset Index Tag x-3 x4-7 x8-b xc-f 1 1 a b c d 2 3 4 5 6 7 122 123 CS 61C L21 Caches II (2) Garcia, Spring 24 UCB
3. Read x34 =..11 1 11 1 Tag field Index field Offset Index Tag x-3 x4-7 x8-b xc-f 1 1 a b c d 2 3 4 5 6 7 122 123 CS 61C L21 Caches II (21) Garcia, Spring 24 UCB
So read block 3 11 1 Tag field Index field Offset Index Tag x-3 x4-7 x8-b xc-f 1 1 a b c d 2 3 4 5 6 7 122 123 CS 61C L21 Caches II (22) Garcia, Spring 24 UCB
No valid data 11 1 Tag field Index field Offset Index Tag x-3 x4-7 x8-b xc-f 1 1 a b c d 2 3 4 5 6 7 122 123 CS 61C L21 Caches II (23) Garcia, Spring 24 UCB
Load that cache block, return word f 11 1 Tag field Index field Offset Index Tag x-3 x4-7 x8-b xc-f 1 1 a b c d 2 3 1 e f g h 4 5 6 7 122 123 CS 61C L21 Caches II (24) Garcia, Spring 24 UCB
4. Read x814 = 1..1 1 1 1 1 Tag field Index field Offset Index Tag x-3 x4-7 x8-b xc-f 1 1 a b c d 2 3 1 e f g h 4 5 6 7 122 123 CS 61C L21 Caches II (25) Garcia, Spring 24 UCB
So read Cache Block 1, Data is 1 1 1 Tag field Index field Offset Index Tag x-3 x4-7 x8-b xc-f 1 1 a b c d 2 3 1 e f g h 4 5 6 7 122 123 CS 61C L21 Caches II (26) Garcia, Spring 24 UCB
Cache Block 1 Tag does not match (!= 2) 1 1 1 Tag field Index field Offset Index Tag x-3 x4-7 x8-b xc-f 1 1 a b c d 2 3 1 e f g h 4 5 6 7 122 123 CS 61C L21 Caches II (27) Garcia, Spring 24 UCB
Miss, so replace block 1 with new data & tag 1 1 1 Tag field Index field Offset Index Tag x-3 x4-7 x8-b xc-f 1 1 2 i j k l 2 3 1 e f g h 4 5 6 7 122 123 CS 61C L21 Caches II (28) Garcia, Spring 24 UCB
And return word j 1 1 1 Tag field Index field Offset Index Tag x-3 x4-7 x8-b xc-f 1 1 2 i j k l 2 3 1 e f g h 4 5 6 7 122 123 CS 61C L21 Caches II (29) Garcia, Spring 24 UCB
Do an example yourself. What happens? Chose from: Cache: Hit, Miss, Miss w. replace Values returned: a,b, c, d, e,, k, l Read address x3? 11 Read address x1c? 1 11 Cache Index Tag x-3 x4-7 x8-b xc-f 1 1 2 i j k l 2 3 1 e f g h 4 5 6 7 CS 61C L21 Caches II (3) Garcia, Spring 24 UCB
Administrivia Midterm CS 61C L21 Caches II (31) Garcia, Spring 24 UCB
Upcoming Calendar Week # #8 This week #9 Next week #9+ Spring Break! Mon Dan Caches I Midterm Dan VM II It s Wed Dan Caches II Dan VM III Party Thurs Lab Exams Back & Discuss Caches No Dan OH Time Fri Dan Caches III / VM I Chema Intro to Sync Digital Woo Hoo! CS 61C L21 Caches II (32) Garcia, Spring 24 UCB
Answers x3 a hit Index = 3, Tag matches, Offset =, value = e 1 14 18 Index = 1, Tag mismatch, 1c so replace from memory, Offset = xc, value = d x1c a miss Since reads, values must = memory values whether or not cached: x3 = e x1c = d CS 61C L21 Caches II (33) Memory Address Value of Word a b c d 3 34 38 3c 81 814 818 81c e f g h i j k l Garcia, Spring 24 UCB
Peer Instructions 1. All caches take advantage of spatial locality. 2. All caches take advantage of temporal locality. 3. On a read, the return value will depend on what is in the cache. CS 61C L21 Caches II (34) ABC 1: FFF 2: FFT 3: FTF 4: FTT 5: TFF 6: TFT 7: TTF 8: TTT Garcia, Spring 24 UCB
Peer Instruction Answers F A L S E T R U E 1. All caches take advantage of spatial locality. 2. All caches take advantage of temporal locality. F A L S E ABC 1: FFF 2: FFT 3: FTF 4: FTT 5: TFF 6: TFT 7: TTF 8: TTT 3. On a read, the return value will depend on what is in the cache. 1. Block size = 1, no spatial! 2. That s the idea of caches; We ll need it again soon. 3. It better not! If it s there, use it. Oth, get from mem CS 61C L21 Caches II (35) Garcia, Spring 24 UCB
And in Conclusion Mechanism for transparent movement of data among levels of a storage hierarchy set of address/value bindings address index to set of candidates compare desired address with tag service hit or miss - load new block and binding on miss address: tag index offset 1 11 Tag x-3 x4-7 x8-b xc-f 1 2 3 1 a b c d CS 61C L21 Caches II (36) Garcia, Spring 24 UCB