MIPS Datapath. MIPS Registers (and the conventions associated with them) MIPS Instruction Types

Similar documents
MIPS%Assembly% E155%

Lecture 5: Procedure Calls

COMP 303 Computer Architecture Lecture 3. Comp 303 Computer Architecture

comp 180 Lecture 10 Outline of Lecture Procedure calls Saving and restoring registers Summary of MIPS instructions

Rui Wang, Assistant professor Dept. of Information and Communication Tongji University.

Chapter 2A Instructions: Language of the Computer

Chapter 2. Computer Abstractions and Technology. Lesson 4: MIPS (cont )

Today s topics. MIPS operations and operands. MIPS arithmetic. CS/COE1541: Introduction to Computer Architecture. A Review of MIPS ISA.

CSE Lecture In Class Example Handout

CISC 662 Graduate Computer Architecture. Lecture 4 - ISA MIPS ISA. In a CPU. (vonneumann) Processor Organization

Control Instructions. Computer Organization Architectures for Embedded Computing. Thursday, 26 September Summary

Control Instructions

Computer Architecture. The Language of the Machine

Instructions: MIPS ISA. Chapter 2 Instructions: Language of the Computer 1

Course Administration

ECE 331 Hardware Organization and Design. Professor Jay Taneja UMass ECE - Discussion 3 2/8/2018

CENG3420 Lecture 03 Review

Computer Architecture

Reduced Instruction Set Computer (RISC)

CISC 662 Graduate Computer Architecture. Lecture 4 - ISA

CS222: MIPS Instruction Set

Reduced Instruction Set Computer (RISC)

COMPSCI 313 S Computer Organization. 7 MIPS Instruction Set

Lecture 4: MIPS Instruction Set

101 Assembly. ENGR 3410 Computer Architecture Mark L. Chang Fall 2009

Lectures 3-4: MIPS instructions

ECE232: Hardware Organization and Design. Computer Organization - Previously covered

Instruction Set Architecture part 1 (Introduction) Mehran Rezaei

ELEC / Computer Architecture and Design Fall 2013 Instruction Set Architecture (Chapter 2)

Instruction Set Architectures Part I: From C to MIPS. Readings:

Computer Organization MIPS Architecture. Department of Computer Science Missouri University of Science & Technology

5/17/2012. Recap from Last Time. CSE 2021: Computer Organization. The RISC Philosophy. Levels of Programming. Stored Program Computers

Recap from Last Time. CSE 2021: Computer Organization. Levels of Programming. The RISC Philosophy 5/19/2011

CS3350B Computer Architecture

EN164: Design of Computing Systems Lecture 09: Processor / ISA 2

ECE468 Computer Organization & Architecture. MIPS Instruction Set Architecture

Instructions: Language of the Computer

ENGN1640: Design of Computing Systems Topic 03: Instruction Set Architecture Design

Machine Language Instructions Introduction. Instructions Words of a language understood by machine. Instruction set Vocabulary of the machine

CSE Lecture In Class Example Handout

Lecture 2. Instructions: Language of the Computer (Chapter 2 of the textbook)

Instruction Set Architecture

Computer Organization MIPS ISA

Subroutines. int main() { int i, j; i = 5; j = celtokel(i); i = j; return 0;}

MIPS Functions and the Runtime Stack

Branch Addressing. Jump Addressing. Target Addressing Example. The University of Adelaide, School of Computer Science 28 September 2015

MIPS R-format Instructions. Representing Instructions. Hexadecimal. R-format Example. MIPS I-format Example. MIPS I-format Instructions

Course Administration

ECE 15B Computer Organization Spring 2010

Chapter 2: Instructions:

Lecture 5: Procedure Calls

CSCI 402: Computer Architectures. Instructions: Language of the Computer (3) Fengguang Song Department of Computer & Information Science IUPUI.

Instructions: Language of the Computer

Instructions: Assembly Language

CS3350B Computer Architecture MIPS Introduction

Math 230 Assembly Programming (AKA Computer Organization) Spring MIPS Intro

MIPS Instruction Set

Computer Organization and Structure. Bing-Yu Chen National Taiwan University

EN164: Design of Computing Systems Topic 03: Instruction Set Architecture Design

Math 230 Assembly Programming (AKA Computer Organization) Spring 2008

ECE232: Hardware Organization and Design

Announcements HW1 is due on this Friday (Sept 12th) Appendix A is very helpful to HW1. Check out system calls

Chapter 2. Instructions: Language of the Computer. Adapted by Paulo Lopes

Code Generation. The Main Idea of Today s Lecture. We can emit stack-machine-style code for expressions via recursion. Lecture Outline.

EE 361 University of Hawaii Fall

ECE369. Chapter 2 ECE369

We can emit stack-machine-style code for expressions via recursion

Computer Organization and Components

Computer Architecture. MIPS Instruction Set Architecture

Computer Hardware Engineering

Instructions: Language of the Computer

Chapter 1. Computer Abstractions and Technology. Lesson 3: Understanding Performance

CS/COE1541: Introduction to Computer Architecture

ECE232: Hardware Organization and Design

UCB CS61C : Machine Structures

Computer Architecture Instruction Set Architecture part 2. Mehran Rezaei

MIPS Functions and Instruction Formats

! Data range can be too small!! Addressable memory is small!! Only room for 16 instruction opcodes! CSE 30321!

Forecast. Instructions (354 Review) Basics. Basics. Instruction set architecture (ISA) is its vocabulary. Instructions are the words of a computer

CS222: Dr. A. Sahu. Indian Institute of Technology Guwahati

Thomas Polzer Institut für Technische Informatik

Do-While Example. In C++ In assembly language. do { z--; while (a == b); z = b; loop: addi $s2, $s2, -1 beq $s0, $s1, loop or $s2, $s1, $zero

CS 4200/5200 Computer Architecture I

Computer Science and Engineering 331. Midterm Examination #1. Fall Name: Solutions S.S.#:

Computer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: MIPS Instruction Set Architecture

Review of Activation Frames. FP of caller Y X Return value A B C

Computer Organization and Structure. Bing-Yu Chen National Taiwan University

Stored Program Concept. Instructions: Characteristics of Instruction Set. Architecture Specification. Example of multiple operands

MODULE 4 INSTRUCTIONS: LANGUAGE OF THE MACHINE

Prof. Kavita Bala and Prof. Hakim Weatherspoon CS 3410, Spring 2014 Computer Science Cornell University. See P&H 2.8 and 2.12, and A.

COMPUTER ORGANIZATION AND DESIGN

Lecture 7: Procedures

Computer Architecture. Chapter 2-2. Instructions: Language of the Computer

Lectures 5. Announcements: Today: Oops in Strings/pointers (example from last time) Functions in MIPS

ECE 154A Introduction to. Fall 2012

Chapter 4. The Processor. Computer Architecture and IC Design Lab

MIPS Instruction Set Architecture (2)

Grading: 3 pts each part. If answer is correct but uses more instructions, 1 pt off. Wrong answer 3pts off.

CS 351 Exam 2 Mon. 11/2/2015

CS/COE0447: Computer Organization

Transcription:

1 Lecture 08 Introduction to the MIPS ISA + Procedure Calls in MIPS Longer instructions = more bits to address registers MIPS Datapath 6 bit opcodes... 2 MIPS Instructions are 32 bits More ways to address memory... plus 6 bit function codes = more functionality MIPS Registers (and the conventions associated with them) Name R# Usage Preserved on Call $zero 0 The constant value 0 n.a. $at 1 Reserved for assembler n.a. $v0-$v1 2-3 Values for results & expr. eval. no $a0-$a3 4-7 Arguments no $t0-$t7 8-15 Temporaries no 3 MIPS Instruction Types Instructions are characterized into basic types For type 32 bits of instruction are interpreted differently 3 types of instructions in MIPS R type I type J type 4 $s0-$s7 16-23 Saved yes $t8-$t9 24-25 More temporaries no $k0-$k1 26-27 Reserved for use by OS n.a. $gp 28 Global pointer yes $sp 29 Stack pointer yes $fp 30 Frame pointer yes In other words: As seen with Add, instruction encoding broken down into X different fields With MIPS, only 3 ways X # of bits arranged Think about datapath: Why might this be good? $ra 31 Return address yes

5 A quick look: more complex ISAs Path of Add from start to finish. 0010 0011 Datapath 6 R-Type: Assembly and Machine Format! R-type: All operands are in registers Assembly: add $9, $7, $8 # add rd, rs, rt: RF[rd] = RF[rs]+RF[rt]!!!!!!!!!!!!!!!!!!!!!!!!! (add: op+func) 31 26 25 21 20 16 15 11 10 6 5 0 op (6) rs (5) rt (5) rd (5) shamt (5) funct (6) Machine: B: 000000 00111 01000 01001 xxxxx 100000 D: 0 7 8 9 x 32 Add: 0010 0001 0010 0011 Mov: 0000 0001 0010 0011 R-type Instructions! All instructions have 3 operands! All operands must be registers! Operand order is fixed (destination first)! Example: 7 I-Type Instructions I-type: One operand is an immediate value and others are in registers Example: addi $s2, $s1, 128 # addi rt, rs, Imm # RF[18] = RF[17]+128 8! C code:! A = B - C;!! (Assume that A, B, C are stored in registers s0, s1, s2.) 31 26 25 21 20 16 15 0 Op (6) rs (5) rt (5) Address/Immediate value (16)! MIPS code:! sub $s0, $s1, $s2! Machine code: 000000 10001 10010 10000 xxxxx 100010 B: 001000 10001 10010 0000000010000000 D: 8 17 18 128! Other R-type instructions " addu, mult, and, or, sll, srl,

I-Type Instructions: Another Example 9 I-Type Instructions: Yet Another Example 10 I-type: One operand is an immediate value and others are in registers Example: lw!"#$%#&'!()*%%%%%+%rf[19] = DM[RF[8]+32] 31 26 25 21 20 16 15 0 Op (6) rs (5) rt (5) Address/Immediate value (16) I-type: One operand is an immediate value and others are in registers Example: Again:: bne $t0, $t1, Again # if (RF[8]!=RF[9]) = + 4 + Imm*4 # else =+4 31 26 25 21 20 16 15 0 Op (6) rs (5) rt (5) Address/Immediate value (16) B: 100011 01000 10011 0000000000100000 D: 35 8 19 32 How about load the next word in memory? B: 00101 01000 01001 0000 0000 0001 0000 D: 5 8 9 16,-./012(340%255/0""367 11 12 Byte addressability J-Type Instructions What immediate values are encoded in an I-type instruction (for example) are affected by the fact that MIPS data words are byte addressable (Let"s look at Questions #1 and #2 on the board)! J-type: only one operand: the target address Example: j 3 # Goto addr. 3 x 4 (i.e. goto addr. 12) 31 26 25 0 Op (6) Target address (26) B: 000010 00000000000000000000000011 D: 2 3

In class examples 13 14 Size of Immediate Operand 8-15 16-31 32-63 4-7 Practical Procedures Have already started to see that you don"t make N copies of for loop body Thus: for (i=0; i<n; i++) { a = b + c; d = a + e; f = d + i; } loop: Might look like this: # N = $2, i = $3 subi $2, $2, 1 add $4, $5, $6 add $7, $4, $8 add $9, $7, $10 addi $3, $3, 1 sub $11, $2, $3 bneq $11, $0, loop # N = N -1 # a = b + c # d = a + e # f = d + i # i = i + 1 # $11 = $3 - $2 # if $11!= 0, loop You wouldn"t make multiple copies of a machine instruction function either... 15 For example: int main(void) { int i; int j; } j = power(i, 7); int power(int i, int n) { int j, k; for (j=0; j<n; j++) k = i*i; return k; } Practical Procedures call: power: Might look like this: i = $4 addi $ 5, $0, 7 j power... subi $2, $2, 1 mult $5, $5, $5 addi $3, $3, 1 sub $11, $2, $3 bneq $11, $0, loop add $2, $5, $0 j call # arg reg. = 7 # data in ret. reg. Advantage: Much greater code density. (especially valuable for library routines, etc.) 16

Procedure calls are so common that there"s significant architectural support. 17! The big picture: Caller +1 MIPS Procedure Handling jal Callee! Need jump and return : " jal ProcAddr # issued in the caller jumps to ProcAddr save the return instruction address in $31 = JumpAddr, RF[31]=+4; " jr $31 ($ra) # last instruction in the callee jump back to the caller procedure = RF[31] jr r 0 r 1...!#8%9%!/2%'/0(:/6%255/0""* 0 r 31 b n-1... b 0 HI LO 18 MIPS Procedure Handling (cont.)! What about passing parameters and return values? " registers $4 - $7 ($a0-$a3) are used to pass first 4 parameters " returned values are in $2 and $3 ($v0-$v1)! 32x32-bit GPRs (General purpose registers) " $0 = $zero (Liar! only 31 GPRs) " $2 - $3 = $v0 - $v1 (return values) " $4 - $7 = $a0 - $a3 (arguments) r 0 r 1 32 bits 0 19 In class example 20 " $8 - $15 = $t0 - $t7 (temporaries) " $16 - $23 = $s0 - $s7 (saved) " $24 - $25 = $t8 - $t9 (more temporaries) " $31 = $ra (return address)... r 31 b n-1... b 0 HI LO

! Register contents across procedure calls are designated as either caller or callee saved! MIPS register conventions: More complex cases " $t*, $v*, $a*: not preserved across call caller saves them if required " $s*, $ra, $fp: preserved across call callee saves them if required " See P&H FIGURE 2.18 (p.88) for a detailed register usage convention " Save to where??! More complex procedure calls " What if your have more than 4 arguments? " What if your procedure requires more registers than available? " What about nested procedure calls? " What happens to $ra if proc1 calls proc 2 which calls proc3, 21 The stack comes to the rescue! Stack "A dedicated area of memory "First-In-Last-Out (FILO) "Used to # Hold values passed to a procedure as arguments # Save register contents when needed # Provide space for variables local to a procedure! Stack operations "push: place data on stack (sw in MIPS) "pop: remove data from stack (lw in MIPS)! Stack pointer "Stores the address of the top of the stack "$29 ($sp) in MIPS 22 Lower Mem Addr Higher Mem Addr Where is the stack located? Memory Structure Reserved Instruction segment Data segment Stack segment SP! Stack pointer is kept double-word aligned (by convention). Addr i-2 i-1 i Top of stack i+1 i+2 $sp = i 23! Each procedure is associated with a call frame! Each frame has a frame pointer: $fp ($30) main { proc1 } proc1 { proc2 } proc2 { proc3 } Call frames Snap shots of stack proc3 proc2 proc1 main Local variables Saved Registes ($fp) ($ra) Argument 5 Argument 6 $sp $fp Argument 5 is in 4($fp) 24