Synthesis of Supervisory Control of Discrete Event System for Static VAR Compansator

Synthesis of Supervisory Control of Discrete Event System for Static VAR Compansator Tarun Jain Department of Electrical Engineering Indian Institute of Technology, BHU Varanasi, India tarun.jain.eee10@itbhu.ac.in Prof. S.K. Nagar Department of Electrical Engineering Indian Institute of Technology, BHU Varanasi, India sknagar.eee@itbhu.ac.in Abstract This paper presents the application of discrete event system in the field of power system. In power system there are various components which required control and coordination when they are in operation. The theory of discrete event system has been applied in the application part of power system. The discrete nature of ULTC and discrete switching behavior of SVC are best suited for the supervisory control of discrete event system. The supervisory control theory is general theory for design and implementation of control logic in DES. ULTC are widely used in power system to care of the transmission line for voltage variation. Whereas SVC has fast dynamic characteristics to support the voltage variation in transients condition. The combination of ULTC and SVC can take care of transmission line in both steady state and dynamic regimes. Keywords- Discrete-event system (DES), under load tap changing transformer (ULTC), static var compensator (SVC), supervisory control. T I. INTRODUCTION HE electrical power system is an important part of this world. The power system consists of generation, transmission and distribution. The devices used in the power systems are under load tap changing transformer (ULTC), dynamic flow controller (DFC), static VAR compensator (SVC), and many more. For the reliable and smooth operation of power system, the control of such devices is necessary. ULTC consists tap changing facilities constitute an important means of controlling voltage in the power system [1][2]. ULTC are widely used in transmission network for the step up or step down the voltage at all level. But ULTC is not capable of providing fast response for voltage variation load. Whereas Static VAR Compensator (SVC) provides fast dynamic response [10]. But due to rating of SVC components, its operation is restricted. Hence the combination of ULTC and SVC is best suited for voltage variation load. The drawback of one device is compensated by another device. Both devices works properly in electrical power system if they are properly control and coordinated. DES is a dynamic system, generally used where control and coordination is required between various component to ensure the orderly flow of events. And it evolves in accordance with the sudden occurrence of physical event at unknown intervals [5]. The technique used in discrete event system is supervisory control, which is effective analytic tool for the control of DES [6]. The application of DES is in various fields i.e. in the field of communication, database management system, queuing system, manufacturing system and also in the field of power system. The application of DES in the field of power system includes Supervisory control, modeling of its component, analysis and diagnosis and monitoring [1]-[4]. From last two decades, study of DES has been done by many researchers of various fields. The problem in DES is solved in two models. First is untimed model, in this model only the sequence of states is evaluated. I.e. only the logical behavior is considered [5]. Where as in second model i.e. timed model both the logical and timing information are to be considered [7]. The component of power system and control logic are model in each mode as finite automata, then supervisory control of DES is possible and designed for the automatic and auto/manual mode of operation and in centralized and decentralized structure [1][2]. The supervisory control of DES is a method for the design and control of the plant and its component by the mean of control logic i.e. control specification. Supervisory control of discrete event system (SCDES) uses systematic formation on a rigorous mathematical basis to ensure non blocking and non conflicting properties of plant and also evaluates controllability of control logic with respect to plant [6]. The problem in DES has been solved by software called TCT. There are many software used in DES. The synthesis methods for DES controls have been developed and implemented in a software environment called TCT [8]. The TCT is use for the synthesis and supervisory control of the problem. The computation for the supervisory control theory (SCT) can be performed by the TCT software. In TCT, all automata model are created by the CREATE command. Then the synchronous product command (SYNC ( )), in TCT used for obtaining the PLANT model in DES. MEET command in TCT is used for to obtain the specifications model in TCT. And by the supervisory control (supcon (PLANT, SPEC)) command in TCT final controller has been design. TCT (toy control theory) is software developed by Professor W. M. Wonham, who invented the supervisory control theory (SCT) [9]. The aim of this paper is to propose a systematic approach to control and coordinated between various power systems components by using TCT implementation for SCT. The 1

application part of supervisory control of discrete event system (SCDES) in power system, in this paper we discuss by taking various components of power system as finite automata and design and implemented in TCT platform. The organization of this paper is as follows. In section 2, we discuss about the basic of discrete event system and its automata briefly. Section 3, gives the idea about the basic of ULTC and SVC. Section 4 deals with supervisory control theory of DES in ULTC and SVC. In section 5, explains the proposed solution of the DES in TCT and synthesis of supervisory control. And finally we conclude in section 6. II. DISCRETE EVENT SYSTEM RW supervisory control theory gives a framework to model and control the behavior of discrete event system [5]. A brief introduction of the theory of DES is given here. In DES model we include the set of states (i.e. initial state marker state), set of event and the state transition function. In automata, we represent the DES as structure. There are other software tools available for simulation and analysis of DES. III. A. Tap Changing Transformer- BASIC OF ULTC AND SVC Transformer with tap changer is an important application in distribution power system for controlling the voltage at all voltage levels. Transformer with ULTC facilities are widely used in transmission network. When the voltage is not normal (i.e. outside a desired range) then after some time delay the controller changes its tap to bring the voltage its normal voltage. The delay is provided to prevent unnecessary changing of tap during transient condition. Fig. 1 shows the block diagram of a ULTC [1][2]. G = (Q,, δ, q 0, Q m ) Where Q = A finite set of states, with q o Q (initial state), Q m Q (set of marker states); = a finite set of events (σ); δ = a transition mapping δ : Q Q : δ (q, σ) =q', q' is the next state after an event σ occurs. G is the plant with all these states and events. G is called as generator and its generates a set of strings (sequence). In other words, it generates a language L(G), consisting of strings of events which are physically possible in the plant [5].A prefix of a string is an initial subsequence of s (i.e., if s is a string in *, u is a prefix of s if ur = s for some string r in * ). A set which contains all of the prefixes of each of its elements is said to be prefix-closed. Clearly, * is a prefix-closed set. As some sets of strings may not contain all of their prefixes, the prefix-closure of a set A, denoted by Ᾱ, is defined which contains all of the prefixes of each element of A. If A = Ᾱ, then the set A is prefix-closed. If A is not prefix-closed, then A Ᾱ with strict inclusion. The language L(G) is the set of all event sequences which are physically possible in the plant. L(G) = {s s Є *, δ(q 0, s) is defined} Clearly, L(G) is a subset of *, and L(G) is also prefix closed, because no event sequence in the plant can occur without its prefix occurring first. Those strings which can be extended to a marker state are of particular importance. The marked language, denoted by L m (G), consists of all strings which reach some marker state. L m (G) is a subset of L(G) and can be formally given as L m (G)= {s Є L(G) δ(q 0, s) є Q m } Fig. 1 Block diagram of control system for automatic changing of transformer taps Designer should have DES model of the plant and control specification for synthesis a supervisory control for the ULTC and also the control specification which are given in the next section. B. Static VAR compensator- SVC with tap changing transformer is widely used in modern electrical power system for improve power quality and reliability because of its transient response is good. SVC has capable of handling transient s condition and oscillation, damping during abnormal condition. While ULTC is not capable of handling these conditions during abnormal operation. This is the main advantage of using SVC with ULTC. But due to its rating, its regulation ability is restricted. So when SVC installed with ULTC on same load for voltage regulation purpose, the drawback of one can be compensated by the other. However these combination works properly only if proper coordination between these two. SVC with ULTC has been shown in Fig. 2. Due to discrete nature of SVC and ULTC, these are easily model as finite automata. Then supervisory control is possible [10]. A DES is said to be non blocking if L m (G) = L(G). This means that there always exists a sequence of events which takes the plant from any (reachable) state to a desired state. TCT software program is developed for modeling and synthesis supervisory control for discrete-event systems in different Fig. 2 Block diagram of SVC. 2

The drawback of ULTC is that it s unable to provide fast dynamic response for voltage variation load. Whereas SVC is a dynamic device which control the voltage during transients condition. But the operation of SVC is restricted due to its power rating. The combination of ULTC and SVC is connected on the same bus for controlling the voltage changes. So there is proper control and coordination is required between ULTC and SVC. IV. DES SUPERVISORY CONTROL FOR ULTC AND SVC Supervisory Control of DES- In this section, we model and discussed the plant and specification. This model is use for the study and implementation of the supervisory controller design. A. Modeling of ULTC plant and its specification Fig. 3 shows the block diagram of ULTC with SVC. ULTC consists of four components: voltmeter, timer, and tap changer and timer adjustment unit. Each component is modeled as finite automata than discrete event system is possible. And by the mean of synchronization, we combine these entire components to form a plant model [10]. assumed here that the tap changer has 5 steps. Events associated with the Tap Changer are Fig. 4 (b). o Tap down command (ev 31) o Tap down successful (ev 32) o Tap up command (ev 33) o Tap up successful (ev 34) o Tap up/down failed (ev 30) Timer Adjustment Unit- The timer adjustment unit receives information from the SVC and sends information to adaptively adjust the ULTC time delay. The Following events associated with the timer adjustment block Fig. 4 (d). o (0 B SVC α 1 B max ) or (β 1 B min B svc < 0) (ev 60) o Delay Time Sets to T d1 (ev 61) o (α 1 B max < B svc α 2 B max ) or (β 2 B min B svc < β 1 B min ) (ev 62) o Delay Time sets to T d2 (ev 63) o (α 2 B max < B svc B max ) or (B min B svc < β 2 B min ) (ev 64) o Delay Time sets to T d3 (ev 65) o B svc < 0 (ev 66) o Delay Time sets to T switching (ev 67) o SVC susceptance measurement unit initialized (ev 69) Operator- Operator can be switch operation of ULTC using the followinh events Fig. 4 (e). o Enter Automatic Mode (ev 41) o Enter Manual Mode (ev 43) Fig. 3 Block diagram of the Supervisory control system for ULTC and SVC Volt Meter- The load voltage (measure) (V l ) must be a dead band (V o ± ID), where V o is the set point, V= V o -V l is the voltage deviation and ID: insensitivity Degree. Voltmeter reports the following events associated with the load voltages Fig. 4 (c). o Voltmeter Initialized (ev 11) o Report V > ID and V is negative (ev10) o Report V < ID (Voltage Recovered) (ev 12) o Report V > ID and V is positive (ev14) o Report Voltage exceeds V max (ev 16) Timer- the timer times out after a certain delay operation time (OT). The following events are associated with the timer Fig. 4 (a). o Timer Starts (ev 21) o Timer Blocks and Resets (ev 25) o Timer Times out (ev 27) o Timer Resets (ev 23). Tap Changer- The transformer tap changer controls the transformer ratio manually or automatically in order to keep the power supply voltage practically constant, independently of the load. If the tap increase (decrease) is successful, the system returns to a state and waits for another command. If the taps increase (decrease) operation fails, the controller changes to the manual mode, and waits for another command. It is Fig. 4. DES models for (a) Timer, (b) Voltmeter, (c) Operator, (d) Tap Changer, (e) Timer Adjustment 3

B. Modeling of SVC-Following events are associated with SVC DES model [Fig. 5] o Susceptance measurement initialized (ev 51) o λb Cmax B svc λb Lmax (ev 50) o B svc < λb Cmax or B svc λb Lmax (ev 52) o V s2 V load V s1 (ev 80) o Fixed voltage reference control is switched on (ev81) o V load > V s2 or V load < V s1 (ev 82) o Floating voltage reference control switched on (ev 83) o The regulation slope X SL1 is switched on (ev 85) o The regulation slope X SL2 is switched on (ev 87) o Voltmeter initialized (ev 89) decreases stepwise. On the other hand, when the applied susceptance of the SVC is decreasing, the time delay of the ULTC is set to its maximum value. g. After of a tap movement, if another tap changing is required in the same direction, the time delay is set to T swithching (minimum possible value for the time delay). Now these logics are implemented in below DES model in Fig.6 (a)(b). Fig. 5. DES models for the SVC control system components Control logic for the ULTC and SVC- The control logic and specification for the ULTC and SVC are discussed here and then make DES model of these specifications. The Plant must be controlled based on these specifications [10]. 1. ULTC Specification- The specification for tap changer is given by the manufacture. The specifications are as follows. When Voltage is not normal, then the controller changes tap ratio after a time delay to restore the voltage i.e. bring it into its dead band. The delay time is based on SVC operation. SVC used to control the unnecessary tap changes during the transient periods. The following are the specification of ULTC. a. If the voltage deviation V > ID and V is negative (ev 10) then the timer will start and when it times out i.e. reaches its maximum (ev 27) then a tap increase command (ev 33) will be made and timer will be reset (ev 23). b. If the voltage deviation V > ID and V is positive (ev 14) then the timer will start and when it times out (ev 28) then a tap decrease command (ev 31) will be made and the timer will be reset (ev 23). c. If the voltage returns to the dead band (ev 12), because of smooth system dynamics or a tap change or some other system events, then the timer is blocked and reset (ev 25). d. If the voltage exceeds the value set for quick lowering (ev 16), then the timer becomes 0 second and therefore the lowering tap command (ev 31) happens instantaneously. e. If a fault in tap increase or decrease happens (ev 30), or operator forces the system from Automatic to manual mode at any time (ev 43) the system moves to the manual state and waits for the operator. f. The time delay of the ULTC is determined based on the SVC operation condition. When the applied susceptance of the SVC is increasing, the time delay of the ULTC will be Fig. 6. DES models for ULTC control specification (SP1 and SP2) 2. SVC Specification- The specification for SVC shown in Fig. 11. And it has following characteristics. a. When the controlled bus voltage is within the desired SVC switching points (ev 80), the fixed voltage reference control with the slope X SL1 is switched on (ev 81 and ev 85). b. When the controlled bus voltage crosses out the desired switching points (ev 82), the floating voltage reference control with the slope X SL2 is switched on (ev 83 and ev 87). c. When the SVC output is returned back to the steady state margin (ev 50), the changeover from the floating voltage reference control and slope X SL2 to a fixed voltage reference control and slope X SL1 is utilized (ev 81 and ev 85). These specifications of SVC are model as DES in the following Fig. 7. 4

Fig. 7. DES models for SVC control specification V. SUPERVISORY CONTROL SYNTHESIS By using the specification and plant model in TCT, the supervisory control is obtained in Automatic and Auto/Manual Mode. TCT is software developed for modeling and synthesis of supervisory control for DES. Design of the DES supervisor for SVC and ULTC model- ULTC_PLANT = Sync (TT, TC, VM, TA, OP) (252, 2658) Blocked_events = None SVC_PLANT = Sync (SSW, SM, VM1) (4, 28) Blocked_events = None PLANT_11 = Sync (ULTC_PLANT, SVC_PLANT) (1008, 17688) Blocked_events = None ULTC_SPEC_11=Meet(SPEC_ULTC_111,SPEC_ULTC_222) (90,821) SPEC_ULTC_SVC_11=Meet(ULTC_11_SPEC,SVC_SPEC_1) (540, 5826) SUP_11_A = Supcon (PLANT_11,SPEC_ULTC_SVC_11) (112,516) CON_SUP=Condat(PLANT_11,SUP_11_A) Controllable. SIM_SUP_11_A=Supreduce(PLANT_11,SUP_11_A,CON_SUP) (36,210;slb=36) true = Nonconflict (PLANT_11, SUP_11_A) M_SUP_11_A = Minstate (SUP_11_A) (80,348) true = Nonconflict (PLANT_11, M_SUP_11_A) TEST_M_SUP_11_A = Meet (PLANT_11, M_SUP_11_A) (80,348) true= Isomorph (TEST_M_SUP_11_A, M_SUP_11_A; identity) The size of the supervisor can be reducing by minstate. Minstate reduces the supervisor to a minimal state transition structure that generates the same closed and marked languages. VI. CONCLUTION This paper presents the application part of the supervisory control of DES in the field of power system. Different components are model in DES. This paper shows different solutions proposed for supervisory control of DES and implemented for problem related to electrical power system. The problem of voltage variations by ULTC is first model in terms of plant and control logics. Then supervisory controllers are design for ULTC in TCT software. It is guaranteed by the synthesis procedure that the designed supervisors are optimal and non blocking. The state size of the supervisory controllers is reducing for easier implementation. Step by step synthesis of the DES supervisory control is suggested. The plants and their control specification should be modeled, followed by the designing the supervisor. A non blocking supervisory control to coordinate the SVC and ULTC are synthesized. The ULTC and the SVC components are their specification has been modeled as finite automata. Controllability of the specification is evaluated and supervisory controllers have been designed in TCT program. REFERENCE [1] Afzalian A, Saadatpoor A and Wonham W.M. Discrete Event System Modeling and Supervisory Control for Under Load Tap Changing Transformer IEEE International Conference on Control Application Proceeding, 2006, Munich, Germany 2006. [2] Noorbakhsh M and Afzalian A (2007b). Design and PLC Based Implementation of Supervisory Controller for Under Load Tap Changer. Proc. of the 2007 IEEE Int. Conf. on Control, Automation and Systems (ICCAS 07), pp. 901-906, Seoul, Korea. [3] Afzalian A, Nabavi Niaki S.A, Iravani R, Wonham W.M. Discrete Event Systems Supervisory Control for a Dynamic Flow Controller. IEEE Trans. On Power Delovery, 24(1), 2009, pp:219-230 [4] Afzalian A, Noorbakhsh M. PLC Implementation of Decentralized Supervisory Control for Dynamic Flow Controller. 2008 IEEE Multi Conference on Systems and Control (CCA 08), San Antonio, Texas (USA), September 3-5, 2008. [5] Ramdage P.J. and Wonham W.M. The Control of Discrete Event System, Proceeding of IEEE, vol. 77, no. 1, 1989. [6] Wonham W.M. Workshop on Supervisory Control of Discrete Event System at IT-BHU Varanasi, January- 2006. [7] Brandin B.A. and Wonham W.M. Modular Supervisory Control of Timed Discrete Event Systems, Proceeding of the 32 nd Conf. on Decision and Control, San Antonio, Texas, December 1993. [8] Wonham W.M. and Lei. F. TCT A Computation tool for supervisory Control Synthesis Proceeding of 8 th International Workshop on DES, Ann Arbor, Michigan U.S.A., July 10-12, 2006. [9] Wonham W.M. Supervisory Control of Discrete Event System. Department of Electrical and Computer Engineering, University of Toronto 2008, available at http://www.control.utoronto.ca/des. [10] M. Noorbakhsh M and Afzalian A (2009), Modeling and Synthesis of DES Supervisory Control for Coordinating ULTC and SVC. 2009 American Control Conf. (ACC 09), pp. 4759-4764, Saint Louis, Missouri,USA. 5