M. Sc (CS) (II Semester) Examination, 2012-13 Subject: Computer System Architecture Paper Code: M.Sc-CS-203 Time: Three Hours] [Maximum Marks: 60 Note: Question Number 1 is compulsory. Answer any four questions from the remaining. Q1.(Give answer in short) Section-A Marks : 10X2 A. What do you mean by interrupt? Write in short. An interrupt is a signal from a device attached to a computer or from a program within the computer that causes the main program that operates the computer to stop and figure out what to do next. While the computer is running a program it doesn t check the flag. When the flag is set, the computer is momentarily interrupted from proceeding with the current program and is informed of the fact that a flag has been set. The computer deviates momentarily from what it is doing to take care of the input or output transfer. It then returns to the current program to continue what it was doing before interrupt. B. What are the functions of first pass assembler and second pass assembler? The function of 1 st pass assembler is to generate a table that correlates all userdefined address symbols with their binary equivalent value. The function of second pass assembler is to translate source program to binary by means of table lookup procedures. A table-lookup procedure is a search of table entries to determine whether a specific item matches one of the items stored in the table. C. Define different type of psedo instruction used in assembler. There are four types of Pseudo instructions used in a assembler A. ORG N: ORG N stands for origin of the program at hexadecimal location N. B. END: Denotes the end of symbolic program C. DEC N: Signed decimal number N to be converted to binary D. HEX N: Hexadecimal number N to be converted to binary.
D. What are the common fields found in instruction formats? The common fields found in instruction formats are 1) Mode field: Specifies the ways of accessing the operand. 2) Operation code field: Specifies the operation to be performed on the operands 3) Address field: It specifies the address of the operand E. Write truth table for 16 functions of logic micro operation. F. Write Boolean function and micro operation for any four logic micro operation.
G. Write any four symbolic designations for shift micro operation. H. Name any four register reference instruction with its function. CLA: Clear AC CMA: Complement AC INC: Increment AC CIR circulate right I. Describe Branch and save return address with diagram. BSA instruction is executed with a sequence of two micro operations BSA instruction is at location 20. The I bit is 0 and the address part of the instruction has the binary equivalent 135. After fetch decode PC contains 21 ie the return address. Return address 21 is stored in 135. And PC is incremented to 136 to serve I/O routine. When I/O work is completed control goes to read the effective address of 135 because of indirect mode to get the return address
J. Write different operations of STACK. There are two important types of operation of STACK 1) PUSH operation 2) POP operation PUSH operation: SP <- SP+1 M [SP] <- DR (Increment stack pointer) (Write item on top of the stack) If (SP=0) then (FULL<-1) (Check if stack is full) Empty<-0 (Mark the stack not empty) POP operation:
SECTION-B Marks-4X10 Q2. Explain arithmetic and logic micro operation with logic circuit. Arithmetic circuit: The basic component of an arithmetic circuit is the parallel adder. By controlling the data inputs to the adder, it is possible to obtain different types of arithmetic operations. The output of the binary adder is calculated from the following arithmetic sum: D= A+ Y+ C in Where A is the 4-bit binary number at the X inputs and Y is the 4-bit binary number at the Y inputs of the binary adder, C in is the input carry, which can be equal to 0 or 1. By controlling the values of 0 or 1, it is possible to generate eight arithmetic micro operations.
Logic Micro operation: There are 16 different logic operations that can be performed with two binary variables. The following table contains 16 columns F0 through F15 represents a truth table of one possible Boolean function for the two variables x an y. The 16 Boolean functions of two variables x and y are expressed in algebraic form as follows
Hardware Implementation: The following figure shows one stage of a circuit that generates the four basic logic micro operations. It consists of four gates and a multiplexer. Each of the four logic operations is generated through a gate that performs the required logic. The outputs of the gates are applied to the data inputs of the multiplexer. The two selection inputs s1 and s0 choose one of the data inputs of the multiplexer and direct its value to the output. Q3. Explain shift micro operation in detail with logic circuit. Shift micro operation is used for serial transfer of data. During a shift-left operation the serial input transfers a bit into the rightmost position. During a shift right operation the serial input transfers a bit into the leftmost position.there are three types of shifts: logical, circular and arithmetic. A logical shift is one that transfers 0 through the serial inputs. shl and shr are used for logical shift left and shift right micro operation. The symbolic representation is as follows
R1<-shl R1 R2<-shr R2 The above micro operation specify 1-bit shift to the left of the content of register R1 and a 1-bit shift to the right of the content of register R2.The bit transferred to the end position through the serial input is assumed to be 0 during a logical shift. The circular shift circulates the bits of the register around the two ends without loss of information. This is accomplished by connecting the serial output of the shift register to its serial input. The symbolic notation for circular shift is R<-cil R R<-cir R An arithmetic shift is a micro operation that shifts a signed binary number to the left or right. An arithmetic shift left multiplies a signed binary number by 2. An arithmetic shift-right divides the number by 2. Arithmetic shifts must leave the sign bit unchanged. The leftmost bit in a register holds the sign bit and the remaining bits hold the number. The sign bit is 0 for positive and 1 for negative. The following figure shows a typical register with n bits. Bit R n-1 holds the sign bit. The arithmetic shift-right leaves the sign bit unchanged and shifts the number to the right. The arithmetic shift left inserts a 0 into R 0 and shifts all other bits to the left. The initial bit of R n-1 is lost and replaced by the bit from R n-2. A sign reversal occurs if the bit in R n-1 changes in value after the shift. This happens in case of overflow. To check this flip-flop V s is used. If V s =0, there is no overflow but if V s =1, there is an over flow and a sign reversal occurs. Hardware implementation: Vs=R n-1 X-OR R n-2 A combinational circuit shifter can be constructed with multiplexers. The 4-bit shifter has four data inputs, A0 through A3 and four data outputs, H0 through H3.There are two serial inputs, one for shift left I L and shift right I R. When the selection input S=0 the input data are shifted right. When S=1 the data are shifted left. A shifter with n data inputs and outputs requires n multiplexers. The two serial inputs can be controlled by another multiplexer to provide the three possible types of shifts. The logic circuit and Boolean function r 4-bit shifter are as follows
Q4. A. Discuss program loops in assembly language. A program loop is a sequence of instruction that are executed many times each time with a different set of data.
The address of first operand is stored 150 is stored in location ADS in line 13. The number of times the statement number 3 must be executed is 100, So -100 is stored in location NBR. The address of the first operand is transferred to location PTR. This corresponds to setting A(J) to A(1). The number -100 is stored in NBR. The address of first operand is transferred to location PTR. The location acts as counter. As the reaches zero the 100 operations will be completed and the program will exit from the loop.
The program loop specified by the DO statement is translated to the sequence of instructions listed in lines 7 through 10. Line 7 specifies an indirect ADD instruction because it has the symbol I. he address of the current operand is stored in location PTR. When this location is addressed indirectly the computer takes the content of PTR to be the address of the operand. As a result the operand in location 150 is added to the accumulator, Location PTR is incremented in line 9 and if nonzero the computer does not skip the next instruction. The next instruction is a branch instruction to the beginning of the loop. When location CTR reaches to zero the next instruction is skipped and line 11 and 12 are executed. The sum so formed in AC is stored in SUM and the computer halts. B) Discuss different types of memory The main memory is the central storage unit in computer system. It is a relatively large and fast memory used to store programs and data during the computer operation. The principal technology used for the main memory is based on semi conductor integrated circuits. Three are two types of memory primary memory and secondary memory. Primary memory stores current data and instructions and the secondary memory stores the rest. Primary memory is divided into RAM and ROM RAM: RAM stands for random access memory. The read and write memory of a computer is called RAM. It possesses random access property. RAM is a volatile memory. The information written into it is retained in it as long as the power supply is on. There are two important types of RAM : Dynamic RAM Static RAM Dynamic RAM: Dynamic RAM loses its stored information in a very short time even though the power supply is on. In a dynamic RAM a binary state is stored on the gate to source stray capacitor of transistor of the MOS memory circuit. The presence of charge is represented as 1 and the absence of charge is represented as 0. The charges leaks in a few millisecond. So dynamic RAM need to be refreshed
every millisecond. Dynamic RAMS are cheaper and have high packing density and moderate speed, They consumes less power. Dynamic RAM are written as DRAM. DRAM s are used for main memory. Static RAM: The static RAM consists of internal flip flops that stores binary information. Static RAM retains stored information only as long as the power supply is on. Static RAMs are costlier and consumes more power. They do not need refreshing circuitry. They have higher speed than dynamic RAM s.static RAM is written as SRAM. SRAM s are used for cache memory. ROM: ROM stands for Read only memory. It is non volatile memory. The information stored in it not lost even if the power supply goes off. It is used for permanent storage of information. The stored information can only be read from ROM s at the time of operation. Information cannot be written into a ROM by the user/ programmer. The content of ROM is decided at the time of manufacturing. ROM is placed in two broad categories Masked programmed: ROM in which contents are written at the time of IC manufacture are called mask-programmed. User programmed: Other types of ROMs are user programmed. Types of ROM: PROM: PROM is a programmable ROM.Its contents are decided by the user. The user can store permanent programs, data or any kind of information in a PROM. PROM s are once programmable; the user can write his information in a PROM only once. EPROM: An EPROM is an erasable PROM. The stored data in EPROMs can be erased by exposing it to high intensity short wave ultraviolet light for about 20 minutes. When an EPROM is exposed to ultra violet light the entire data are erased. The user cannot erase the contents of certain selected memory locations. EEPROM: EEPROM is an electrically erasable PROM. It is known as electrically alterable PROM. The chip can be reprogrammed on a byte by byte basis. Either a single byte or the entire chip can be erased in one operation.
The following figures shows an example of a 1024X8 memory constructed with 128X8 RAM chips and 512 X 8 POM chips. 5) Explain instruction pipeline in detail with flow chart. An instruction pipeline reads consecutive instructions from memory while previous instructions are being executed in other segments. This causes the instruction fetch and executes phases to overlap and perform simultaneous operations. In instruction pipeline the decoding of the instruction is combined with the calculation of effective address into one segment. Instruction execution and storing of instruction are combined into one segment. This reduces the instruction into four segments. The following figure shows how the instruction cycle in the CPU can be processes with a four segment pipeline. While an instruction is being executed in segment4, the next instruction in sequence is busy in fetching an operand from memory in segment 3. The effective address is calculated in a separate segment. Once in a while an instruction in the sequence may be a program control that causes a branch out of normal sequence. In that case the pending operations in the last two segments are completed and all information stored in the instruction buffer is deleted. The pipeline then restarts from the new address stored
in the program counter. Similarly an interrupt request, when acknowledged, it causes the pipeline to empty and restart again from a new address value. The segments of the instruction pipelining are FI, DA, FO & EX. The time in the horizontal axis is divided into steps of equal duration. The four segments are represented in the figure. FI= The segment that fetches an instruction. DA=The segment that decodes the instruction and calculates the effective address. FO=The segment that fetches the operant. Ex=The segment that executes the instruction.
Branch Instruction: In the absence of a branch instruction, each segment operates on different.thus in step 4 instruction 1 is being executed in segment EX; the operand for instruction 2 is being fetched in segment FO; instruction 3 is being decoded in segment DA; and instruction 4 is being fetched from memory in segment FI. Let us assume that instruction in 3 is a branch instruction. As soon as the instruction is decoded in segment DA in step 4, the transfer from FI to DA of the other instructions is halted until the branch instruction is executed in step 6. If the branch is taken, a new instruction is fetched in step 7. If the branch is not taken, the instruction fetched previously in step 4 can be used. The pipeline then continues until a new branch instruction is encountered. Q6. Discuss the design of accumulator logic. In an accumulator design he adder and logic circuits has three sets of inputs. One set of 16 inputs comes from the outputs of AC. Another set of 16 inputs comes from the data register DR. A third set of eight inputs comes from the input register INPR. The outputs of the adder and logic circuits provide gates for controlling the LD, INR and CLR in the register and for controlling the operation of the adder and logic circuit. The circuit associated with AC register is shown below.
In order to design the logic associated with AC all statements that changes the content of Ac is needed. The statements are as follows. The gate structure of AC register from the above function table is as follows
Q7. Explain the concept of DMA in detail. Direct access Memory The transfer of data between a fast storage device and memory is always limited by the speed of the CPU. Removing the CPU from the path and letting the peripheral device to manage the memory buses directly is known as direct access memory. In DMA CPU is idle and has no control of the memory buses. A DMA
controller takes over the buses to manage the transfer directly between the I/O device and memory. The following figure shows two control signals in the CPU that facilitate the DMA transfer. The bus request (BR) input is the external DMA that the buses used by the DMA controller to request the CPU to relinquish control of the buses. When this input is active CPU terminates the execution of the current instruction and places the address bus, the data bus, and the read and writes lines into a high impedance state. The CPU activates bus grant (BG) output to inform the external DMA that buses are free. The DMA that originates the bus request can now take control of the buses to conduct memory transfer without processor intervention. When the DMA terminates the transfer, it disables the bus request line. The CPU disables the bus grant, takes control of the buses, and returns to its normal operation. DMA controller: The DMA controller needs an address register, a word count register and a set of address lines for communication. The unit communicates with CPU via the data bus and control lines. The register in the DMA are selected by the CPU through the address bus by enabling the DS (DMA select) and RS (Register select) inputs. The read and write inputs are bi directional. When the BG input is 0 the CPU can communicates with the DMA registers through the data bus to read from or write to the DMA register. When BG=1, the CPU frees the bus and DMA can communicate directly with the memory. Following figure shows block diagram of DMA controller
DMA controller has three register: Address register: The address register contains an address to specify the desired location in memory. The address register is incremented after each word is transferred to memory Word count register: It holds the number of words to be trans transfer and internally tested for zero. This register is decremented by one after each word transfer and internally tested for zero. Control register: The control register specifies the mode of transfer. DMA transfer: The CPU initializes the DMA by sending the following information 1) The starting address of the memory block where data are available or stored 2) The word count, which is the number of words in the memory block 3) Control to specify the mode of transfer such as read or write 4) A control to start the DMA transfer. The following figure shows DMA transfer in a computer system. When the peripheral device sends a DMA request DMA controller activates BR line.the CPU responds with BG line.the DMA sends acknowledgement to the peripheral
device. When BG=0 CPU communicates with DMA. When BG=1 DMA takes the control. Q8. What do you mean by page replacement? Explain different types of page replacement with examples. When a page fault occurs, the OS loads the faulted page from disk into a page frame memory. If the processor has used all frames the OS must replace a page for each page faulted in. This is known as page replacement. Page replacement algorithm determines the page to be replaced. There are three types of page replacement algorithms. 1) FCFS page replacement algorithm using 3 frames: In FIFO the algorithm selects for replacement the page which has been used for a longest period of time. Total number of page fault for the following is 15.
2) Optimal page replacement algorithm by using 3 frames: In optimal the algorithm selects the page which will not be used for a longest period of time. Total number of page fault for the following example is 9. 3) LRU page replacement algorithm by using 3 frames: In LRU the algorithm selects the page that has been least recently used. Total number of page fault for the following example is 12.