To Interface The 8085 Microprocessor

To Interface The 8085 Microprocessor A microprocessor has to be interfaced with various peripherals to perform various functions. Let's discuss about the Interfacing techniques in detail. Introduction We know that a microprocessor is the CPU of a computer. A microprocessor can perform some operation on a data and give the output. But to perform the operation we need an input to enter the data and an output to display the results of the operation. So we are using a keyboard and monitor as Input and output along with the processor. Microprocessors engineering involves a lot of other concepts and we also interface memory elements like ROM, EPROM to access the memory. Interfacing Types There are two types of interfacing in context of the 8085 processor. Memory Interfacing. I/O Interfacing. Memory Interfacing: While executing an instruction, there is a necessity for the microprocessor to access memory frequently for reading various instruction codes and data stored in the memory. The interfacing circuit aids in accessing the memory. Memory requires some signals to read from and write to registers. Similarly the microprocessor transmits some signals for reading or writing a data. But what is the purpose of interfacing circuit here? The interfacing process involves matching the memory requirements with the microprocessor signals. The interfacing circuit therefore should be designed in such a way that it matches the memory signal requirements with the signals of the microprocessor. For example for carrying out a READ process, the microprocessor should initiate a read signal which the memory requires to read a data. In simple words, the primary function of a memory interfacing circuit is to aid the microprocessor in reading and writing a data to the given register of a memory chip. I/O Interfacing: We know that keyboard and Displays are used as communication channel with outside world. So it is necessary that we interface keyboard and displays with the

microprocessor. This is called I/O interfacing. In this type of interfacing we use latches and buffers for interfacing the keyboards and displays with the microprocessor. But the main disadvantage with this interfacing is that the microprocessor can perform only one function. It functions as an input device if it is connected to buffer and as an output device if it is connected to latch. Thus the capability is very limited in this type of interfacing. Programmable Peripheral Devices Programmable peripheral devices were introduced by Intel to increase the overall performance of the system. These devices along with I/O functions, they perform various other functions such as time delays, counters and interrupt handling. These devices are nothing but a combination of many devices on a single chip. A programmable device can be set up to perform specific function by writing a code in the internal register. As this code controls the function of the device it s called control word and internal register in which it is stored is called Control Register. INTEL developed some peripheral devices for processors like 8085/8086/8088. The peripheral devices includes 8255 Parallel Communication Interface (PPI) 8251 Serial communication Interface (USART- Universal Synchronous/Asynchronous Receiver/Transmitter) 8257 DMA Controller 8279 Keyboard/Display Controller. 8259 Programmable Interrupt controller 8254 Programmable Timer

Types of Communication Interface There are two ways in which a microprocessor can connect with outside world or other memory systems. Serial Communication Interface Parallel Communication interface Serial Communication Interface: In serial communication interface, the interface gets a single byte of data from the microprocessor and sends it bit by bit to other system serially (or) the interface receives data bit by bit serially from the external systems and converts the data into a single byte and transfers it to the microprocessor. Parallel Communication Interface: This interface gets a byte of data from microprocessor and sends it bit by bit to the other systems in simultaneous (or) parallel fashion. The interface also receives data bit by bit simultaneously from the external system and converts the data into a single byte and transfers it to microprocessor. Consider that we have a microprocessor interfaced to both I/O device and also a memory chip. Now how to select between the two devices according to the requirement? For this purpose an address decoding circuit is used. An address decoding circuit aids in selecting the required I/O device or a memory chip. 1.THE 8255 PROGRAMMABLE PERIPHERAL INTERFACE (PPI). 8255 IS A WIDELY USED, PROGRAMMABLE, PARALLEL I/O DEVICE. It can be programmed to transfer data under various conditions from simple I/O to interrupt I/O. It is flexible, versatile & economical (when multiple I/O ports are required), but somewhat complex. It is an important general purpose I/O device that can be used with almost any P. BLOCK DIAGRAM & PIN CONFIGRATION OF 8255.

8255 Control Word format in the BSR Mode

Pinout

8254 PROGRAMMABLE INTERVAL TIMER Features Status read-back command Counter latch command Read/write least significant bit (LSB) only, most significant bit (MSB) only,or LSB first then MSB Six programmable counter modes o Interrupt on terminal count o Hardware retriggerable one-shot o Rate generator o Square wave mode

o Software-triggered strobe o Hardware-triggered strobe (retriggerable) Binary or binary coded decimal strobe Developed in VHDL and synthesizes to approximately 5,000 gates Functionally based on the Intel 82C54 device

Description The 8254 programmable interval time/counter megafunction is a highperformance function that is designed to solve the common timing control problems in microcomputer system design. It provides three independent 16-bit counters, and each counter may operate in a different mode. All modes are software programmable. The 8254 megafunction solves one of the most common problems in any microcomputer system: the generation of accurate time delays under software control. Instead of setting up timing loops in software, the 8254 megafunction can be

programmed to match requirements by programming one of the counters for the desired delay. OPERATIONAL DESCRIPTION General After power-up, the state of the 8254 is undefined.the Mode, count value, and output of all Counters are undefined.how each Counter operates is determined when it is programmed. Each Counter must be programmed before it can be used. Unused counters need not be programmed. By contrast, initial counts are written into the Counters,not the Control Word Register. The A1,A0 inputs are used to select the Counter to be written into. The format of the initial count is determined by the Control Word used. Write Operations The programming procedure for the 8254 is very flexible. Only two conventions need to be remembered: 1) For each Counter, the Control Word must be written before the initial count is written. 2) The initial count must follow the count format specified in the Control Word (least significant byte only, most significant byte only, or least significant byte and then most significant byte). Since the Control Word Register and the three Counters have separate addresses (selected by the A1,A0 inputs), and each Control Word specifies the Counter it applies to (SC0,SC1 bits), no special instruction sequence is required. Any programming sequence that follows the conventions in Figure 7 is acceptable. A new initial count may be written to a Counter at any time without affecting the Counter's programmed Mode in any way. Counting will be affected as described in the Mode definitions. The new count must follow the programmed count format.if a Counter is programmed to read/write two-byte counts, the following precaution applies: A program must not transfer control between writing the first and second byte to another routine which also writes into that same Counter. Otherwise, the Counter will be loaded with an incorrect count. Read Operations

It is often desirable to read the value of a Counter without disturbing the count in progress. This is easily done in the 8254 There are three possible methods for reading the counters: a simple read operation, the Counter Latch Command, and the Read-Back Command.Each is explained below. The first method is to perform a simple read operation. To read the Counter,which is selected with the A1, A0 inputs, the CLK input of the selected Counter must be inhibited by using either the GATE input or external logic. Otherwise, the count may be in the process of changing when it is read, giving an undefined result. Mode Definitions The following are defined for use in describing the operation of the 8254. CLK Pulse: a rising edge, then a falling edge, in that order, of a Counter's CLK input.trigger: a rising edge of a Counter's GATE input. Counter loading: the transfer of a count from the CR to the CE (refer to the ``Functional Description'') MODE 0: INTERRUPT ON TERMINAL COUNT Mode 0 is typically used for event counting. After the Control Word is written, OUT is initially low, and will remain low until the Counter reaches zero. OUT then goes high and remains high until a new count or a new Mode 0 Control Word is written into the Counter. GATE = 1 enables counting; GATE = 0 disables counting. GATE has no effect on OUT. After the Control Word and initial count are written to a Counter, the initial count will be loaded on the next CLK pulse. This CLK pulse does not decrement the count, so for an initial count of N, OUT does not go high until N a 1 CLK pulses after the initial count is written. If a new count is written to the Counter, it will be loaded on the next CLK pulse and counting will continue from the new count. If a two-byte count is written,the following happens: 1) Writing the first byte disables counting. OUT is set low immediately (no clock pulse required) 2) Writing the second byte allows the new count to be loaded on the next CLK pulse. This allows the counting sequence to be synchronized by software. Again, OUT does not go high until Na1 CLK pulses after the new count of N is written. If an initial count is written while GATE e 0, it will still be loaded on the next CLK pulse. When GATE goes high, OUT will go high N CLK pulses later; no CLK pulse is needed to load the Counter as this has already been done.

MODE 1: HARDWARE RETRIGGERABLE ONE-SHOT OUT will be initially high. OUT will go low on the CLK pulse following a trigger to begin the one-shot pulse,and will remain low until the Counter reaches zero. OUT will then go high and remain high until the CLK pulse after the next trigger.

After writing the Control Word and initial count, the Counter is armed. A trigger results in loading the Counter and setting OUT low on the next CLK pulse,thus starting the one-shot pulse. An initial count of N will result in a one-shot pulse N CLK cycles in duration. The one-shot is retriggerable, hence OUT will remain low for N CLK pulses after any trigger. The one-shot pulse can be repeated without rewriting the same count into the counter. GATE has no effect on OUT If a new count is written to the Counter during a oneshot pulse, the current one-shot is not affected unless the counter is retriggered. In that case, the Counter is loaded with the new count and the oneshot pulse continues until the new count expires. MODE 2: RATE GENERATOR This Mode functions like a divide-by-n counter. It is typically used to generate a Real Time Clock interrupt.out will initially be high. When the initial count has decremented to 1, OUT goes low for one CLK pulse. OUT then goes high again, the Counter reloads the initial count and the process is repeated.mode 2 is periodic; the same sequence is repeated indefinitely. For an initial count of N, the sequence repeats every N CLK cycles.

GATE = 1 enables counting; GATE = 0 disables counting. If GATE goes low during an output pulse,out is set high immediately. A trigger reloads the Counter with the initial count on the next CLK pulse;out goes low N CLK pulses after the trigger. Thus the GATE input can be used to synchronize the Counter. After writing a Control Word and initial count, the Counter will be loaded on the next CLK pulse. OUT goes low N CLK Pulses after the initial count is written. This allows the Counter to be synchronized by software also. Writing a new count while counting does not affect the current counting sequence. If a trigger is received after writing a new count but before the end of the current period, the Counter will be loaded with the new count on the next CLK pulse and counting will continue from the new count. Otherwise, the new count will be loaded at the end of the current counting cycle. In mode 2, a COUNT of 1 is illegal. MODE 3: SQUARE WAVE MODE

Mode 3 is typically used for Baud rate generation.mode 3 is similar to Mode 2 except for the duty cycle of OUT. OUT will initially be high. When half the initial count has expired, OUT goes low for the remainder of the count. Mode 3 is periodic; the sequence above is repeated indefinitely. An initial count of N results in a square wave with a period of N CLK cycles. GATE e 1 enables counting; GATE e 0 disables counting. If GATE goes low while OUT is low, OUT is set high immediately; no CLK pulse is required. A trigger reloads the Counter with the initial count on the next CLK pulse. Thus the GATE input can be used to synchronize the Counter. After writing a Control Word and initial count, the Counter will be loaded on the next CLK pulse. This allows the Counter to be synchronized by software also. Writing a new count while counting does not affect the current counting sequence. If a trigger is received after writing a new count but before the end of the current half-cycle of the square wave, the Counter will be loaded with the new count on the next CLK pulse and counting will continue from the new count. Otherwise, the new count will be loaded at the end of the current half-cycle. Mode 3 is implemented as follows: Even counts: OUT is initially high. The initial count is loaded on one CLK pulse and then is decremented by two on succeeding CLK pulses. When the count expires OUT changes value and the Counter is reloaded with the initial count. The above process is repeated indefinitely. Odd counts: OUT is initially high. The initial count minus one (an even number) is loaded on one CLK pulse and then is decremented by two on succeeding CLK pulses. One CLK pulse after the count expires,out goes low and the Counter is reloaded with the initial count minus one. Succeeding CLK pulses decrement the count by two. When the count expires, OUT goes high again and the Counter is reloaded with the initial count minus one. The above process is repeated indefinitely. So for odd counts, OUT will be high for (N a 1)/2 counts and low for (N b 1)/2 counts

MODE 4: SOFTWARE TRIGGERED STROBE OUT will be initially high. When the initial count expires,out will go low for one CLK pulse and then go high again. The counting sequence is ``triggered'' by writing the initial count. GATE = 1 enables counting; GATE = 0 disables counting. GATE has no effect on OUT After writing a Control Word and initial count, the Counter will be loaded on the next CLK pulse. This CLK pulse does not decrement the count, so for an initial count of N, OUT does not strobe low until N a 1 CLK pulses after the initial count is written. If a new count is written during counting, it will be loaded on the next CLK pulse and counting will continue from the new count. If a two-byte count is written,the following happens: 1) Writing the first byte has no effect on counting. 2) Writing the second byte allows the new count to be loaded on the next CLK pulse. This allows the sequence to be ``retriggered'' by software. OUT strobes low N a 1 CLK pulses after the new count of N is written.

MODE 5: HARDWARE TRIGGERED STROBE (RETRIGGERABLE)

OUT will initially be high. Counting is triggered by a rising edge of GATE. When the initial count has expired, OUT will go low for one CLK pulse and then go high again. After writing the Control Word and initial count, the counter will not be loaded until the CLK pulse after a trigger. This CLK pulse does not decrement the count, so for an initial count of N, OUT does not strobe low until N a 1 CLK pulses after a trigger. A trigger results in the Counter being loaded with the initial count on the next CLK pulse. The counting sequence is retriggerable. OUT will not strobe low for N a 1 CLK pulses after any trigger. GATE has no effect on OUT. If a new count is written during counting, the current counting sequence will not be affected. If a trigger occurs after the new count is written but before the current count expires, the Counter will be loaded with the new count on the next CLK pulse and counting will continue from there

APPLICATIONS Unipolar full step Stepper motor: INPUT SEQUENCE: X Y X Y 1 1 0 0 0 1 1 0 0 0 1 1 1 0 0 1 8255 CONTROL WORD: 1 0 0 0 0 0 0 0 =80H PROGRAM: MVI A, 80 OUT port B START MVI A, FC OUT port A CALL DELAY MVI A, F6 OUT port A CALL DELAY MVI A, F3 OUT port A CALL DELAY MVI A, F9 OUT port A JMP START DELAY LXI D, 0003 CALL DELAY RET

MULTIPLE CHOICE: 1. If an information flows from memory to microprocessor, which signal is used by it 2. is used to enable the memory chip 3.If the starting address of 6K memory is 0D00, then ending address will be 4.. If an information flows to memory, which signal is used by it 5. The assignment of addresses to various I/O devices in a memory chip is called 6. is used to demultiplex address and data bus. 7. applications of stepper motor 8. is the maximum possible memory size which can be used in a microprocessor QUESTIONS 1. Name the two modes of operation of DMA controller? 2. List the operating modes of 8253 timer. 3. Give the control word format of timer? 4. What is the use of USART? 5. Compare serial and parallel communication. 6. What is the use of Keyboard and display controller? 7. What are the functions performed by 8279? 8. What is PPI? 9. Give the control word format for I/O mode of 8255? 10. Give the BSR mode format of 8255. 11. What is the need for interrupt controller? 12. What are the registers present in 8259? 13. What are the applications of 8253? 14. Define interrupts. 15. Define DMA process. 16. Give the status word format of 8257. 17. Draw the Block diagram and explain the operations of 8251 serial communication interface. 18. Draw the Block diagram of 8279 and explain the functions of each block. 19. Draw the block diagram of programmable interrupt controller and explain its operations. 20. Discuss in detail about the operation of timer along with its various modes. 21. Draw the Block diagram of DMA controller and explain its operations. 22.What does the CPU do when it receive an interrupt? How do you enable and disable interrupts in 8086.

23 Explain the command words/control words of 8259 in details. 24. With the help of block diagram explain various modes of operation of 8259 in details. 25. Explain type 0,1,2 interrupts found interrupt vector table of 8086/8088 microprocessor. 26. Describe the use of CAS0, CAS and CAS2 lines in a system with a cascaded 8259 s. 27. What are the different modes of operation of the 8253 programmable timer? How does 8254 differ from 8253? 28. Which mode will you use to generate a square wave? Give a flow chart to generate it on 8253. 29. Explain with neat waveform the mode 0 of the 8253 timer/counter. 30. Explain with the help of block diagram, functioning of 8253 in various programmable modes. 31. A 32-bit binary counter is to be implemented using timer/counter i)design and explain the control word to meet above requirement ii)draw timing diagram of the mod(s) used.