Tekms TK68020 Micrprcessr September 3, 2014 Prduct Overview Features Addressing Mde Extensins fr Enhanced Supprt f High-Level Languages Object-Cde Cmpatible with Earlier M68000 Micrprcessrs Addressing Mde Extensins fr Enhanced Supprt f High-Level Languages New Bit Field Data Type Accelerates Bit-Oriented Applicatins e.g., Vide Graphics An On-Chip Instructin Cache fr Faster Instructin Executin Cprcessr Interface t Cmpanin 32-Bit Peripherals-the MC68881 and MC68882 Flating-Pint Cprcessrs and the MC68851 Paged Memry Management Unit Pipelined Architecture with High Degree f Internal Parallelism Allwing Multiple Instructins T Be Executed Cncurrently High-Perfrmance Asynchrnus Bus Is Nnmultiplexed and Full 32 Bits Dynamic Bus Sizing Efficiently Supprts 8-/16-/32- Bit Memries and Peripherals Full Supprt f Virtual Memry and Virtual Machine Sixteen 32-Bit General-Purpse Data and Address Registers Tw 32-Bit Supervisr Stack Pinters and Five Special-Purpse Cntrl Registers Eighteen Addressing Mdes and Seven Data Types 4-Gbyte Direct Addressing Range 16-Mbyte Direct Addressing Rang Selectin f Prcessr Speeds 16.67. 20, 25, and 33.33 MHz Available in mdified 132 pin BQFP (Using adaptr) see mechanical data sectin. General Descriptin The TK68020 is a functinal equivalent f the Mtrla M68020 and they are pin-fr-pin cmpatible. It is a full 32-bit implementatin f the M68000 family f micrprcessrs frm Mtrla. The TK68020 is a full 32-bit implementatin f the 68000 family f micrprcessrs frm Mtrla. The TK68020 is implemented with 32-bit registers and data paths, 32-bit addresses, a rich instructin set, and versatile addressing mdes. The TK68020 is bject-cde cmpatible with earlier members f the 68000 family and has the added features f new addressing mdes in supprt f highlevel languages, an n-chip instructin cache, and a flexible cprcessr interface with full IEEE flating-pint supprt available. The internal peratins f this micrprcessr perate in parallel, allwing multiple instructins t be executed cncurrently. The asynchrnus bus structure f the TK68020 uses a nn-multiplexed bus with 32 bits f address and 32 bits f data. The prcessr supprts a dynamic bus sizing mechanism that allws the prcessr t transfer perands t r frm external devices while autmatically determining device prt size n a cycle-by-cycle basis. The dynamic bus interface allws access t devices f differing data bus widths, in additin t eliminating all data alignment restrictins. TK68020 (Tp View) 9/03/14 www.tekms.cm 1
Tekms TK68020 Micrprcessr Figure 1 TK68020 Blck Diagram 9/03/14 www.tekms.cm 2
Tekms Prgramming Mdel The prgramming mdel f the TK68020 cnsists f tw grups f registers, the user mdel and the supervisr mdel, that crrespnd t the user and supervisr privilege levels, respectively. User prgrams executing at the user privilege level use the registers f the user mdel. System sftware executing at the supervisr level uses the cntrl registers f the supervisr level t perfrm supervisr functins. As shwn in the prgramming mdels (see Figure 2 and Figure 3), the TK68020 has 16 32-bit general-purpse registers, a 32-bit PC, tw 32-bit SSPs, a 16-bit SR, a 32- bit VBR, tw 3-bit alternate functin cde registers, and tw 32-bit cache handling (address and cntrl) registers. The user prgramming mdel remains unchanged frm earlier 68000 family micrprcessrs. The supervisr prgramming mdel supplements the user prgramming mdel and is used exclusively by TK68020 system prgrammers wh utilize the supervisr privilege level t implement sensitive perating system functins. The supervisr prgramming mdel cntains all the cntrls t access and enable the special features f the TK68020. All applicatin sftware, written t run at the nn-privileged user level, migrates t the MC68020 frm any 68000 platfrm withut mdificatin. Registers D7-D0 are data registers used fr bit and bit field (1 t 32 bits}, byte (8 bit), wrd (16 bit), lng-wrd (32 bit). and quad-wrd (64 bit) peratins. Registers A6- AO and the USP, ISP, and MSP are address registers that may be used as sftware stack pinters r base address registers. Register A7 (shwn as A7 in Figure 1-2 and as A7' and A7'' in Figure 1-3) is a register designatin that applies t the USP in the user privilege level and t either the ISP r MSP in the supervisr privilege level. In the supervisr privilege level, the active stack pinter (interrupt r master) is called the SSP. In additin, the address registers may be used fr wrd and lng-wrd peratins. All f the 16 general-purpse registers (D7-D0, A7-AO) may be used as index registers. The PC cntains the address f the next instructin t be executed by the TK68020. During instructin executin and exceptin prcessing, the prcessr autmatically increments the cntents f the PC r places a new value in the PC, as apprpriate. The SR (see Figure 4) stres the prcessr status. It cntains the cnditin cdes that reflect the results f a previus peratin and can be used fr cnditinal instructin executin in a prgram. The cnditin cdes are extend (X), negative (N), zer (Z), verflw (V), and carry (C). The user byte, which cntains the cnditin cdes, is the nly prtin f the SR infrmatin available in the user privilege level, and it is referenced as the TK68020 Micrprcessr CCR in user prgrams. In the supervisr privilege level, sftware can access the entire SR, including the interrupt pririty mask (three bit s) and cntrl bits that indicate whether the prcessr is in: 1. One f tw trace mdes (T1, TO) 2. Supervisr r user privilege level (S) 3. Master r interrupt mde (M) The VBA cntains the base address f the exceptin vectr table in memry. The displacement f an exceptin vectr is added t the value in this register t access the vectr table. The alternate functin cde registers, SFC and DFC, cntain 3-bit functin cdes. Fr the TK68020, functin cdes can be cnsidered extensins f the 32-bit linear address that ptinally prvide as many as eight 4-Gbyte address spaces. Functin cdes are autmatically generated by the prcessr t select address spaces fr data and prgram at the user and supervisr privilege levels and t select a CPU address space fr prcessr functins (e.g., cprcessr cmmunicatins). Registers SFC and DFC are used by certain instructins t explicitly specify the functin cdes fr peratins. The CACA cntrls the n-chip instructin cache f the TK68020. The CAAR stres an address fr cache cntrl functins. Data Types And Addressing Mdes Overview Fr detailed infrmatin n the data types and addressing mdes supprted by the TK68020, refer t 68000 Family Prgrammer's Reference Manuals. The TK68020 supprts seven basic data types: 1. Bits 2. Bit Fields (Fields f cnsecutive bits, (32 bits lng) 3. BCD Digits (Packed: 2 digits/byte, Unpacked: 1 digit/byte) 4. Byte Integers (8 bits) 5. Wrd Integers (16 bits) 6. Lng-Wrd Integers (32 bits) 7. Quad-Wrd Integers (64 bits) In additin, the TK68020 instructin set supprts peratins n ther data types such as memry addresses. The cprcessr mechanism allws direct supprt f flating pint peratins with the MC68881 and MC68882 flating-pint cprcessrs as well as specialized user-defined data types and functins. 9/03/14 www.tekms.cm 3
Tekms TK68020 Micrprcessr Figure 2 Figure 3 Figure 4 9/03/14 www.tekms.cm 4
Tekms TK68020 Micrprcessr The 18 addressing mdes listed in Table 1 include nine basic types: 1. Register Direct 2. Register Indirect 3. Register Indirect with Address 4. Memry Indirect 5. PC Indirect with Displacement 6. PC Indirect with Index 7. PC Memry Indirect 8. Abslute 9. Immediate The register indirect addressing mdes have pstincrement, pre-increment, displacement and index capabilities. The PC mdes have index and ffset capabilities. Bth mdes are extended t prvide indirect reference thrugh memry. In additin t these addressing mdes, many instructins specify the use f CCR, stack pinter, and/r PC. Table 1. Addressing Mdes 9/03/14 www.tekms.cm 5
Tekms Instructin Set Overview Fr detailed infrmatin n the TK68020 instructin set, refer t M6BOOOPM/AD. The instructins in the TK68020 instructin set are listed in Table 2. The instructin set has been tailred t supprt structured high-level languages and sphisticated perating systems. Many instructins perate n bytes, wrds, r lng wrd, and mst instructins can use any f the 18 addressing mdes. Virtual Memry And Virtual Machine Cncepts The full addressing range f the TK68020 is 4 Gbytes (4,294,967,296 bytes) in each f eight address spaces. Even thugh mst systems implement a smaller physical memry, the system can be made t appear t have a full 4 Gbytes f memry available t each user prgram by using virtual memry techniques. In a virtual memry system, a user prgram can be written as if it has a large amunt f memry available, althugh the physical memry actually present is much smaller. Similarly, a system can be designed t allw user prgrams t access devices that are nt physically present in the system, such as tape drives, disk drives, printers, terminals, and s frth. With prper sftware emulatin, a physical system can appear t be any ther M68000 cmputer system t a user prgram, and the prgram can be given full access t all f the resurces f that emulated system. Such an emulated system is called a virtual machine. Virtual Memry A system that supprts virtual memry has a limited amunt f high-speed physical memry that can be accessed directly by the prcessr and maintains an image f a much larger virtual memry n a secndary strage device such as a large-capacity disk drive. When the prcessr attempts t access a lcatin in the virtual memry map that is nt resident in physical memry, a page fault ccurs. The access t that lcatin is temprarily suspended while the necessary data is fetched frm secndary strage and placed in physical memry. The suspended access is then either restarted r cntinued. The TK68020 uses instructin cntinuatin t supprt virtual memry. When a bus cycle is terminated with a bus errr, the micrprcessr suspends the current instructin and executes the virtual memry bus errr handler. When the bus errr handler has cmpleted executin, it returns cntrl t the prgram that was executing when the errr was detected, reruns the faulted bus cycle (when required), and cntinues the suspended instructin. TK68020 Micrprcessr Virtual Machine A typical use fr a virtual machine system is the develpment f sftware, such as an perating system, fr a new machine als under develpment and nt yet available fr prgramming use. In a virtual machine system, a gverning perating system emulates the hardware f the new machine and allws the new sftware t be executed and debugged as thugh it were running n the new hardware. Since the new sftware is cntrlled by the gverning perating system, it is executed at a lwer privilege level than the gverning perating system. Thus, any attempts by the new sftware t use virtual resurces that are nt physically present (and shuld be emulated) are trapped t the gverning perating system and perfrmed by its sftware. In the TK6B020 implementatin f a virtual machine, the virtual applicatin runs at the user privilege level. The gverning perating system executes at the supervisr privilege level and any attempt by the new perating system t access supervisr resurces r execute privileged instructins causes a trap t the gverning peratin system. Instructin cntinuatin is used t supprt virtual 1/0 devices in memry mapped input/utput systems. Cntrl and data registers fr the virtual device are simulated in the memry map. An access t a virtual register causes a fault, and the functin f the register is emulated by sftware. Pipelined Architecture The TK68020 cntains a three-wrd instructin pipe where instructin pcdes are decded. As shwn in Figure 5, instructin wrds (instructin peratin wrds and all extensin wrds) enter the pipe at stage 8 and prceed t stages C and D. An instructin wrd is cmpletely decded when it reaches stage D f the pipe. Each stage has a status bit that reflects whether the wrd in the stage was laded with data frm a bus cycle that was terminated abnrmally. Stages f the pipe are nly filled in respnse t specific prefetch requests issued by the sequencer. Wrds are laded int the instructin pipe frm the cache hlding register. Althugh the individual stages f the pipe are nly 16 bits wide, the cache hlding register is 32 bits wide and cntains the entire lng wrd. This lng wrd is btained frm the instructin cache r the external bus in respnse t a prefetch request frm the sequencer. When the sequencer requests an even-wrd (lng-wrd-aligned) prefetch, the entire lng wrd is accessed frm the instructin cache r the external bus and laded int the cache hlding register, and the highrder wrd is als laded int stage B f the pipe. The instructin wrd fr the next sequential prefetch can then be accessed directly frm the cachehlding register, and n external bus cycle r instructin cache access is required. The cache hlding register prvides instructin wrds t the pipe regardless f whether the instructin cache is enabled r disabled. 9/03/14 www.tekms.cm 6
Tekms TK68020 Micrprcessr Table 2 Figure 5 9/03/14 www.tekms.cm 7
Tekms TK68020 Micrprcessr The sequencer is either executing micrinstructins r awaiting cmpletin f accesses that are necessary t cntinue executing micrcde. The bus cntrller is respnsible fr all bus activity. The sequencer cntrls the bus cntrller, instructin executin, and internal prcessr peratins such as the calculatin f effective addresses and the setting f cnditin cdes. The sequencer initiates instructin wrd prefetches and cntrls the validatin f instructin wrds in the instructin pipe. Prefetch requests are simultaneusly submitted t the cache hlding register, the instructin cache, and the bus cntrller. Thus, even if the instructin cache is disabled, an instructin prefetch may hit in the cache hlding register and cause an external bus cycle t be abrted. Cache Memry Due t lcality f reference, instructins that are used in a prgram have a high prbability f being reused within a shrt time. Additinally, instructins that reside in prximity t the instructins currently in use als have a high prbability f being utilized within a shrt perid. T explit these lcality characteristics, the TK68020 cntains an n-chip instructin cache. The cache imprves the verall perfrmance f the system by reducing the number f bus cycles required by the prcessr t fetch infrmatin frm memry and by increasing the bus bandwidth available fr ther bus masters in the system. Electrical Characteristics Table 3 Table 4 9/03/14 www.tekms.cm 8
Tekms Mechanical Data The Tekms TK68020 features a 144 pin TQFP attached t an adapter card t allw the adapter t fit the same ftprint as the BQFP it replaces. (Plastic BQFP are nt TK68020 Micrprcessr available.) As shwn in Figure 7, there are n crner bumpers n this adapter card versin. Figure 6 9/03/14 www.tekms.cm 9
Tekms TK68020 Micrprcessr TK68020 (Tp View) Figure 7 9/03/14 www.tekms.cm 10
Tekms TK68020 Micrprcessr Ordering Infrmatin Cde Temperature Package Frequency TK68020FC16E 0 t +70C Mdified 132 pin BQFP (Using adaptr) - RHS 16 MHz Cntact Infrmatin The TK68020 may be rdered directly frm Tekms: Tekms, Inc. 4120 Cmmercial Center Drive Suite 400 Austin, TX 78744 512 342-9871 phne 512 342-9873 fax Sales@Tekms.Cm www.tekms.cm Revisin Histry Date Revisin Descriptin 1/26/14 1.0 Initial Release 9/03/14 1.1 Ceramic package reference remved 2014 Tekms, Inc. Infrmatin cntained in this publicatin regarding device applicatins and the like is intended fr suggestin nly and may be superseded by updates. N representatin r warranty is given and n liability is assumed by Tekms Incrprated with respect t the accuracy r use f such infrmatin r infringement f patents r ther intellectual prperty rights arising frm such use r therwise. Use f Tekms prducts as critical cmpnents in life supprt systems is nt authrized except with express written apprval by Tekms. N licenses are cnveyed, implicitly r therwise, under any intellectual prperty rights. The Tekms lg and name are registered trademarks f Tekms, Inc. All rights reserved. All ther trademarks mentined herein are the prperty f their respective cmpanies. All rights reserved. Terms and prduct names in this dcument may be trademarks f thers. 11 www.tekms.cm 9/03/14