Fundamentals of Computer Organization and Design Errata Sivarama P. Dandamudi School of Computer Science Carleton University September 8, 2003
Chapter 2 Digital Logic Basics 1. Page 81, Exercise 2-22 Replace the exercise in the book by the following: Using Boolean algebra show that the following two expressions are equivalent: A B C + A C D + A B C + A B D + ABC + AC + A BCD A + B D + C D + B C + BCD 1
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Chapter 3 Combinational Circuits 1. Page 88, Figure 3.6 The output of the MUX should be F 1 (not F 2 as given in this figure). 2. Page 104, Figure 3.28 Replace the figure with the following (essentially deletes the useless XOR gate):......... A 15 B 15 A B 1 A 0 B 0 F 1 F 0 1 Carry out A C out B F 1 F 0 C in... A C out B F 1 F 0 C in A C out B F 1 F 0 C in F F F R 15... R 1 R 0 Figure 3.28 A 16-bit ALU built with the 1-bit ALU. 3. Page 104, last line The last line the rightmost bit set to 1 (through the XOR gate): should be replaced with the rightmost bit set to 1 (through the F 0 bit): 3
4 Chapter 4 The following corrections are related to the exercises. 4. Page 107, Exercise 3 8 Add the following clarification: If you need to, you can use one additional inverter in your implementation. 5. Page 107, Exercise 3 12 Add the following clarification: If you need to, you can use one additional inverter in your implementation. 6. Page 107, Exercise 3 13 Revise the exercise as follows: Implement the O 0 and O 1 outputs of the priority encoder, shown in Figure 3.14, using a 74153 multiplexer chip. If you need to, you can use one additional inverter in your implementation. 7. Page 107, Exercise 3 14 Add the following clarification: If you need to, you can use one additional inverter in your implementation. 8. Page 108, Exercise 3 20 Add the following clarification: Set both quotient and remainder to zero when dividing by zero. 9. Page 108, Exercise 3 23 Revise the exercise as follows: Implement the O 0 and O 1 outputs of the priority encoder, shown in Figure 3.14, using a PLA (with four inputs and two outputs). Use the simplified notation to express your design. 10. Page 108, Exercise 3 25 Delete it (as we deleted the XOR gate from Figure 3.28). 11. Page 108, Exercise 3 26 Delete it (same as Exercise 3 12).
Chapter 5 System Buses 1. Page 170, Figure 5.16 3.3 V 32-bit connector should be 3.3 V 64-bit connector 3.3 V 64-bit connector should be 3.3 V 32-bit connector The revised figure is shown below: 3.3 V 64 bit connector 000000000000 111111111111 000000000000000000000000000000000 111111111111111111111111111111111000000000000 32 bit section 64 bit section 000000000000 111111111111 000000000000000000000000000000000 111111111111111111111111111111111 3.3 V 32 bit connector 5 V 32 bit connector 1111111111111111111111111111111111 000000000000000000000000000000000011111111111 32 bit section 64 bit section 1111111111111111111111111111111111 000000000000000000000000000000000011111111111 000000000000 111111111111 5 V 64 bit connector Figure 5.16 PCI connectors for 5 V and 3.3 V. 5
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Chapter 8 Pipelining and Vector Processing 1. Page 310, Figure 8.26 V2 V3+FV4 should be V1 V2+FV3 The revised figure is shown below: Instruction A1 5 I E VL A1 I V1 V2 + FV3 2. Page 311, Figure 8.27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 E I S S S F F F F F R1 R2 R3 R4 R5 D D D Setup phase Shutdown phase Figure 8.26 Timing analysis of a simple vector addition operation. V2 V3+FV4 should be V1 V2+FV3 V5 V6*FV7 should be V4 V5*FV6 The revised figure is shown below: Instruction 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 A1 5 I E VL A1 I E V1 V2 + FV3 I S S S F F F F F R1 R2 R3 R4 R5 D D D V4 V5 * FV6 I S S S F F F F F F R1 R2 R3 R4 R5 D D D Figure 8.27 Overlapped execution of floating-point addition and multiplication operations. 7
8 Chapter 8 3. Page 312, Figure 8.28 V2 V3+FV4 should be V1 V2+FV3 V5 V2*FV7 should be V4 V5*FV1 The revised figure is shown below: Instruction 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 A1 5 I E VL A1 I E V1 V2 + FV3 I S S S F F F F F R1 R2 R3 R4 R5 D D D V4 V5 * FV1 I S S S H H H H H H H F F F F F F R1 R2 R3 R4 R5 D D D Multiply unit on hold 20 21 22 23 24 25 26 27 28 Figure 8.28 A vector chaining example.
Chapter 9 Overview of Assembly Language 1. Page 354, Table at the top loopnz should be loopnz target Loop while zero target Loop while not zero 2. Page 377, Program 9.4 Line 37: delete nwln 9
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Chapter 14 RISC Processors 1. Page 579, Second line from bottom bc/bca should be bcl/bcla 2. Page 610, Last line dpnt Dynamic branch taken should be dptk Dynamic branch taken 11
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Chapter 16 Memory System Design 1. Page 692, Exercise 16 26 152, 320, 868, 176, should be 152, 320, 864, 176, 13
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Chapter 17 Cache Memory 1. Page 724, Table 17.6 Last line, second column: Qrite-back should be Write-back 15
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Chapter 18 Virtual Memory 1. Page 745, Example 18.1 3rd line: 2 40 2 12 =2 28 should be 2 40 =2 12 =2 28 17
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Chapter 19 Input/Output Organization 1. Page 824, Exercise 19 16 received incorrectly should be received correctly 2. Page 824, Exercise 19 17 received correctly should be received incorrectly 3. Page 824, Exercise 19 21 Hint: Use a multiplexer and XOR gates should be Hint: Use a decoder and XOR gates 19