Hardware and Software Architecture Chapter 2 1
Basic Components The x86 processor communicates with main memory and I/O devices via buses Data bus for transferring data Address bus for the address of a memory location or an I/O port Control bus for control signals (Interrupt request, memory read/write ) Each operation must be synchronized by the system clock Registers are high-speed storage within the processor 2
Central Processing Unit The operation of the CPU can be reduced to three basic steps: 1) Fetch 2) Decode 3) Execute Each step includes intermediate steps. 3
The Fetch-Decode-Execute Cycle Is the basic cycle for instruction execution Fetch the next instruction place it in queue update program counter Decode the instruction perform address translation fetch operands from memory Execute the instruction store result in memory or registers set status flags according to result Before fetching next instruction, the CPU checks if an interrupt is pending (more on that later) 4
Simplified CPU Design Data Bus Data Registers Address Registers Control Unit Arithmetic Logic Unit Status Flags Memory Address Bus Copyright 1999-2001, Kip R. Irvine. All rights reserved.
Address and data Buses The internal data bus is a series of parallel wires that transmit data between various parts of the CPU. When data must be read from external memory control unit calculates its address and places the address on the address bus. Registers Within the CPU are high speed storage areas called registers, which are linked directly by an internal control unit and the arithmetic logic unit. Clock Each of the individual operations take place within the CPU must be synchronized by an internal clock. The most basic unit of time for machine instructions is called the machine cycle or clock cycle, and is measured in millions of cycles per seconds (MHz). 6
16-Bit Register Set (Intel 8086, 8088, 80286) Registers are 8, 16 or 32 bit high speed storage locations directly inside the CPU and are designed to be accessed on much faster Speed than conventional memory. The CPU has an internal data bus that is generally twice wide as its external data bus. When a processing loop must be optimized for speed, e.g. We would almost always use registers for calculations and decision Making inside the loop. the 8086, 8088 and 80286 processors have 16-bit registers. more... Copyright 1999-2001, Kip R. Irvine. All rights reserved.
Intel 16-bit Registers Ge ne ral Purpose Index AX AH AL BP SP BX BH BL SI CX CH CL DI DX DH DL Segment CS Status and Control Flags IP SS DS ES Copyright 1999-2001, Kip R. Irvine. All rights reserved.
Data Registers (also called general purpose registers) AX (Accumulator) It is favored by CPU for arithmetic operations. Other operations are also slightly more efficient when performed using AX. BX (base) It can hold the address of a procedure or variable. Three other registers with this ability are SI,DI and BP. It can also perform arithmetic and data movement CX (counter) It acts as a counter for repeating or looping instruction. These instructions automatically repeat and decrement CX. DX (data) It has special role in multiply and divide operations. When multiplying e.g. DX holds the high 16 bits of the product. 9
Segment Registers The CPU contains four segment registers used as base locations for program instructions, data and the stack. CS (code) It holds the base location of all executable instructions (code) in a program. DS (data) It is the default base location for variables.the CPU calculates their locations using the segment value in DS. SS (stack) It contains the base location of the stack. ES (extra data) It is an additional base location for memory variables. 10
Index Registers 11 It contains the offset of data and instructions. It speed up processing of strings, arrays, and other data structures containing multiple elements. BP (base pointer) It contained the assumed offset from the SS register as does the stack pointer. It is also used by the subroutine to locate variables that are passed on the stack by a calling program. SP (stack pointer) It contains the offset of the top of the stack. The SP and SS register combine to complete the address of the top of the stack. SI (source index) It takes its name from the string movement instructions in which the source string is pointed to by the SI register. DI (destination index) It acts as the destination for string movement instructions.
Status and Control Registers IP (instruction pointer) always contains the offset of the instruction to be executed next within the current code segment The FLAGS register consist of individual bits indicating either the mode of operation of the CPU (control flag) the outcome of an arithmetic operation (status) 12
Instruction Execution Cycle Fetch the next instruction place in queue update program counter Decode the instruction perform address translation fetch operands Execute the instruction perform required operation store the results in memory and/or registers update status flags attached to CPU more... Copyright 1999-2001, Kip R. Irvine. All rights reserved.
Intel Microprocessor Family Intel 8080 8-bit registers, 8-bit external data path addresses 64K memory Intel 8086 16-bit registers, 16-bit external data path addresses 1MB memory supports real mode Intel 8088 identical to 8086, except with 8-bit external data path Copyright 1999-2001, Kip R. Irvine. All rights reserved.
Intel Microprocessor Family Intel 8087 coprocessor executes only floating-point instructions Intel 80286 addresses 16MB of memory supports real mode and protected mode Intel 80287 coprocessor executes only floating-point instructions Copyright 1999-2001, Kip R. Irvine. All rights reserved.
Intel Microprocessor Family Intel386 (Intel 80386) 32-bit registers, 32-bit external data path addresses 4GB of memory supports real mode, protected mode and virtual mode Copyright 1999-2001, Kip R. Irvine. All rights reserved.
Intel Microprocessor Family Intel486 parallel instruction execution, modeled after competing RISC processors integrated floating-point unit internal 8K high-speed cache Copyright 1999-2001, Kip R. Irvine. All rights reserved.
Intel Microprocessor Family Intel Pentium (Intel586) early 90MHz model was at least 90% faster than Intel486 superscalar architecture (two instruction pipelines) 64-bit internal data path 16K internal cache (8K data, 8K code) Copyright 1999-2001, Kip R. Irvine. All rights reserved.
Intel Microprocessor Family Intel Pentium II 500 MHz clock speeds branch prediction logic out-of-order instruction execution larger internal cache Copyright 1999-2001, Kip R. Irvine. All rights reserved.
Improved Instruction Execution Cycle The 80386 was the first processor in the Intel family to include parallel stages in its execution cycle. The six stages and the parts of the processor that carry them out are: 1) Bus Interface Unit(BIU) It accesses memory and provide input-output. 2) Code Prefetch Unit It receives machine instructions from BIU and inserts them into the instruction prefetch queue. 3) Instruction Decode Unit It decodes machine instructions from the prefetch queue and translate them into microcode. 20
4) Execution Unit It executes the microcode instruction produced by the instruction decode unit. 5) Segment Unit It translates logical addresses to linear address and perform protection checks. 6) Paging Unit It translates linear addresses into physical addresses and performs page protection checks and keeps the list of recently accessed pages. 21
32-bit Register Set (Intel386, Intel486, Pentium) General Purpose Index EAX 31 0 AX EBP ESP BP SP EBX BX ESI SI ECX CX EDI DI EDX DX Segment EFLAGS EIP Status and Control Flags IP CS SS DS ES FS GS code stack data Copyright 1999-2001, Kip R. Irvine. All rights reserved.
Types of Memory ROM (read-only memory) used for BIOS (basic input-output system) write-once memory EPROM can be erased with ultraviolet light Static RAM (random access memory) may be rewritten unlimited number of times requires no refresh signal Dynamic RAM must be refreshed constantly cheaper than static RAM Copyright 1999-2001, Kip R. Irvine. All rights reserved.
Logical and Physical Addresses To specify the location of a memory byte we can use either a logical address or a physical address 24 Physical address: specify its absolute location. This is the number that goes onto the address bus For a bus of n lines, physical addresses go from 0 to 2^{n} - 1 Logical address = base:offset base = location of a block of memory (ex: segment) containing the referenced memory byte offset (displacement) = location of the referenced memory byte relative to its base
Intel s x86 Addresses in Real Mode 20 bits are used for physical addresses from 00000h to FFFFFh Logical address = [segment:offset] Segment = block of memory containing at most 2^{16} bytes located at a physical address which is a multiple of 10h (16d) Ex: the segment 08F1h starts at physical address 08F10h Offset = displacement of the referenced byte relative to its base segment 25
Real Mode Memory Architecture Only 1MB of memory is addressable with the 20 bits used for physical addresses RAM: from 0 to BFFFFh ROM: from C0000h to FFFFFh The memory above 1MB (extended memory) is addressable only in protected mode In this course we focus on real mode DOS is the dominant real-mode OS 26
Real Mode Memory Architecture (cont.) The 1st KB of memory (from 0 to 3FFh) contains the interrupt vector table each entry of this table contains the segment:offset address of an interrupt handler this is the routine invoked when an interrupt has occurred (more later) the interrupt handler is normally located in the ROM BIOS The ROM BIOS (from F0000h to FFFFFh) contains low-level I/O routines and configuration/diagnostic software 27
Real Mode Memory Architecture (cont.) The BIOS data area is located (at 00400h) just above the interrupt vector table contains serial and parallel port addresses, time and date, keyboard buffer pointers (for more see table 1) Next comes more BIOS routines (loaded from io.sys) to manage this data After comes various parts of DOS Addresses from A0000h to BFFFFh are located on the video adapter (VRAM) The rest (< 640 KB) is for user programs 28
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