US 20060136688Al (19) United States (12) Patent Application Publication (10) Pub. No.: US 2006/0136688 A1 Pang et al. (43) Pub. Date: Jun. 22, 2006 (54) REDUNDANT SAS STORAGE VIRTUALIZATION SUBSYSTEM AND SYSTEM USING THE SAME, AND METHOD THEREFOR (76) Inventors: Ching-Te Pang, Yonghe City (TW); Michael Gordon Schnapp, Banqiao City (TW); Shiann-Wen Sue, Banqiao City (TW); Cheng-Yu Lee, Chung-Ho City (TW) Correspondence Address: ROSENBERG, KLEIN & LEE 3458 ELLICOTT CENTER DRIVE-SUITE 101 ELLICOTT CITY, MD 21043 (US) (21) Appl. No.: 11/246,268 (22) Filed: Oct. 11, 2005 Related US. Application Data (60) Provisional application No. 60/ 593,212,?led on Dec. 21, 2004. Publication Classi?cation (51) Int. Cl. G06F 12/00 (2006.01) (52) Us. or...... 711/162; 711/112 (57) ABSTRACT A redundant external storage virtualization computer sys tem. The redundant storage virtualization computer system includes a host entity for issuing an 10 request, a redundant external SAS storage virtualization controller pair coupled to the host entity for performing an 10 operation in response to the IO request issued by the host entity, and a plurality of physical storage devices for providing storage to the com puter system. Each of the physical storage devices is coupled to the redundant storage virtualization controller pair through a SAS interconnect. The redundant storage virtual ization controller pair includes a?rst and a second SAS storage virtualization controller both coupled to the host entity. In the redundant SAS storage virtualization controller pair, When the second storage virtualization controller is not on line, the?rst storage virtualization controller Will take over the functionality originally performed by the second storage virtualization controller. I0 Request to be issued Agent SVC issues and executes IO Request YES Does SVC possess access ownership of the PSD to be accessed? Any data transferred from PSD to agent SVC as part of IO Request? NO Send IO request information to alternate SVC for it to execute as agent Transfer data from agent SVC to Request-initiating SVC 0 Nothing Snecial to do Transfer any data to be transferred to PSD from request-initiating SVC (access requester) to agent SVC (access owner) 7 Transfer IO Request Execution Completion status information to request-initiating SVC
Patent Application Publication Jun. 22, 2006 Sheet 1 0f 35 US 2006/0136688 A1 HOST SVS 20 SVC 200 SVC 200 DASD ARRAY 00 DASD 420 (SAS DASD 420A) DASD 420 (SAS DASD 420A) DASD 420 (SAS DASD 420A) DASD 420 (SATA DASD 420$) DASD 420 (SATA DASD 420s) _ DASD 420 (SATA DASD 4208) FIG. 1
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Patent Application Publication Jun. 22, 2006 Sheet 6 0f 35 US 2006/0136688 A1 CPU Chipset/Parity Engine 244A IM Parity A E I 22511 : to Host-side IO Device Interconnect = PCI-X Controller 220 7 Interface < : > Memory 930 <,:> Interface = to 920 memory 280 PCI-X a Interface < I: > 932 to SAS IO Device Arbiter ; Interconnect 982 Controller 300 X-BUS Interface \':> 940 to ROM 246, NVRAM 248, DMA ' EMS 360, etc. 980 UARTl ~ 986 <I:> UART2 to COM 1, COM 2. CPU I] ; Internal Interface 2, Registers 910 984 IL BUS 990 FIG. 4 to CPU 242
Patent Application Publication Jun. 22, 2006 Sheet 7 of 35 US 2006/0136688 A1 to Central Processing Circuit 240 to Central Processing Circuit 240 SAS 10 Device Interconnect Controller 300 Controller 3 l 0 PCI-X to SAS Controller 3 l O to DASD ARRAY 400/ Processing SVC 800 Circuit 240 to Central to D ASD Processing ARRAY Circuit 400/ SVC 800 240 SAS IO Device Interconnect Controller 300 to Central PCI-X to SAS Controller 310 PCI-X to SAS Controller 310 Circuit 340 to DASD 400/ SVC 800 SVC 200 side SVC 200 slde SAS IO Device Interconnect Controller 300 IP IDA or 0.1 CMGZ CW6»). mwm4 SUO 0 IS. CSH3 vlmaul MAUI. C P S100 Slol0 w m CSH3 0 B a C m k3 mm E a.h3 mewm g WC.mh ma S 4V Ammo D 0 D FIG. 5C SVC 200 side
Patent Application Publication Jun. 22, 2006 Sheet 8 0f 35 US 2006/0136688 A1 PCI-X to SAS Controller 310 PCI-X to SAS Interface 312 to Central _ 31> SAS Port 600 > Processing Con?guratlon (a c 't 240 316 cm C3 SAS Port 600 < > Bus Interface. O 318. to DASD Array 400/ ' svc 800 <, ;; SAS Port 600 > PI G. 6A PCI-X to SAS Controller 310 PCI-X to SAS Interface 312 to Central, Q: SAS Port 600 <,L_:'> Processing con?3glu6ratlon Expanding C' 't 240 ' ' ircul <- SAS Port 600 C C1rcu1t340 > Bus Interface < 318 0 0 to DASD 0 Array 400/ SVC 800 ; SAS Port 600 <;:> - SAS PI G. 6B
Patent Application Publication Jun. 22, 2006 Sheet 9 0f 35 US 2006/0136688 Al O D PCI-X to SAS Controller 310 PCI-X IO SAS Interface 312 to Central _ SAS Port 600 :1) SAS Processing con?3glu6ratlon Expanding C- 't 240 lrcul _ SAS Port 600 21> ' C1rcu1t340 < _ Bus Interface 31s 0 <::> 0 t0 DASD. Array 400/ T SAS P011 600 9 SVC 800 PI G. 6C SAS PO11 600 Transport Layer 690 I I TO PCI-X i.. to SAS SAS Port Layer 700. Interface I v 3 l 2 <:> I SAS Link Layer 710 I,_ I I I 0. SAS PHY Layer 720 I _. I I I ' o I SAS Physical Layer 73o ' L to DASD I i) 420... PI G. 6D
Patent Application Publication Jun. 22, 2006 Sheet 10 0f 35 US 2006/0136688 A1 SAS Expander 315 Expander Connection Phy 0 Phy 0 Phy O Management Function Expander Management SMP PI G. 6E PCI-X to SAS Controller 310 PCI-X t0 SAS Interface 312 m to Central _ t, SAS P011 600 _> Processing Con?guration.. Circuit 240 316.. : Bus Interface. ' 318 (52> SAS P rt 600 O <,. #6 DASD Array 400/ SVC 800. Expanding. 0 Circuit 340.. 0 Ci) SAS Port 600 <::> PI G. 6F
Patent Application Publication Jun. 22, 2006 Sheet 11 0f 35 US 2006/0136688 A1 PCl-X t0 SAS Controller 310 PCI-X to SAS Interface 312 to Central cza SAS Port 600 > Processing Con?guration o 0 Circuit 240 316 0 o :> Bus Interface.. 318 <:::i> SAS P rt 600 ~ td)dasd Array 400/ C331) SAS Port 600 (1:1) SAS SVC 800. Expanding. 0 Circuit 340 Q O O <;::;> SAS Port 600 <;::{> <):,'> PI G. 6G SVCs / A \ To SVC 200 To SVC 800 To SVC 200 To SVC 800 I _V SATA MUX 460 -? SATA Canister SAS HDD 420A 450 SATA HDD 420s 0 0 0 \ Y / H G. 10 DASD array 400
Patent Application Publication Jun. 22, 2006 Sheet 12 of 35 US 2006/0136688 A1 Central Processing To Controller To Memory Circuit 240A {} 220 {T 280 i} U CPU Chipset/Parity Engine 244A To Controller 300 LCD EMS CPU ROM NVRAM 350 360 Q Q Q 242 246 248 F1 G. 7A Central Processing To Controller To Memory Circuit 240B f} 220 f} 280 U U To Controller 300 CPU Chipset 244B 11 <3 11 11 11 > Parity LCD EMS Engine CPU ROM NVRAM 350 360 0 0 0 260 242 246 248 PI G. 7B
Patent Application Publication Jun. 22, 2006 Sheet 14 of 35 US 2006/0136688 A1 SAS 10 Device Interconnect Controller 300 DASD ARRAY 400 PCI-X to SAS Controller 310 SAS Port 600 Port 1 DASD 420A SAS Port 600 P0" 2 SAS Port 600 PO" 1 DASD 420A SAS P011 600 Port 2 SAS Port 600 DASD > 4208 SAS Port 600 DASD < > 4203 PI G. 8A
Patent Application Publication Jun. 22, 2006 Sheet 15 0f 35 US 2006/0136688 A1 to SAS 10 Device Intercgnngct DASD ARRAY 400 Controller 300 Expanding \ Circuit 340 / P <il?/ (p X Q) Port 1 DASD 420A > Port 2 <: il> PO" 1 DASD 420A :> Port 2 < > DASD 420s MUX O Q Q (P), (Q) <[ > DASD 420s MUX O O I to svc 800 P1 G. 8B
Patent Application Publication Jun. 22, 2006 Sheet 16 0f 35 US 2006/0136688 A1 mun Backplane 320 DASD ARRAY 400 Switching Circuit 340 P0" 1 DASD 420A Port 2 DASD 420S MUX to SAS IO Device Interconnect Port 2 Controlle<rf00 PO" 1 DASD 420A A VV MUX DASD 420$ VVVV to SVC 800 FIG. 8C
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