VXS-610 Dual FPGA and PowerPC VXS Multiprocessor Two Xilinx Virtex -5 FPGAs for high performance processing On-board PowerPC CPU for standalone operation, communications management and user applications Two PMC/XMC sites for maximum I/O density and flexibility Serial RapidIO Interconnect Development Kits for Linux and VxWorks, including comprehensive FPGA IP core library Dual FPGA and PowerPC VXS Multiprocessor Overview The VXS-610 PowerPC and Dual FPGA multiprocessor is designed to meet modern data processing needs, as well as high performance computing applications. A Xilinx Virtex-5 FPGA enables high performance DSP applications to be implemented with low levels of power consumption. The FPGA processing is supplemented by an onboard PowerPC for standalone operation, communications management and user applications. VXS-610 maximizes sensor I/O density with two PMC/XMC sites. These enable multi-channel signal digitization schemes to be implemented on-card, or pre-digitized signals to be brought on-board using digital I/O. Network I/O such as Ethernet or 1553 can also be implemented using mezzanine cards. Features Single Slot VXS Multiprocessor PowerPC node with Freescale MPC8548E processor 512MB DDR2-SDRAM for PowerPC 2 FPGA nodes with Xilinx Virtex -5 SX95T or LX155T FPGAs 2 banks 256MB DDR2-SDRAM per FPGA 1 bank 8MB DDR-II-SRAM per FPGA Serial RapidIO switch for P0 interconnect Front panel and backplane Ethernet and RS232 ports 2x PMC/XMC sites Built-in Test capability Development Kits available for Linux and VxWorks FPGA Development Kit provides IP cores for all FPGA peripherals As part of the scalable REVX series of products from Nallatech, the VXS-610 is complemented by further PMC/XMC Air-cooled and conduction-cooled versions mezzanines, VXS processing engines, and application 10011100110011010101000010011000000110111011010110011001010110110010101010110001001100111001100110101010000100110000001101110110101100110010101101100101010101 development tools. 11100110011010101000010011000000110111011010110011001010110110010101010110001001100111001100110101010000100110000001101110110101100110010101101100101010101100 00110011010101000010011000000110111011010110011001010110110010101010110001001100111001100110101010000100110000001101110110101100110010101101100101010101100010 1010101101100101010101100010011001110011001101010100001001100000011011101101011001100101011011001010101011000100110011100110011010101000010011000000110111011010110011001010 1101100101010101100010011001110011001101010100001001100000011011101101011001100101011011001010101011000100110011100110011010101000010011000000110111011010110011001010110110 0101010101100010011001110011001101010100001001100000011011101101011001100101011011001010101011000100110011100110011010101000010011000000110111011010110011001010110110010101 The Leader in FPGA 0101100010011001110011001101010100001001100000011011101101011001100101011011001010101011000100110011100110011010101000010011000000110111011010110011001010110110010101010110 Accelerated Computing 0010011001110011001101010100001001100000011011101101011001100101011011001010101011000100110011100110011010101000010011000000110111011010110011001010110110010101010110001001 1001110011001101010100001001100000011011101101011001100101011011001010101011000100110011100110011010101000010011000000110111011010110011001010110110010101010110001001100111 0011001101010100001001100000011011101101011001100101011011001010101011000100110011100110011010101000010011000000110111011010110011001010110110010101010110001001100111001100 1101010100001001100000011011101101011001100101011011001010101011000100110011100110011010101000010011000000110111011010110011001011011001010101011000100110011100110011010101
Functional Diagram Figure 1: VXS-610 Functional Diagram
Specification PowerPC Node Device» Freescale MPC8548E (single e500 core)» Operating Frequency: 1 GHz Memory» 512MB DDR2 SDRAM» 64MB Flash Connectivity» PCI-X/PCI-64/PCI-32 Interface» x4 SRIO interface to FPGA» Local bus interface to FPGAs» Backplane and front-panel Ethernet ports» Backplane and front-panel RS232 ports Host Controller» PowerPC local bus bridge» SelectMAP FPGA configuration» Temperature sensor interfacing» Clock control and reset sequencing» Boot flash controller» Power supply monitoring» BIOS control» Interrupt handling» Built-in host controller firmware updater FPGA Nodes FPGA» 2 FPGA Nodes per card» Xilinx Virtex-5 SX95T-2 or LX155T FPGA» Contact a Nallatech sales representative for Virtex-5 FXT FPGA availability» FPGA boot via host controller SDRAM» DDR2 SDRAM» 2 banks per FPGA» 256 MB per bank» 32 bit data bus (each bank)» 200MHz max operating frequency» 400Mb/s max data rate (DDR) FPGA Node (continued) SRAM Bank» DDR-II SRAM» 1 bank per FPGA» 8 MB per bank» 32 bit data bus» 200MHz max operating frequency» 400Mb/s max data rate (DDR) Connectivity Serial RapidIO» x4 Serial RapidIO links» Interconnects FPGAs, PowerPC and P0 VXS connector» Integrated into MPC8548E, Tundra Serial RapidIO switch and FPGAs (via SRIO endpoint IP core)» Speed: 1.25/2.5/3.125 Gb/s* High Speed Serial» Interconnects FPGAs, PMC/XMC sites» Speed: 1.25/2.5/3.125 Gb/s*» Aurora protocol by default VMEbus» Interconnects PowerPC to backplane VME bus via Tundra TSi148 VME bridge» VME64, 2eSST, master/slave mode PCI/PCI-X bus» Interconnects PowerPC to PMC/XMC sites and TSi148 VME bridge» 64-bit PCI 2.2 bus controller (up to 66 MHz, 3.3V I/O)» 64-bit PCI-X bus controller (up to 133 MHz, 3.3V I/O)» 32-bit PCI support Power PC Local Bus» Interconnects PowerPC to Host Controller and Flash» Bridged to FPGA node via Host Controller Ethernet» Interconnects PowerPC to backplane and front panel» Integrated into MPC8548E» Front panel (RJ45 copper): 1 channel 10BASE-T, 100BASE-TX, 1000BASE-T» Backplane P2 (copper): 1 channel 10BASE-T, 100BASE-TX, 1000BASE-T (requires PHY chip on rear transition module) RS232» Interconnects PowerPC to backplane and front panel» Integrated into MPC8548E» Front panel: single channel RS232 (RJ11)» Backplane P2: single channel RS232
Specification Connectivity (continued) Backplane GPIO» Each PMC/XMC slot has 28 lines of GPIO between Pn4 connector and VXS backplane P2 (single ended/differential)» 4 bit backplane GPIO bus to FPGA (single ended) Expansion PMC/XMC Sites» 2x PMC/XMC sites supporting Pn1, Pn2, Pn3, Pn4 and Pn5 connectors» PCI-X 133 PCI bus to PowerPC» 8x GTP links between XMC sites» GTP links PCIe, SRIO capable (additional IP cores required)» Each PMC/XMC slot has 28 lines of GPIO connectivity between Pn4 connector and VXS backplane P2 connector» XMC links use Aurora by default Development Kit» The VXS-621 Development Kit includes Software Development Kit, FPGA Development Kit, Hardware Documentation and Application Notes required to build applications for the VXS-610.» VXS-610 Development Kits are available for Linux or VxWorks 6.6. Software Development Kits (continued) VXS-610 VxWorks 6.6 SDK» Supports VxWorks 6.6» Includes VxWorks drivers and API to interface to and control card» Examples and documentation provided» Each Software Development Kit is included with the appropriate version of the VXS-610 Development Kit FPGA Development Kit» The VXS-610 FPGA Development Kit (FDK) provides an optimized Library of FPGA IP cores for the VXS-620» Cores Provided:» DDR2 SDRAM» DDR-II SRAM» Host controller local bus interface core» Clocking core» GTP link Aurora Cores» SRIO interface cores» Cores are provided in pre-synthesized netlist format, and as VHDL source code» Examples and full documentation provided» The FPGA Development Kit is included with the appropriate version of the VXS-610 Development Kit Figure 2: VXS-610 Development Kit Software Development Kits VXS-610 Linux SDK» Compiled for Linux kernel 2.6.20» Includes Linux OS, device drivers and API to interface to and control card» Driver source code, examples and documentation provided» Examples and documentation provided Figure 3: VXS-610 FDK
Specification Cable Pack A cable pack is available for VXS-610. This provides connectivity to the card from other systems for development and debug proposes. A minimum of one cable pack is required to develop applications using the VXS-610. REVX Cable Pack A VXS» VXS JTAG & RS232 adaptor module breaks out JTAG and RS232 links to standard connectors from custom connectors on VXS card» VXS JTAG & RS232 adaptor module cables» RJ45 Ethernet cable» RJ11 RS232 cable and RJ11/DE9 adaptor Electrical» VXS-610 requires 5V to be supplied from the VME/VXS backplane» Hosted PMC cards may require 3.3V, +/-12V supplies in addition» Power consumption is application dependant. Power estimation tools from Xilinx can be used to estimate the power consumption of FPGA applications.» Contact a Nallatech sales representative for further information on power consumption Ruggedization Levels Level L1 L2 L3 L4 Description Air Cooled Commercial Air Cooled Extended Temp Air Cooled Rugged Conduction Cooled Rugged Operating Temp C Storage Temp C 0 to +55-20 to +65-40 to +70-40 to +70-40 to +85-40 to +85-50 to +100-50 to +100 Vibration Class 0.04g²/Hz, 5-100Hz 0.04g²/Hz, 5-100Hz 0.04g²/Hz, 100-1000Hz 0.1g²/Hz, 100-1000Hz Operating Shock 20g, 11mS 20g, 11mS 20g, 11mS 40g, 11mS Humidity Conformal Coat No Optional Optional Optional
Ordering Order Codes & Deliverables VXS-610-SX95T-L1: VXS-610-LX155T-L1: VXS-610-LINUX: VXS-610 with SX95T-2 FPGA; Nallatech L1 Ruggedization Level; forced air cooled heat frame VXS-610 with SX95T-2 FPGA; Nallatech L1 Ruggedization Level; forced air cooled heat frame VXS-610 Development Kit for Linux; Project License Delivered via web download or DVD VXS-610-VXWORKS: VXS-610 Development Kit for VxWorks 6.6; Project License Delivered via web download or DVD RCP-A-VXS: REVX Cable Pack A - VXS: 1x RJ45 Ethernet cable; 1x RJ11 RS232 cable; 1x RJ11/DE9 adaptor; 1x VXS JTAG & RS232 adaptor module and 2x JTAG adaptor cables Contact a Nallatech sales representative for availability of alternative FPGA and ruggedization options. Warranty This product has a 1 year hardware warranty (return to manufacturer). Warranty extensions are available. Support This product includes 30 days technical support. Technical support can optionally be extended to 1 year.