ECE 3060 VLSI and Advanced Digital Design

Similar documents
Simplification of Boolean Functions

1. How many white tiles will be in Design 5 of the pattern? Explain your reasoning.

ECE260B CSE241A Winter Logic Synthesis

1/28/2013. Synthesis. The Y-diagram Revisited. Structural Behavioral. More abstract designs Physical. CAD for VLSI 2

CSE241 VLSI Digital Circuits UC San Diego

Chapter 2 Combinational Logic Circuits

Synthesis 1. 1 Figures in this chapter taken from S. H. Gerez, Algorithms for VLSI Design Automation, Wiley, Typeset by FoilTEX 1

ECE260B CSE241A Winter Logic Synthesis

ELCT201: DIGITAL LOGIC DESIGN

ECE 3060 VLSI and Advanced Digital Design

IT 201 Digital System Design Module II Notes

Programmable Logic Devices

Gate Level Minimization Map Method

ELCT201: DIGITAL LOGIC DESIGN

Giovanni De Micheli. Integrated Systems Centre EPF Lausanne

EE292: Fundamentals of ECE

Building Roads. Page 2. I = {;, a, b, c, d, e, ab, ac, ad, ae, bc, bd, be, cd, ce, de, abd, abe, acd, ace, bcd, bce, bde}

SIS Logic Synthesis System

CHAPTER-2 STRUCTURE OF BOOLEAN FUNCTION USING GATES, K-Map and Quine-McCluskey

Chapter 2 Combinational

Advanced Digital Logic Design EECS 303

Boolean Analysis of Logic Circuits

IMPLEMENTATION DESIGN FLOW

Combinational Logic Circuits

ECE380 Digital Logic

Specifying logic functions

1. Fill in the entries in the truth table below to specify the logic function described by the expression, AB AC A B C Z

LSN 4 Boolean Algebra & Logic Simplification. ECT 224 Digital Computer Fundamentals. Department of Engineering Technology

Retiming. Adapted from: Synthesis and Optimization of Digital Circuits, G. De Micheli Stanford. Outline. Structural optimization methods. Retiming.

DKT 122/3 DIGITAL SYSTEM 1

EEE130 Digital Electronics I Lecture #4_1

Chapter 3. Gate-Level Minimization. Outlines

Switching Circuits & Logic Design

DIGITAL ARITHMETIC: OPERATIONS AND CIRCUITS

2.1 Binary Logic and Gates

ENGIN 112. Intro to Electrical and Computer Engineering

Chapter 2 Combinational Logic Circuits

Combinational Circuits

COE 561 Digital System Design & Synthesis Introduction

Two-Level Logic Optimization ( Introduction to Computer-Aided Design) School of EECS Seoul National University

CSCI 220: Computer Architecture I Instructor: Pranava K. Jha. Simplification of Boolean Functions using a Karnaugh Map

A B AB CD Objectives:

Combinational Logic Circuits

VLSI Test Technology and Reliability (ET4076)

A Boolean Paradigm in Multi-Valued Logic Synthesis

DATA MINING II - 1DL460

Division. Reverse Box Method

4 KARNAUGH MAP MINIMIZATION

Design of Framework for Logic Synthesis Engine

Alignment to the Texas Essential Knowledge and Skills Standards

Digital Logic Lecture 7 Gate Level Minimization

CS8803: Advanced Digital Design for Embedded Hardware

Mathematics Scope & Sequence Algebra I

Combinatorial Algorithms. Unate Covering Binate Covering Graph Coloring Maximum Clique

1. Divide by using long division. (8x 3 + 6x 2 + 7) (x + 2)

Experiment 4 Boolean Functions Implementation

SYNERGY INSTITUTE OF ENGINEERING & TECHNOLOGY,DHENKANAL LECTURE NOTES ON DIGITAL ELECTRONICS CIRCUIT(SUBJECT CODE:PCEC4202)

Introduction. The Quine-McCluskey Method Handout 5 January 24, CSEE E6861y Prof. Steven Nowick

Apriori Algorithm. 1 Bread, Milk 2 Bread, Diaper, Beer, Eggs 3 Milk, Diaper, Beer, Coke 4 Bread, Milk, Diaper, Beer 5 Bread, Milk, Diaper, Coke

Literal Cost F = BD + A B C + A C D F = BD + A B C + A BD + AB C F = (A + B)(A + D)(B + C + D )( B + C + D) L = 10

Lecture (04) Boolean Algebra and Logic Gates

Lecture (04) Boolean Algebra and Logic Gates By: Dr. Ahmed ElShafee

Overview. CSE372 Digital Systems Organization and Design Lab. Hardware CAD. Two Types of Chips

Homework 3 Handout 19 February 18, 2016

Chapter 7: Frequent Itemsets and Association Rules

HDL. Operations and dependencies. FSMs Logic functions HDL. Interconnected logic blocks HDL BEHAVIORAL VIEW LOGIC LEVEL ARCHITECTURAL LEVEL

Unit 4: Formal Verification

Bawar Abid Abdalla. Assistant Lecturer Software Engineering Department Koya University

SIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN

VLSI CAD Flow: Logic Synthesis, Placement and Routing Lecture 5. Guest Lecture by Srini Devadas

Gate Level Minimization

LOGIC SYNTHESIS AND VERIFICATION ALGORITHMS. Gary D. Hachtel University of Colorado. Fabio Somenzi University of Colorado.

Design and Synthesis for Test

Summary. Boolean Addition

VLSI Test Technology and Reliability (ET4076)

9/10/2016. The Dual Form Swaps 0/1 and AND/OR. ECE 120: Introduction to Computing. Every Boolean Expression Has a Dual Form

ENGINEERS ACADEMY. 7. Given Boolean theorem. (a) A B A C B C A B A C. (b) AB AC BC AB BC. (c) AB AC BC A B A C B C.

Design of the Power Standard Document

Combinational Logic Circuits Part III -Theoretical Foundations

ESE535: Electronic Design Automation. Today. EDA Use. Problem PLA. Programmable Logic Arrays (PLAs) Two-Level Logic Optimization

ABC basics (compilation from different articles)

1. Answer: x or x. Explanation Set up the two equations, then solve each equation. x. Check

COPYRIGHTED MATERIAL INDEX

Boolean Function Simplification

Mining Frequent Patterns without Candidate Generation

Read-Once Functions (Revisited) and the Readability Number of a Boolean Function. Martin Charles Golumbic

Bawar Abid Abdalla. Assistant Lecturer Software Engineering Department Koya University

How to find a minimum spanning tree

Software Implementation of Break-Up Algorithm for Logic Minimization

CMPE223/CMSE222 Digital Logic

Chapter 8. 8 Minimization Techniques. 8.1 Introduction. 8.2 Single-Output Minimization Design Constraints

Lecture 25 Notes Spanning Trees

Name Date Class. Vertical angles are opposite angles formed by the intersection of two lines. Vertical angles are congruent.

Experiment 3: Logic Simplification

Gate-Level Minimization

ICS 252 Introduction to Computer Design

Architectural-Level Synthesis. Giovanni De Micheli Integrated Systems Centre EPF Lausanne

Chapter 2 Part 5 Combinational Logic Circuits

state encoding with fewer bits has fewer equations to implement state encoding with more bits (e.g., one-hot) has simpler equations

University of Technology

Transcription:

ECE 3060 VLSI and Advanced Digital Design Lecture 15 Multiple-Level Logic Minimization

Outline Multi-level circuit representations Minimization methods goals: area, delay, power algorithms: algebraic, boolean rule-based methods Examples of transformations Boolean and algebraic models Disclaimer: lecture notes based on originals by Giovanni De Micheli

Motivation Multiple level networks Semi-custom libraries Advantages of gates versus macros (PLA) 8more flexible 8better performance might want to minimize certain paths Applicable to a variety of designs

Circuit modeling Logic network interconnection of logic functions hybrid structural/behavioral model Bound (mapped) gates interconnection of logic gates structural model

Example of a bound network

Logic equations of example 8p = ce + de 8q = a + b 8r = p + a 8s = r + b 8t = ac + ad + bc + bd + e 8u = q c + qc + qc 8v = a d + bd + c d + ae 8w = v 8x = s 8y = t 8z = u

Example of network

Example circuit output function w x y z a d + bd + c d + ae a' + b' + ce + de ac + ad + bc + bd + e a + b + c

Network optimization Minimize area (power) estimate subject to delay constraints Minimize maximum delay subject to area (power) constraints Maximize testability Minimize power

Area: number of literals Estimation 8in MOS, # literals = # poly strips number of functions/gates Delay: number of stages 8most often used metric refined gate delay models sensitizable paths 8paths for which there are conditions under which a signal propagates through the path

Problem analysis Multiple-level optimization is hard Exact methods: exponential complexity impractical 8die on reasonably sized networks Approximate (heuristic) methods: algorithms which explore part of exact soln. space rule-based methods 8replacement of subcircuits by other subcircuits

Strategies for minimization Improve circuits step by step circuit transformations Preserve network behavior Methods differ in types of transformations selection and order of transformations

Example elimination Eliminate one function from the network Perform variable substitution Example s = r + b'; r = p + a' => s = p + a' + b'

Example: elimination

Example decomposition Break one function into smaller ones Introduce new vertices in the network Example: v = a'd + bd + c'd + ae' => j = a' + b + c'; v = jd + ae'

Example: decomposition

Example extraction Find a common sub-expression of two (or more) expressions Extract sub-expression as new function Introduce new vertex in the network Example: p = ce + de; t = ac + ad + bc + bd + e p = (c + d)e; t = (c + d)(a + b) + e => k = c + d; p = ke; t = ka + kb + e

Example: extraction

Example simplification Simplify a local function Example: u = q'c + qc' + qc => u = q + c

Example: simplification

Example subsitution Simplify a local function by using an additional input that was not previously in the function s support set Example: t = ka + kb + e => t = kq + e (because q = a + b)

Example: substitution

Example outcome sequence of transformations 8j = a' + b + c' 8k = c + d 8q = a + b 8s = ke + a' + b' 8t = kq + e 8u = q + c 8v = jd + ae'

Minimization approaches Algorithmic approach: define an algorithm for each transformation type algorithm is an operator on the network Rule-based approach rule-data base 8set of pattern pairs pattern replacement driven by rules

Algorithmic approach Each operator has well-defined properties heuristic methods still used weak optimality properties Sequence of operators defined by scripts based on experience

Example elimination algorithm Set a threshold k (usually 0) k corresponds to the maximum area (or power or delay) increase allowed Examine all expressions Eliminate expressions if the increase in literals does not exceed the threshold goal: reduce the number of logic expressions

Example elimination algorithm 8ELIMINATE (G(V,E), k) { 8 repeat { 8 v x = selected vertex with value < k ; 8 if (v x == empty vertex) return; 8 replace x by f x in the network; 8 } 8}

Example MIS/SIS rugged script sweep; eliminate -1 simplify -m nocomp eliminate -1 sweep; eliminate 5 simplfy -m nocomp resub -a fx resub -a; sweep eliminate -1; sweep full-simplify -m nocomp

Algebraic Division f quotient = f dividend / f divisor when f dividend = f divisor * f quotient + f remainder f divisor * f quotient!= 0 the literals of f divisor are disjoint from the literals of f quotient Note: if f remainder = 0, then f divisor is called a factor, and f divisor is said to factor f quotient

Definitions Cube-free expression cannot be factored by a cube (implicant) Kernel of an expression cube-free quotient of the expression divided by a cube (the cube used for division is called a cokernel) Kernel set K(f) of an expression set of kernels

Example f = ace + bce + de + g Divide f by a. Get ce. Not cube free. Divide f by b. Get ce. Not cube free Divided f by c. Get ae+be. Not cube free. Divide f by ce. Get a+b. Cube free. Kernel! Divide f by d. Get e. Not cube free. Divide f by e. Get ac+bc+d. Cube free. Kernel! Divide f by g. Get 1. Not cube free. Expression f is a kernel of itself because cube free. K(f) = {(a+b); (ac+bc+d); (ace+bce+de+g)}

Example y = ad + bd + cde + ge The literals are a, b, c, d, e, g Try all combinations of literals There exists a recursive function for calculating kernels very fast (we won't cover this recursive function)

Example: use kernel computation to implement extraction Steps: (1) calculate K(x), (2) calculate K(y), (3) calculate K(z), (4) if there are some kernels in common, perform extraction with largest kernel (largest # of cubes, break tie by choosing largest # of literals)

Boolean and algebraic methods Boolean methods exploit properties of logic functions use don't care conditions complex at times Algebraic methods view functions as polynomials exploit properties of polynomial algebra simpler, faster but weaker

Example Boolean substitution h = a + bcd + e; q = a + cd => h = a + bq + e (because a + bq + e = a + b(a + cd) + e = a + bcd + e) Algebraic substitution t = ka + kb + e => t = kq + e (because q = a + b)

Summary Multi-level logic synthesis is performed by step-wise transformations Algorithms are based on both the boolean and algebraic models Rule-based models