Intel Acceleration Stack for Intel Xeon CPU with FPGAs 1.0 Errata

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Intel Acceleration Stack for Intel Xeon CPU with FPGAs 1.0 Errata Updated for Intel Acceleration Stack for Intel Xeon CPU with FPGAs: 1.0 Production Subscribe Send Feedback Latest document on the web: PDF HTML

Contents Contents...3 Flash Fallback Does Not Meet PCIe Timeout... 4 Unsupported Transaction Layer Packet Types... 5 JTAG Timing Failures May Be Reported in the FPGA Interface Manager...6 fpgabist Tool Does Not Pass Hexadecimal Bus Numbers Properly...7 Possible Low dma_afu Bandwidth Due to memcpy Function... 8 regress.sh -r Option Does Not Work With dma_afu... 9 Intel Acceleration Stack for Intel Xeon CPU with FPGAs 1.0 Errata Revision History...10 2

Intel Acceleration Stack for Intel Xeon CPU with FPGAs 1.0 Errata This document provides information about errata affecting the Intel Acceleration Stack for Intel Xeon CPU with FPGAs. Issue Affected Versions Planned Fix Flash Fallback Does Not Meet PCIe Timeout on page 4 Unsupported Transaction Layer Packet Types on page 5 Acceleration Stack 1.0 Production Acceleration Stack 1.0 Production No Planned Fix No Planned Fix JTAG Timing Failures May Be Reported in the FPGA Interface Manager on page 6 fpgabist Tool Does Not Pass Hexadecimal Bus Numbers Properly on page 7 Acceleration Stack 1.0 Production Acceleration Stack 1.1 Acceleration Stack 1.0 Production Acceleration Stack 1.1 Possible Low dma_afu Bandwidth Due to memcpy Function on page 8 regress.sh -r Option Does Not Work With dma_afu on page 9 Acceleration Stack 1.0 Beta and Production Acceleration Stack 1.0 Production Acceleration Stack 1.1 No planned fix The table below can be used as a reference to identify the FPGA Interface Manager (FIM), Open Programmable Acceleration Engine (OPAE) and Intel Quartus Prime Pro Edition version that corresponds to your software stack release. Table 1. Intel Acceleration Stack 1.0 Reference Table Intel Acceleration Stack Version Boards FIM Version (PR Interface ID) OPAE Version Intel Quartus Prime Pro Edition 1.0 Production (1) Intel PAC with Intel Arria 10 GX FPGA ce489693-98f0-5f33-946d-560708 be108a 0.13.1 17.0.0 Related Information Intel Acceleration Stack for Intel Xeon CPU with FPGAs Release Notes Refer to the release notes for more information about known issues and enhancements for Intel Acceleration Stack 1.0 (1) The factory partition of the configuration flash contains the Acceleration Stack 1.0 Alpha version. When the image in the user partition cannot be loaded, a flash failover occurs and the factory image is loaded instead. After a flash failover occurs, the PR ID reads as d4a76277-07da-528d-b623-8b9301feaffe. Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2008 Registered

Flash Fallback Does Not Meet PCIe Timeout The host may hang or report a PCIe failure after a flash failover has occurred. This issue can be seen when the user image in flash is corrupted and the configuration subsystem loads the factory image into the FPGA. Follow the instructions in the "Updating Flash with FPGA Interface Manager (FIM) Image using Intel Quartus Prime Programmer" section in the Intel Acceleration Stack Quick Start Guide for Intel Programmable Acceleration Card with Intel Arria 10 GX FPGA. If the issue persists, contact your local field representative. Affects: Intel Acceleration Stack 1.0 Production : No planned fix Related Information Intel Acceleration Stack Quick Start Guide for Intel Programmable Acceleration Card with Intel Arria 10 GX FPGA 4

Unsupported Transaction Layer Packet Types The Acceleration Stack FPGA Interface Manager (FIM) does not support PCIe* Memory Read Lock, Configuration Read Type 1, and Configuration Write Type 1 transaction layer packets (TLPs). If the device receives a PCIe packet of this type, it does not respond with a Completion packet as expected. No workaround available. Affects: Intel Acceleration Stack 1.0 Production : No planned fix 5

JTAG Timing Failures May Be Reported in the FPGA Interface Manager The Intel Quartus Prime Pro Edition Timing Analyzer may report unconstrained JTAG I/O paths in the FIM. These unconstrained paths can be safely ignored because the JTAG I/O paths are not used in the FIM. Affects: Intel Acceleration Stack 1.0 Production : Planned fix in Intel Acceleration Stack 1.1 6

fpgabist Tool Does Not Pass Hexadecimal Bus Numbers Properly The Open Programmable Acceleration Engine (OPAE) fpgabist tool does not pass valid bus numbers if the PCIe bus number is any character above F. If any of these characters are included, you may encounter the following error message: Running mode: nlb_3 Attempting Partial Reconfiguration: invalid bus: d4 Failed to load gbs file: /home/lab/workspace/dcp/prc/hw/samples/ nlb_mode_3/bin/nlb_mode_3.gbs Please try a different gbs Change /usr/bin/bist_common.py line 83 from cmd = "{} -b {} -v {}".format('fpgaconf', bus_num, gbs_file) to cmd = "{} -b 0x{} -v {}".format('fpgaconf', bus_num, gbs_file) Affects: Intel Acceleration Stack 1.0 Production : Planned fix in Intel Acceleration Stack 1.1 7

Possible Low dma_afu Bandwidth Due to memcpy Function fpgabist may report lower bandwidth for the dma_afu but not the native loopback 3 (NLB3) due to the use of the memcpy function in the dma_afu driver. You can workaround this erratum by removing memcpy from the dma_afu driver code and adding code to accept buffers from the user that have been pre-pinned. For use with OpenCL*, there is no current workaround. Affects: Intel Acceleration Stack 1.0 Beta and Production : Planned fix in Intel Acceleration Stack 1.1 8

regress.sh -r Option Does Not Work With dma_afu When using the -r option with regress.sh, the script does not work with the dma_afu example. Using the -r option results in a fatal gcc error. Do not use the -r option when running the regress.sh script. Running the script without the -r option places the output simulation in $OPAE_LOC/ase/rtl_sim instead of a user-specified directory. Affects: Intel Acceleration Stack 1.0 Production : No planned fix 9

Intel Acceleration Stack for Intel Xeon CPU with FPGAs 1.0 Errata Revision History Date Intel Acceleration Stack Version Changes 2018.06.22 1.0 Production (compatible with Intel Quartus Prime Pro Edition 17.0.0) 2018.04.11 1.0 Production (compatible with Intel Quartus Prime Pro Edition 17.0.0) Updated the path of the bist_common.py file in the fpgabist Tool Does Not Pass Hexadecimal Bus Numbers Properly erratum. Initial release. 10

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