Solving the System-Level Design Riddle. October 2014

Similar documents
On-chip Networks Enable the Dark Silicon Advantage. Drew Wingard CTO & Co-founder Sonics, Inc.

Embedded Hardware and Software

Hardware Software Bring-Up Solutions for ARM v7/v8-based Designs. August 2015

Introducing the FPGA-Based Prototyping Methodology Manual (FPMM) Best Practices in Design-for-Prototyping

Mapping Multi-Million Gate SoCs on FPGAs: Industrial Methodology and Experience

Does FPGA-based prototyping really have to be this difficult?

Place Your Logo Here. K. Charles Janac

EEM870 Embedded System and Experiment Lecture 4: SoC Design Flow and Tools

Software Driven Verification at SoC Level. Perspec System Verifier Overview

System-on-Chip Architecture for Mobile Applications. Sabyasachi Dey

The Use Of Virtual Platforms In MP-SoC Design. Eshel Haritan, VP Engineering CoWare Inc. MPSoC 2006

Overcoming the Memory System Challenge in Dataflow Processing. Darren Jones, Wave Computing Drew Wingard, Sonics

Evolution of UPF: Getting Better All the Time

HES-7 ASIC Prototyping

Embedded HW/SW Co-Development

SoC Communication Complexity Problem

100M Gate Designs in FPGAs

Using Virtual Platforms To Improve Software Verification and Validation Efficiency

Topic 01. Software Engineering, Web Engineering, agile methodologies.

The Embedded System Design Process. Wolf Text - Chapter 1.3

Activities Common to Software Projects. Software Life Cycle. Activities Common to Software Projects. Activities Common to Software Projects

CONSIDERATIONS FOR THE DESIGN OF A REUSABLE SOC HARDWARE/SOFTWARE

SoC Silicon and Software Design Cost Analysis: Costs for Higher Complexity Continue to Rise

FPGA system development What you need to think about. Frédéric Leens, CEO

IMPROVES. Initial Investment is Low Compared to SoC Performance and Cost Benefits

Ncore Cache Coherent Interconnect

The Evolution of Mobile

Optimizing ARM SoC s with Carbon Performance Analysis Kits. ARM Technical Symposia, Fall 2014 Andy Ladd

Codesign Framework. Parts of this lecture are borrowed from lectures of Johan Lilius of TUCS and ASV/LL of UC Berkeley available in their web.

S2C K7 Prodigy Logic Module Series

The Internet of Trust and a New Frontier For Exploration

Verification of Clock Domain Crossing Jitter and Metastability Tolerance using Emulation

Virtual Hardware ECU How to Significantly Increase Your Testing Throughput!

Boost FPGA Prototype Productivity by 10x

SiFive Freedom SoCs: Industry s First Open-Source RISC-V Chips

Technology for Innovators TM TI WIRELESS TECHNOLOGY DELIVERING ALL THE PROMISE OF 3G

Early Software Development Through Emulation for a Complex SoC

Test and Verification Solutions. ARM Based SOC Design and Verification

SOFTWARE DRIVES HARDWARE, LESSONS LEARNED AND FUTURE DIRECTIONS

Benefits of Network on Chip Fabrics

Park Sung Chul. AE MentorGraphics Korea

Appendix SystemC Product Briefs. All product claims contained within are provided by the respective supplying company.

Dr. Ajoy Bose. SoC Realization Building a Bridge to New Markets and Renewed Growth. Chairman, President & CEO Atrenta Inc.

Software Engineering Lifecycles. Controlling Complexity

SoC Overview. Multicore Applications Team

Chapter 1. Software and Software Engineering. What is this course about?

3D Graphics in Future Mobile Devices. Steve Steele, ARM

Hardware Software Codesign of Embedded Systems

Virtual PLATFORMS for complex IP within system context

Efficient HW/SW Co-Design & Validation of Complex Emerging Systems

Heterogeneous, Distributed and Scalable Cache-Coherent Interconnect

THE NEW COLLABORATIVE WORKFORCE. Enterprise Communications, Advanced.

Administrivia. Added 20 more so far. Software Process. Only one TA so far. CS169 Lecture 2. Start thinking about project proposal

EEL 5722C Field-Programmable Gate Array Design

Veloce2 the Enterprise Verification Platform. Simon Chen Emulation Business Development Director Mentor Graphics

What are Embedded Systems? Lecture 1 Introduction to Embedded Systems & Software

Yafit Snir Arindam Guha Cadence Design Systems, Inc. Accelerating System level Verification of SOC Designs with MIPI Interfaces

Figure 1: Target environment includes peripherals.

Kevin Donnelly, General Manager, Memory and Interface Division

The Challenges of System Design. Raising Performance and Reducing Power Consumption

Power Aware Architecture Design for Multicore SoCs

Module 4 Business Value of Telecommunication Networks 4.1 Internet Revolution 4.2 Business value of Internet, Intranet and Extranet

PowerAware RTL Verification of USB 3.0 IPs by Gayathri SN and Badrinath Ramachandra, L&T Technology Services Limited

FPGA Adaptive Software Debug and Performance Analysis

2. BOM integration? Variable BOMs? No-pop? How is all that handled in ODB++?

SOFTWARE LIFE-CYCLE MODELS 2.1

Hardware Software Codesign of Embedded System

User-Centered Development

Test Driven Development. René Barto SES Agile Development - Test Driven Development

Integrate Ethernet QVIP in a Few Hours: an A-to-Z Guide by Prashant Dixit, Questa VIP Product Team, Mentor Graphics

The Embedded System Design Process. Wolf Text - Chapter 1.3

Next Generation Verification Process for Automotive and Mobile Designs with MIPI CSI-2 SM Interface

SYSTEMS ON CHIP (SOC) FOR EMBEDDED APPLICATIONS

For a long time, programming languages such as FORTRAN, PASCAL, and C Were being used to describe computer programs that were

ESL design with the Agility Compiler for SystemC

Verification Futures Nick Heaton, Distinguished Engineer, Cadence Design Systems

Strato and Strato OS. Justin Zhang Senior Applications Engineering Manager. Your new weapon for verification challenge. Nov 2017

Stacked Silicon Interconnect Technology (SSIT)

Wai Chee Wong Sr.Member of Technical Staff Freescale Semiconductor. Raghu Binnamangalam Sr.Technical Marketing Engineer Cadence Design Systems

Modeling Performance Use Cases with Traffic Profiles Over ARM AMBA Interfaces

UFS 3.0 Controller Design Considerations

Modeling and Simulation of System-on. Platorms. Politecnico di Milano. Donatella Sciuto. Piazza Leonardo da Vinci 32, 20131, Milano

Will Everything Start To Look Like An SoC?

NetSpeed ORION: A New Approach to Design On-chip Interconnects. August 26 th, 2013

PartnerSURGE Sales & Pre-Sales Certification

Best Practices of SoC Design

The Process of Software Architecting

Verifying the Correctness of the PA 7300LC Processor

High Speed Multi-User ASIC/SoC Prototyping system

Hardware Design Environments. Dr. Mahdi Abbasi Computer Engineering Department Bu-Ali Sina University

Multi-Board Systems Design

Model-Based Design for effective HW/SW Co-Design Alexander Schreiber Senior Application Engineer MathWorks, Germany

Agile Software Development Agile UX Work. Kati Kuusinen TUT / Pervasive / IHTE

Validation Strategies with pre-silicon platforms

Combining TLM & RTL Techniques:

Hardware in the Loop Functional Verification Methodology

eplus Managed Services eplus. Where Technology Means More.

Bibliography. Measuring Software Reuse, Jeffrey S. Poulin, Addison-Wesley, Practical Software Reuse, Donald J. Reifer, Wiley, 1997.

Security. Made Smarter.

Creating an Intranet using Lotus Web Content Management. Part 2 Project Planning

Transcription:

Solving the System-Level Design Riddle

What is the System Design Riddle? With no errors? Then marketing says they need it How do complete my design ontime? Onbudget? Sooner With higher performance n less area Sooner? Sorry, meant early maybe you can drop a feature? Page 2 Sonics, nc. 2014, all rights reserved

DDR3 2133 DDR3 2133 133 Hz 133 Hz On-die SRA DRA Ch. 1 DRA Ch. 2 On-die RO P Control S S 128 128 128 32 32 T T T T T T 533 Hz 1333 Hz 1066 Hz 533 Hz Cortex- A15 Cluster 128 A 2x2 B 2x3 D 1x3 S PCe Cortex- A7 Cluster ali- T658 Cluster Display Video Video HD CC-400 Ctrl. Engine Encode S 128 128 32 32 T E-net E 4x1 C 2x3 SonicsGN Request Network T Security Engine H 5x2 F 4x1 J 3x1 G 4x1 SD/ DA SATA UFS CF/ HS C 267 Hz 133 Hz 133 Hz 133 Hz 133 Hz 32 32 32 32 267 Hz 133 Hz 267 Hz 267 Hz 133 Hz 4x1 267 Hz 267 Hz Cam 1 Cam 2 Audio USB 1 USB 2 USB 3 USB OTG Power Domain Boundary 400 Hz How Sonics helps Sonics on-chip networks help leading SoC designers solve some of the most difficult challenges in SoC design P ntegration 133 Hz 533 Hz 533 Hz 533 Hz Peripherals S S S S 200 Hz 200 Hz 133 Hz 133 Hz 133 Hz 133 Hz High Frequency emory Throughput Physical Design Power anagement Security Time-to-market Development costs Sonics System P: On-chip Networks, emory Subsystem, Power Partitioning & anagement, Performance onitor & Debug, Security Firewalls Page 3 Sonics, nc. 2014, all rights reserved

Sonics The NoC Leader for 18 Years Sonics enables designers to integrate any P from anywhere, anytime Easy P re-use Connecting third party P/subsystems Total System P approach: ntelligent memory scheduling Optimal power-aware designs Data flow services: QoS, Security firewalls Software drivers Commanding presence in digital entertainment, mobile and wireless 200+ SoC tape-outs Results: 2.5B+ units shipped 138+ patent properties mproved TT and quality Page 4 Sonics, nc. 2014, all rights reserved

Does Sonics Solve the Riddle? No, not entirely Using Sonics and other high-quality P will aid greatly But there are limitations that good P alone doesn t solve - Your design methodology is probably wrong, though it may be the best you can do today 5 Sonics, nc. 2014, all rights reserved

What s wrong? Waterfall ethodologies Specification Prototype Design Simulation Verification Emulation Software Sequential operations Little parallelism Changes in one phase may result in a reset of all downstream steps While design reuse (and use of purchased P) is allowed, it cannot be fully exploited f one feature is causing a delay, it may be impossible to move forward with the rest of the design until it is resolved n general, the focus is on the process, rather than the desired outcome Physical Design t s easy to see the problems with the waterfall method. t assumes that every requirement can be identified before any design or coding occurs. 6

Reasons for Changing C ethodology Some drivers for change Consumer products Short release cycle Low power, but still always on Security Design costs ot Starting design without a complete spec akimoto s wave shifts emphasis from standardization to customization System companies are in best position to assume product risk Desired new attributes Ability to make reasonable progress with an incomplete specification To better solve modern design challenges: Time-to-market Power Security Ability to easily ship on-time /early with a reduced feature set mproved relationship between architectural, logical, physical, and software design 7

Why is Sonics leading this? 100% 250 90% 80% 200 Percent of Reuse 70% 60% 50% 40% 30% 20% 150 100 50 Avg, Number of P Blocks 10% 0% 0 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014* 2015* 2016* 2017* 2018* Percent of Reuse Avg. Number of P Blocks Source: Semico Research Corp. Page 8 Sonics, nc. 2014, all rights reserved

Why is Sonics leading this? $70 $120 Dollars $60 $50 $40 $30 $20 $10 $100 $80 $60 $40 $20 Total Dollars $0 90nm 65nm 45nm / 40nm 32nm / 28nm 20nm 14nm* 10nm* $0 Silicon P ntegration Cost Software P ntegration Cost Total P ntegration Cost Source: Semico Research Corp. Page 9 Sonics, nc. 2014, all rights reserved

SoC Architects Drive Both SW & HW SW Development of HWindependent SW Dev. of HWdependent SW and system architecture exploration Large (and growing) teams dependent upon architecture SoC architect responsible for many views of architecture Normally disparate ncreasing complexity of SW and HW results in increased costs and delays HW Performance analysis architecture validation and RTL verification and implementation Page 10 Sonics, nc. 2014, all rights reserved

Worth considering: Agile SW Development The Agile anifesto was written in February of 2001, at a summit of seventeen independent-minded practitioners of several programming methodologies. The participants didn't agree about much, but they found consensus around four main values: ndividuals and interactions over processes and tools Working software over comprehensive documentation Customer collaboration over contract negotiation Responding to change over following a plan Test & Feedback Requirements Development Architecture & Design The Agile movement proposes alternatives to traditional project management. Agile approaches are typically used in software development to help businesses respond to unpredictability. 11

HW and C Design Teams ust Evolve Yesterday Tomorrow Component-Level Aggregation System-Level Architecture One-time Usage Platform Reuse Hierarchical Requirements and Stepwise Design anagement Concurrent Engineering and Agile C ethodology Dedicated Resources Shared Resources 12

What an Agile C ethodology ight Look Like Waterfall Specification Time Prototype Design Simulation Verification Emulation Physical Design 13

What an Agile C ethodology ight Look Like Agile C ethodology Specification Prototype Design Simulation Verification Emulation Physical Design 14 Time Change the slope! The more vertical the better!

Short term actions Sonics Plan Get the discussion started Create the communications links Gather the interested parties How you can help Join the Linkedn group Participate in the conversation nvite others to get involved too Step 1: Join the Agile C ethodology group on Linkedn Step 2: Join the conversation participate! 15

Partnering to Win with Sonics Now, and in the Future Sonics has The best technology The strongest commitment The largest team The most experience The best support The strongest roadmap What can we do to help your team? Page 16 Sonics, nc. 2014, all rights reserved