University of California at Berkeley College of Engineering epartment of Electrical Engineering and Computer Sciences EECS150 J. Wawrzynek Spring 2003 2/21/03 Exam I Solutions Name: I number: This is a closed-book, closed-note exam. No calculators please. You have 3 hours. Each question is marked with its number of points (one point per expected minute of time). Put your name and SI on each page. You can work out your answers on the backs of the pages and use the extra blank sheets at the end of the booklet. Show your work. Write neatly and be well organized. Good luck! problem maximum score 1 10pts 2 8pts 3 10pts 4 12pts 5 7pts 6 7pts 7 7pts 8 17pts 9 22pts total 100pts
1. [10pts] Short Answer. a) The largest (and most advanced) chips produced today contain approximately how many transistors? (100 thousand, 100 million, 100 billion) 100 Million b) Moore s law says that the number of transistors on a chip doubles every how many months? 18 months c) FPGAs are often used instead of ASICs in digital systems because they (reduce time to market, improve performance, or both)? Reduce time to market d) Internally an n-lut may be implemented using how many latches? e) An n-lut can implement how many different functions? f) Write the Boolean equation for the sum output (s) of a full-adder cell: 2 N N 2 2 S = A B C in g) Write the Boolean equation for the carry output (c) of a full-adder cell: C = AB + AC in + BC in = (A B)C in + AB h) Sketch the circuit for a 4-bit ripple-adder based instances of the full-adder cell: i) Simplify (x + y)(x + y): Y e) Write the canonical product-of-sums form for exor(a,b): ( A + B ) (A + B) 2
2. a) [3pts] Using instances of a positive-level sensitive latch, shown to the right, along with any simple logic gates required, draw the circuit for a negativeedge triggered -type flip-flop. b) [5pts] The waveforms below for the signal c and x are applied to the circuit to the right. Fill in the resulting waveform that would appear at y. x c c y c x y 3
3. a) [3pts] The circuit shown to the right is a kind of 3-input NOR-gate. Write a Boolean expression in terms of a, b, and c, that would need to be applied to x for correct operation: a x b c X = A B C X = A + B + C b) [7pts] Using nothing but non-inverting tristate buffers, shown to the right, draw a circuit that implements a 3-input multiplexor. Label the inputs as a, b, and c, the control as s0 and s1, and the output as x. The multiplexor has the following action: if [s1 s0] = 00, output a; if [s1 s0] = 10, output b; if [s1 s0] = 01 or 11, output c. 4. S1 S0 A ENB ENB B ENB C ENB 4
a) [5pts] Is it possible to map the following Boolean expression to the CLB structure shown below? If so, prove it by labeling the inputs with the appropriate variables and the internal wires with the corresponding Boolean expressions. Complemented inputs are not available. F = ac + ad + a e f = a ( c + d ) + a (e f ) A E F C 2-LUT 2-LUT 0 1 F b) [3pts] Based on the CLB structure from part a), show how to partition the following circuit into the minimum number of CLBs by carefully drawing circles around sets of gates, one circle per CLB: c) [4pts] Reorganize the circuit from part b) and partition it, based on the CLB structure from part a), to achieve less delay. raw your result below: 5
5. Consider the following logic circuit. a b c d f a) [3pts] Write an unreduced expression for f: F = ab(ab+cd)+cd b) [4pts] Simplify the expression (minimize the number of literals). Show all steps and your final result below: F = abab + abcd + cd F = ab + abcd + cd F = ab (1 + cd) + cd F = ab (1) +cd F = ab + cd 6
6. [7pts] Convert the following sum-of-products expression to product-of-sums form. Hint: use a K-map. A B C + A BC + ABC + A B ab cd 00 01 11 10 00 1 1 01 1 1 1 11 1 10 1 (a + b + c + d) ( a + c ) ( b + c ) ( a + b) 7
8 7. [7pts] erive a circuit that implements the following Boolean expression using as few 2-input NAN-gates as possible. Show your work and the resulting circuit below. Complemented inputs are not available. (A +B )(C + ) + (E +F )(G +H ) ((AB) (C) + (EF) (GH) ) (((AB) (C) ) ((EF) (GH) ) ) A B C E F G H A B C E F G H A B C E F G H
8. Consider the design of a Verilog module that computes the maximum value of two unsigned 2-bit integers, A and B. A B 2 2 MAX 2 M a) [5pts] Write the behavioral Verilog description below: Module Prob8_a( A, B, M); Input [1:0] A,B; Output [1:0] M; assign M = (A>B)?A:B; endmodule; 9
b) [12pts] Using instances only of simple logic gates (with any number of inputs), write a structural Verilog description. Your description must use the minimum total number of logic gates needed. Show your work. Logic derivation and simplification: 00 01 11 10 00 0 0 1 1 01 0 0 1 1 11 1 1 1 1 10 1 1 1 1 00 01 11 10 00 0 1 1 0 01 1 1 1 0 11 1 1 1 1 10 0 0 1 0 10
Write the structural Verilog description below (gates only): Module Prob8_b( A, B, M); Input [1:0] A,B; Output [1:0] M; wire nota1,notb1,t_1,t_2,t_3; not(nota1,a[1]); not(notb1,b[1]); Or(M[1],A[1],B[1]); Or(t_1,A[0],B[0]); Or(t_2,A[1],notB1,B[0]); Or(t_3,notA1,A[0],B[1]) And(M[0],t_1,t_2,t_3); endmodule; 11
9. Consider the design of a Moore style finite state machine (FSM) with two inputs, and CE, one 2-bit wide output X, and no reset input. is the clock signal and CE is the count enable signal. While CE=1, the FSM behaves as a binary counter, i.e. its output cycles through the pattern 00, 01, 10, 11, 00, moving from one output value to the next on each positive edge of. If CE=0 the output value remains unchanged. Note that the FSM has no reset input signal. You can assume that it starts up in any legal state. a) [3pts] Sketch the state transition diagram that represents the behavior of this FSM: CE' CE' S0 [00] CE CE CE S1 [01] S2 [10] S3 [11] CE' CE' CE b) [2pts] Sketch the circuit diagram for the FSM. You do not need to show the details of the combinational logic part of the circuit (just show it as a box labeled CL ). Label all inputs and outputs: CE CL SET CLR X CLK 12
c) [7pt] Write a Verilog description of this FSM. You are allowed to describe the combinational logic part of the circuit using a behavioral description: Module bcounter (,CE, x); input,ce; output [1:0] x; reg [1:0] CS, NS, x; parameter s0=2 b00,s1=2 b01,s2=2 b10,s3=2 b11; always@(cs) begin X = CS; case (CS) s0: NS = s1; s1: NS = s2; s2: NS = s3; s3: NS = s0; endcase end always@(posedge ) CS<=CE?NS:CS; endmodule 13
d) [10pts] raw a circuit diagram for a one-hot encoded version of the FSM. For this part, show all details of any combinational logic. on t forget to show the output circuitry. CE SET CLR CE X[0] SET CE CLR SET CE CLR X[1] SET CLR 14