Minimizing Data hazard Stalls by Forwarding Data Hazard Classification Data Hazards Present in Current MIPS Pipeline

Instruction Pipelining Review: MIPS In-Order Single-Issue Integer Pipeline Performance of Pipelines with Stalls Pipeline Hazards Structural hazards Data hazards Minimizing Data hazard Stalls by Forwarding Data Hazard Classification Data Hazards Present in Current MIPS Pipeline Control hazards Reducing Branch Stall Cycles Static Compiler Branch Prediction Delayed Branch Slot Canceling Delayed Branch Slot Pipelining and Handling of Exceptions Precise exception Handling Pipelined MIPS CPU Design from 350 Extending The MIPS Pipeline to Handle Floating-Point Operations Pipeline Characteristics With FP Support Maintaining Precise Exceptions in FP/Multicycle Pipelining (In Appendix A) #1 Lec # 2 Fall 2014 8-27-2014

Instruction Pipelining Review Instruction pipelining is CPU implementation technique where multiple operations on a number of instructions are overlapped. Instruction pipelining exploits Instruction-Level Parallelism (ILP) An instruction execution pipeline involves a number of steps, where each step completes a part of an instruction. Each step is called a pipeline stage or a pipeline segment. The stages or steps are connected in a linear fashion: one stage to the next to form the pipeline -- instructions enter at one end and progress through the stages and exit at the other end. 1 2 3 4 5 The time to move an instruction one step down the pipeline is is equal to the machine cycle and is determined by the stage with the longest processing delay. Pipelining increases the CPU instruction throughput: The number of instructions completed per cycle. Under ideal conditions (no stall cycles), instruction throughput is one instruction per machine cycle, or ideal CPI = 1 Or IPC = 1 Pipelining does not reduce the execution time of an individual instruction: The time needed to complete all processing steps of an instruction (also called instruction completion latency). Pipelining may actually increase individual instruction latency Minimum instruction latency = n cycles, where n is the number of pipeline stages (In Appendix A and 350) The pipeline described here is called an in-order pipeline because instructions are processed or executed in the original program order Order = Program order T = I x CPI x C #2 Lec # 2 Fall 2014 8-27-2014

Generic CPU Machine Instruction Processing Steps Instruction Fetch (Implied by The Von Neumann Computer Model) Obtain instruction from program storage The Program Counter (PC) points to next instruction to be processed Instruction Decode Operand Fetch Execute Result Store Next Instruction Determine required actions and instruction size Locate and obtain operand data Compute result value or status Deposit results in storage for later use Determine successor or next instruction (i.e Update PC) Major CPU Performance Limitation: The Von Neumann computing model implies sequential execution one instruction at a time #3 Lec # 2 Fall 2014 8-27-2014

Program Order 1 2 3 4 5 MIPS In-Order Single-Issue Integer Pipeline i.e execution in program order Ideal Operation Fill Cycles = number of stages -1 Clock Number Time in clock cycles Instruction Number 1 2 3 4 5 6 7 8 9 Instruction I IF ID EX MEM WB Instruction I+1 IF ID EX MEM WB Instruction I+2 IF ID EX MEM WB Instruction I+3 IF ID EX MEM WB Instruction I +4 IF ID EX MEM WB 4 cycles = n -1 Time to fill the pipeline MIPS Pipeline Stages: IF = Instruction Fetch ID = Instruction Decode EX = Execution MEM = Memory Access WB = Write Back (In Appendix A) First instruction, I Completed In-order = instructions executed in original program order Ideal pipeline operation without any stall cycles (No stall cycles) (Classic 5-Stage) Last instruction, I+4 completed n= 5 pipeline stages Ideal CPI =1 (or IPC =1) #4 Lec # 2 Fall 2014 8-27-2014

A Pipelined MIPS Integer Datapath Pipeline Version 1 (in 350): No Forwarding, Branch resolved in MEM stage Assume register writes occur in first half of cycle and register reads occur in second half. IF Stage 1 ID EX Stage 2 Stage 3 Branches resolved Here in MEM (Stage 4) MEM Stage 4 WB Stage 5 Classic Five Stage Integer Single-Issue In-Order Pipeline for MIPS Taken Branch Penalty = 4-1 = 3 cycles (In Appendix A and 350) #5 Lec # 2 Fall 2014 8-27-2014

1 IF ID EX MEM WB 2 Write destination register in first half of WB cycle IF ID EX MEM WB 3 IF ID EX MEM WB 4 Read operand registers in second half of ID cycle IF ID EX MEM WB 5 Operation of ideal integer in-order 5-stage pipeline IF ID EX MEM WB (In Appendix A and 350) #6 Lec # 2 Fall 2014 8-27-2014

CPI = 1 Pipelining Performance Example Example: For an unpipelined CPU: Clock cycle = 1ns, 4 cycles for ALU operations and branches and 5 cycles for memory operations with instruction frequencies of 40%, 20% and 40%, respectively. If pipelining adds 0.2 ns to the machine clock cycle then the speedup in instruction execution from pipelining is: Non-pipelined Average instruction execution time = Clock cycle x Average CPI = 1 ns x ((40% + 20%) x 4 + 40%x 5) = 1 ns x 4.4 = 4.4 ns CPI = 4.4 In the pipelined implementation five stages are used with an average instruction execution time of: 1 ns + 0.2 ns = 1.2 ns Speedup from pipelining = Instruction time unpipelined Instruction time pipelined = 4.4 ns / 1.2 ns = 3.7 times faster T = I x CPI x C here I did not change #7 Lec # 2 Fall 2014 8-27-2014

Resource Not available: Pipeline Hazards Hazards are situations in pipelining which prevent the next instruction in the instruction stream from executing during the designated clock cycle possibly resulting in one or more stall (or wait) cycles. Hazards reduce the ideal speedup (increase CPI > 1) gained from pipelining and are classified into three classes: Hardware Component Correct Operand (data) value Correct PC Structural hazards: Arise from hardware resource conflicts when the available hardware cannot support all possible combinations of instructions. Data hazards: Arise when an instruction depends on the result of a previous instruction in a way that is exposed by the overlapping of instructions in the pipeline Control hazards: Arise from the pipelining of conditional branches and other instructions that change the PC (In Appendix A and 350) Correct PC not available when needed in IF i.e A resource the instruction requires for correct execution is not available in the cycle needed Hardware structure (component) conflict Operand not ready yet when needed in EX #8 Lec # 2 Fall 2014 8-27-2014

Performance of Pipelines with Stalls Hazard conditions in pipelines may make it necessary to stall the pipeline by a number of cycles degrading performance from the ideal pipelined CPU CPI of 1. CPI pipelined = Ideal CPI + Pipeline stall clock cycles per instruction = 1 + Pipeline stall clock cycles per instruction If pipelining overhead is ignored and we assume that the stages are perfectly balanced then speedup from pipelining is given by: Speedup = CPI unpipelined / CPI pipelined = CPI unpipelined / (1 + Pipeline stall cycles per instruction) When all instructions in the multicycle CPU take the same number of cycles equal to the number of pipeline stages then: Speedup = Pipeline depth / (1 + Pipeline stall cycles per instruction) (In Appendix A and 350) T = I x CPI x C IPC= 1/CPI #9 Lec # 2 Fall 2014 8-27-2014

Structural (or Hardware) Hazards In pipelined machines overlapped instruction execution requires pipelining of functional units and duplication of resources to allow all possible combinations of instructions in the pipeline. If a resource conflict arises due to a hardware resource being required by more than one instruction in a single cycle, and one or more such instructions cannot be accommodated, then a structural hazard has occurred, for example: e.g. May need stall cycles to prevent hardware structures conflicts when a pipelined machine has a shared single-memory pipeline stage for data and instructions. stall the pipeline for one cycle for memory data access i.e A hardware component the instruction requires for correct execution is not available in the cycle needed (In Appendix A and 350) #10 Lec # 2 Fall 2014 8-27-2014

IF ID EX MEM WB Or store One shared memory for instructions and data IF ID EX MEM WB Program Order IF ID EX MEM WB IF ID EX MEM WB (In Appendix A and 350) MIPS with Memory Unit Structural Hazards IF ID EX MEM #11 Lec # 2 Fall 2014 8-27-2014

CPI = 1 + stall clock cycles per instruction = 1 + fraction of loads and stores x 1 IF ID EX MEM WB Or store One shared memory for instructions and data Program Order Stall or wait Cycle (In Appendix A and 350) Resolving A Structural Hazard with Stalling Instructions 1-3 above are assumed to be instructions other than loads/stores IF ID EX MEM #12 Lec # 2 Fall 2014 8-27-2014

A Structural Hazard Example (i.e loads/stores) Given that data references are 40% for a specific instruction mix or program, and that the ideal pipelined CPI ignoring hazards is equal to 1. A machine with a data memory access structural hazards requires a single stall cycle for data references and has a clock rate 1.05 times higher than the ideal machine. Ignoring other performance losses for this machine: Average instruction time = CPI X Clock cycle time Average instruction time = (1 + 0.4 x 1) x Clock cycle ideal CPI = 1.4 1.05 = 1.3 X Clock cycle time ideal i.e. CPU without structural hazard is 1.3 times faster (In Appendix A and 350) #13 Lec # 2 Fall 2014 8-27-2014

Data Hazards Data hazards occur when the pipeline changes the order of read/write accesses to instruction operands in such a way that the resulting access order differs from the original sequential instruction operand access order of the unpipelined machine resulting in incorrect execution. Data hazards may require one or more instructions to be stalled to ensure correct execution. Example: Producer of Result (data) 1 2 3 4 5 Consumers of Result (data) DADD R1, R2, R3 DSUB R4, R1, R5 AND R6, R1, R7 OR R8,R1,R9 XOR R10, R1, R11 All the instructions after DADD use the result of the DADD instruction DSUB, AND instructions need to be stalled for correct execution. i.e Correct operand data not ready yet when needed in EX cycle (In Appendix A and 350) CPI = 1 + stall clock cycles per instruction Arrows represent data dependencies between instructions Instructions that have no dependencies among them are said to be parallel or independent A high degree of Instruction-Level Parallelism (ILP) is present in a given code sequence if it has a large number of parallel instructions #14 Lec # 2 Fall 2014 8-27-2014

Program Order 1 2 3 4 5 Data Hazard Example Figure A.6 The use of the result of the DADD instruction in the next three instructions causes a hazard, since the register is not written until after those instructions read it. (In Appendix A) Two stall cycles are needed here (to prevent data hazard) #15 Lec # 2 Fall 2014 8-27-2014

Minimizing Data Hazard Stalls by Forwarding Data forwarding is a hardware-based technique (also called register bypassing or short-circuiting) used to eliminate or minimize data hazard stalls. Using forwarding hardware, the result data of an instruction is copied directly from where it is produced (ALU, memory read port etc.), to where subsequent instructions need it (ALU input register, memory write port etc.) For example, in the MIPS integer pipeline with forwarding: The ALU result from the EX/MEM register may be forwarded or fed back to the ALU input latches as needed instead of the register operand value read in the ID stage. Similarly, the Data Memory Unit result from the MEM/WB register may be fed back to the ALU input latches as needed. If the forwarding hardware detects that a previous ALU operation is to write the register corresponding to a source for the current ALU operation, control logic selects the forwarded result as the ALU input rather than the value read from the register file. (In Appendix A and 350) #16 Lec # 2 Fall 2014 8-27-2014

ID EX MEM WB 1 2 3 1 3 1 2 3 2 Forwarding Paths Added Pipeline Version 2 (in 350): With Forwarding, Branch resolved in MEM stage #17 Lec # 2 Fall 2014 8-27-2014

Program Order 1 Forward 2 Forward 3 4 5 Pipeline with Forwarding A set of instructions that depend on the DADD result uses forwarding paths to avoid the data hazard (In Appendix A and 350) #18 Lec # 2 Fall 2014 8-27-2014

Program Order Load/Store Forwarding Example 1 2 Load 3 Store Forwarding of operand required by store during MEM #19 Lec # 2 Fall 2014 8-27-2014

Data Hazard Classification Given two instructions I, J, with I occurring before J in an instruction stream (program execution order): RAW (read after write): A true data dependence violation J tried to read a source before I writes to it, so J incorrectly gets the old value. WAW (write after write): A name dependence violation J tries to write an operand before it is written by I The writes end up being performed in the wrong order. WAR (write after read): A name dependence violation J tries to write to a destination before it is read by I, so I incorrectly gets the new value. RAR (read after read): Not a hazard. I.... J Program Order #20 Lec # 2 Fall 2014 8-27-2014

I (Write) Data Hazard Classification I (Read) I.... J e.g ADD.D F2, F1, F0 e.g ADD.D F8, F2, F9 J (Read) Shared Operand e.g ADD.D F2, F1, F0 e.g ADD.D F1, F3, F4 J (Write) Shared Operand Or Name Program Order Read after Write (RAW) I (Write) Write after Read (WAR) I (Read) e.g ADD.D F2, F1, F0 e.g ADD.D F2, F5, F7 J (Write) Shared Operand Or Name e.g ADD.D F2, F4, F6 e.g ADD.D F8, F4, F6 J (Read) Shared Operand Write after Write (WAW) Read after Read (RAR) not a hazard #21 Lec # 2 Fall 2014 8-27-2014

Data Hazards Present in Current MIPS Pipeline Read after Write (RAW) Hazards: Possible? Results from true data dependencies between instructions. Yes possible, when an instruction requires an operand generated by a preceding instruction with distance less than four. Resolved by: Forwarding and/or Stalling. Write after Read (WAR) Hazard: Results when an instruction overwrites the result of an instruction before all preceding instructions have read it. Write after Write (WAW) Hazard: Results when an instruction writes into a register or memory location before a preceding instruction have written its result. Possible? Both WAR and WAW are impossible in the current pipeline. Why? Pipeline processes instructions in the same sequential order as in the program. All instruction operand reads are completed before a following instruction overwrites the operand. Thus WAR is impossible in current MIPS pipeline. All instruction result writes are done in the same program order. Thus WAW is impossible in current MIPS pipeline. i.e In-Order Integer Pipeline MIPS in-order integer pipeline i.e WAW impossible because instructions reach WB stage in program order #22 Lec # 2 Fall 2014 8-27-2014

RAW Data Hazards Requiring Stall Cycles In some code sequence cases, potential data hazards cannot be handled by bypassing. For example: LD R1, 0 (R2) DSUB R4, R1, R5 AND R6, R1, R7 OR R8, R1, R9 The LD (load double word) instruction has the data in clock cycle 4 (MEM cycle). The DSUB instruction needs the data of R1 in the beginning of that cycle. Hazard prevented by hardware pipeline interlock causing a stall cycle. (In Appendix A) i.e. a load instruction followed immediately with an instruction that uses the loaded value #23 Lec # 2 Fall 2014 8-27-2014

Program Order 1 One stall needed 2 3 4 A Data Hazard Requiring A Stall: A load instruction followed immediately with an instruction that uses the loaded value (In Appendix A and 350) #24 Lec # 2 Fall 2014 8-27-2014

Hardware Pipeline Interlocks A hardware pipeline interlock detects a data hazard and stalls the pipeline until the hazard is cleared. The CPI for the stalled instruction increases by the length of the stall. For the Previous example, (no stall cycle): LD R1, 0(R1) IF ID EX MEM WB DSUB R4,R1,R5 IF ID EX MEM WB AND R6,R1,R7 IF ID EX MEM WB OR R8, R1, R9 IF ID EX MEM WB With Stall Cycle: Stall + Forward Incorrect Execution Correct Execution LD R1, 0(R1) IF ID EX MEM WB DSUB R4,R1,R5 IF ID STALL EX MEM WB AND R6,R1,R7 IF STALL ID EX MEM WB OR R8, R1, R9 STALL IF ID EX MEM WB (In Appendix A) One stall #25 Lec # 2 Fall 2014 8-27-2014

Program Order 1 LD R1,0(R1) Stall one cycle then, forward data of LD instruction to DSUB instruction 2 Stall DSUB R4, R1,R5 3 Then Stall + Forward First stall one cycle then forward 4 One Stall A Data Hazard Requiring A Stall: A load followed immediately by an instruction that uses the loaded value in EX stage results in a single stall cycle even with forwarding as shown. #26 Lec # 2 Fall 2014 8-27-2014

Stall + forward Stall + Forward Forward Hazard Detection Unit Operation #27 Lec # 2 Fall 2014 8-27-2014

Static Compiler Instruction Scheduling (Re-Ordering) for Data Hazard Stall Reduction Many types of stalls resulting from data hazards are very frequent. For example: A = B + C produces a stall when loading the second data value (B). Rather than allow the pipeline to stall, the compiler could sometimes schedule the pipeline to avoid stalls. i.e re-order instructions or reduce Compiler pipeline or instruction scheduling involves rearranging the code sequence (instruction reordering) to eliminate or reduce the number of stall cycles. (In Appendix A) Static = At compilation time by the compiler Dynamic = At run time by hardware in the CPU #28 Lec # 2 Fall 2014 8-27-2014

1 2 Static Compiler Instruction Scheduling Example For the code sequence: 1 a = b + c 2 d = e - f a, b, c, d,e, and f are in memory Assuming loads have a latency of one clock cycle, the following code or pipeline compiler schedule eliminates stalls: Original code with stalls: LD Rb,b Stall LD Rc,c DADD Ra,Rb,Rc SD Ra,a LD Re,e Stall LD Rf,f DSUB Rd,Re,Rf SD Rd,d 2 stalls for original code e.g. 0(R1) Pipeline with forwarding assumed here Re-order Instructions to eliminate stalls Scheduled code with no stalls: LD Rb,b LD Rc,c LD Re,e DADD Ra,Rb,Rc LD Rf,f SD Ra,a DSUB Rd,Re,Rf SD Rd,d No stalls for scheduled code #29 Lec # 2 Fall 2014 8-27-2014

i.e version 2 Control Hazards When a conditional branch is executed it may change the PC and, without any special measures, leads to stalling the pipeline for a number of cycles until the branch condition is known (branch is resolved). Otherwise the PC may not be correct when needed in IF In current MIPS pipeline, the conditional branch is resolved in stage 4 (MEM stage) resulting in three stall cycles as shown below: Branch instruction IF ID EX MEM WB Branch successor stall stall stall IF ID EX MEM WB Branch successor + 1 IF ID EX MEM WB Branch successor + 2 IF ID EX MEM 3 stall cycles Branch successor + 3 IF ID EX Branch successor + 4 IF ID Branch Penalty Branch successor + 5 IF Assuming we always stall or flush the pipeline on a branch instruction: Three clock cycles are wasted for every branch for current MIPS pipeline (In Appendix A and 350) Branch Penalty = stage number where branch is resolved - 1 here Branch Penalty = 4-1 = 3 Cycles i.e Correct PC is not available when needed in IF Correct PC available here (end of MEM cycle or stage) #30 Lec # 2 Fall 2014 8-27-2014

Reducing Branch Stall Cycles Pipeline hardware measures to reduce branch stall cycles: 1- Find out whether a branch is taken earlier in the pipeline. 2- Compute the taken PC earlier in the pipeline. In MIPS: i.e Resolve the branch in an early stage in the pipeline In MIPS branch instructions BEQZ, BNE, test a register for equality to zero. This can be completed in the ID cycle by moving the zero test into that cycle. Both PCs (taken and not taken) must be computed early. Requires an additional adder because the current ALU is not useable until EX cycle. This results in just a single cycle stall on branches. As opposed branch penalty = 3 cycles before #31 Lec # 2 Fall 2014 8-27-2014

Branch resolved in stage 2 (ID) Branch Penalty = 2-1 = 1 cycle Modified MIPS Pipeline: Conditional Branches Completed (resolved) in ID Stage (stage2) Stage 2 ID Stage 3 Stage 4 Stage 5 EX MEM WB IF Stage 1 Pipeline Version 3 (in 350): With Forwarding, Branch resolved in ID stage (In Appendix A and 350) #32 Lec # 2 Fall 2014 8-27-2014

Compile-Time Reduction of Branch Penalties 1 2 Most Common 3 How to handle branches in a pipelined CPU? One scheme discussed earlier is to flush or freeze the pipeline by whenever a conditional branch is decoded by holding or deleting any instructions in the pipeline until the branch destination is known (zero pipeline registers, control lines). (or assume) Another method is to predict that the branch is not taken where the state of the machine is not changed until the branch outcome is definitely known. Execution here continues with the next instruction; stall occurs here when the branch is taken. (or assume) i.e always stall on a branch i.e PC+4 Another method is to predict that the branch is taken and begin fetching and executing at the target; stall occurs here if the branch is not taken. (harder to implement more on this later). Delayed Branch: An instruction following the branch in a branch delay slot is executed whether the branch is taken or not (part of the ISA). Supported by all RISC ISAs #33 Lec # 2 Fall 2014 8-27-2014

Predict Branch Not-Taken Scheme (or assume) Not Taken Branch (no stall) (most common scheme) Taken Branch (stall) Stall Assuming the MIPS pipeline with reduced branch penalty = 1 i.e Pipeline Version 3 Stall when the branch is taken Pipeline stall cycles from branches = frequency of taken branches X branch penalty CPI = 1 + stall clock cycles per instruction #34 Lec # 2 Fall 2014 8-27-2014

Pipeline Performance Example Assume the following MIPS instruction mix: Type Frequency Arith/Logic 40% Load 30% of which 25% are followed immediately by an instruction using the loaded value Store 10% branch 20% of which 45% are taken 1 stall 1 stall What is the resulting CPI for the pipelined MIPS with forwarding and branch address calculation in ID stage when using a branch not-taken scheme? CPI = Ideal CPI + Pipeline stall clock cycles per instruction = 1 + stalls by loads + stalls by branches = 1 +.3 x.25 x 1 +.2 x.45 x 1 = 1 +.075 +.09 = 1.165 Branch Penalty = 1 cycle #35 Lec # 2 Fall 2014 8-27-2014 i.e Pipeline Version 3

Static Compiler Branch Prediction Static Branch prediction encoded in branch instructions using one prediction bit = 0 = Not Taken, = 1 = Taken How? Must be supported by ISA, Ex: HP PA-RISC, PowerPC, UltraSPARC Two basic methods exist to statically predict branches at compile time: Branch Encoding 1 By examination of program behavior and the use of information collected from earlier runs of the program. X X = Static Prediction bit X= 0 Not Taken X = 1 Taken For example, a program profile may show that most forward branches and backward branches (often forming loops) are taken. The simplest scheme in this case is to just predict the branch as taken. 2 To predict branches on the basis of branch direction, choosing backward branches as taken and forward branches as not taken. Static = By the compiler Program profile-based static branch prediction Loop? Dynamic = By hardware in the CPU #36 Lec # 2 Fall 2014 8-27-2014

Static Branch Prediction Performance: Profile-Based Compiler Branch Misprediction Rates for SPEC92 More Loops (FP has more loops) Integer Average 15% Floating Point Average 9% #37 Lec # 2 Fall 2014 8-27-2014

ISA Reduction of Branch Penalties: Delayed Branch (action) When delayed branch is used, the branch is delayed by n cycles, following this execution pattern: conditional branch instruction i.e. ISA Support Needed Program Order sequential successor 1 sequential successor 2.. }n branch action delay slots These instructions in branch delay slots are always executed regardless of branch direction sequential successor n branch target if taken The sequential successor instruction are said to be in the branch delay slots. These instructions are executed whether or not the branch is taken. In Practice, all machines that utilize delayed branching have a single instruction delay slot. (All RISC ISAs) The job of the compiler is to make the successor instruction in the delay slot a valid and useful instruction. #38 Lec # 2 Fall 2014 8-27-2014

Delayed Branch Example Not Taken Branch (no stall) Taken Branch (no stall) Single Branch Delay Slot Used Assuming branch penalty = 1 cycle i.e. Pipeline Version # 3 All RISC ISAs #39 Lec # 2 Fall 2014 8-27-2014

Delayed Branch-delay Slot Scheduling Strategies The branch-delay slot instruction can be chosen from three cases: A An independent instruction from before the branch: Always improves performance when used. The branch must not depend on the rescheduled instruction. B An instruction from the target of the branch: Improves performance if the branch is taken and may require instruction duplication. This instruction must be safe to execute if the branch is not taken. Hard to Find C An instruction from the fall through instruction stream: Improves performance when the branch is not taken. The instruction must be safe to execute when the branch is taken. The performance and usability of cases B, C is improved by using a canceling or nullifying branch. Most Common e.g From Body of a loop #40 Lec # 2 Fall 2014 8-27-2014

(A) (B) (C) Example: From the body of a loop (In Appendix A) Most Common #41 Lec # 2 Fall 2014 8-27-2014

Branch-delay Slot: Canceling Branches (AKA Canceling Delayed Branch Action) In a canceling branch, a static compiler branch direction prediction is included with the branch-delay slot instruction. Branch Encoding X X = Static Prediction bit X= 0 Not Taken X = 1 Taken When the branch goes as predicted, the instruction in the branch delay slot is executed normally. When the branch does not go as predicted the instruction is turned into a no-op (i.e. cancelled). Why? Canceling branches eliminate the conditions on instruction selection in delay instruction strategies B, C The effectiveness of this method depends on whether we predict the branch correctly. #42 Lec # 2 Fall 2014 8-27-2014

Pipeline Version # 3 Assumed Here Branch Goes Not As Predicted Cancelled Stall or No-OP Branch Goes As Predicted Normal No Stall Branch Predicted Taken By Compiler Canceling Branch Example Predicted Taken #43 Lec # 2 Fall 2014 8-27-2014

Performance Using Canceling Delay Branches MIPS 70% Static Prediction Accuracy #44 Lec # 2 Fall 2014 8-27-2014

The MIPS R4000 Integer Pipeline Implements MIPS64 but uses an 8-stage pipeline instead of the classic 5- stage pipeline to achieve a higher clock speed. Pipeline Stages: IF: First half of instruction fetch. Start instruction cache access. IS: Second half of instruction fetch. Complete instruction cache access. RF: Instruction decode and register fetch, hazard checking. EX: Execution including branch-target and condition evaluation. DF: Data fetch, first half of data cache access. Data available if a hit. DS: Second half of data fetch access. Complete data cache access. Data available if a cache hit TC: Tag check, determine data cache access hit. WB: Write back for loads and register-register operations. Branch resolved in stage 4. Branch Penalty = 3 cycles if taken ( 2 with branch delay slot) (In Appendix A) 1 2 3 4 5 6 7 8 Branch resolved here in stage 4 Thus branch penalty = 4-1 = 3 cycles #45 Lec # 2 Fall 2014 8-27-2014

Deeper Pipelines = More Stall Cycles and Higher CPI T = I x CPI x C MIPS R4000 Example LW data available here Program Order Even with forwarding the deeper pipeline leads to a 2-cycle load delay (2 stall cycles). (In Appendix A) Forwarding of LW Data As opposed to 1-cycle in classic 5-stage pipeline #46 Lec # 2 Fall 2014 8-27-2014

Pipelining and Handling of Exceptions Exceptions are events that usually occur in normal program execution where the normal execution order of the instructions is changed (often called: interrupts, faults). Types of exceptions include: I/O device request Invoking an operating system service Tracing instruction execution Breakpoint (programmer-requested interrupt). Integer overflow or underflow FP anomaly Page fault (not in main memory) Misaligned memory access Memory protection violation Undefined instruction Hardware malfunctions #47 Lec # 2 Fall 2014 8-27-2014

Characteristics of Exceptions Synchronous vs. asynchronous: Synchronous: occurs at the same place with the same data and memory allocation Asynchronous: Caused by devices external to the processor and memory. User requested vs. coerced: User requested: The user task requests the event. Coerced: Caused by some hardware event. User maskable vs. user nonmaskable: User maskable: Can be disabled by the user task using a mask. Within vs. between instructions: Whether it prevents instruction completion by happening in the middle of execution. Resuming vs. terminating: Terminating: The program execution always stops after the event. Resuming: the program continues after the event. The state of the pipeline must be saved to handle this type of exception. The pipeline is restartable in this case. #48 Lec # 2 Fall 2014 8-27-2014

Handling of Resuming Exceptions A resuming exception (e.g. a virtual memory page fault) usually requires the intervention of the operating system. To handle the exception The pipeline must be safely shut down and its state saved for the execution to resume after the exception is handled as follows: 1 Force a trap instruction into the pipeline on the next IF. 2 Turn of all writes for the faulting instruction and all (following) instructions in the pipeline. Place zeroes into pipeline latches starting with the instruction that caused the fault to prevent state changes. is invoked 3 The exception handling routine of the operating system saves the PC of the faulting instruction and other state data to be used to return from the exception. i.e save program state #49 Lec # 2 Fall 2014 8-27-2014

Exception Handling Issues: Precise Exception Handling When using delayed branches, as many PCs as the the length of the branch delay plus one need to be saved and restored to restore the state of the machine. After the exception has been handled special instructions are needed to return the machine to the state before the exception occurred (RFE, Return to User code in MIPS). Precise exceptions and handling imply that a pipeline is stopped so the instructions just before the faulting instruction are completed and and those after it can be restarted from scratch. After handling the exception (i.e. As if processor is not pipelined) Machines with arithmetic trap handlers and demand paging must support precise exceptions. i.e Precise exception handling imply handling exceptions as if the processor is not pipelines #50 Lec # 2 Fall 2014 8-27-2014

Exceptions in MIPS Integer Pipeline The following represent problem exceptions for the MIPS 5 pipeline stages: IF Page fault on instruction fetch; misaligned memory access; memory-protection violation. ID Undefined or illegal opcode EX Arithmetic exception MEM Page fault on data fetch; misaligned memory access; memory-protection violation WB None Program Order Example: LD IF ID EX MEM WB DADD IF ID EX MEM WB can cause a data page fault and an arithmetic exception at the same time ( LD in MEM and DADD in EX) Handled by dealing with data page fault and then restarting execution, then the second exception will occur but not the first. i.e handle exceptions in program order one at a time (as if processor is not pipelined) #51 Lec # 2 Fall 2014 8-27-2014

Precise Exception Handling in MIPS (i.e MIPS Integer Single-Issue In-Order Pipeline) How? 1 2 3 The instruction pipeline is required to handle exceptions of instruction i before those of instruction i+1 i.e in program order The hardware posts all exceptions caused by an instruction in a status vector associated with the instruction which is carried along with the instruction as it goes through the pipeline. Once an exception indication is set in the vector, any control signals that cause a data value write is turned off. For the following instructions When an instruction enters WB the vector is checked, if any exceptions are posted, they are handled in the order they would be handled in an unpipelined machine. i.e in program order Any action taken in earlier pipeline stages is invalid but cannot change the state of the machine since writes where disabled. i.e by later instructions in program order #52 Lec # 2 Fall 2014 8-27-2014

Floating Point/Multicycle Pipelining in MIPS Completion of MIPS EX stage floating point arithmetic operations in one or two cycles is impractical since it requires: Solution: A much longer CPU clock cycle, and/or An enormous amount of logic. Instead, the floating-point pipeline will allow for a longer latency (more EX cycles than 1). Floating-point operations have the same pipeline stages as the integer instructions with the following differences: The EX cycle may be repeated as many times as needed (more than 1 cycle). There may be multiple floating-point functional units. A stall will occur if the instruction to be issued either causes a structural hazard for the functional unit or cause a data hazard. The latency of functional units is defined as the number of intervening cycles between an instruction producing the result and the instruction that uses the result (usually equals stall cycles with forwarding used). The initiation or repeat interval is the number of cycles that must elapse between issuing an instruction of a given type. (In Appendix A) to the same functional unit #53 Lec # 2 Fall 2014 8-27-2014 (Stall?)

Extending The MIPS Pipeline to Handle Floating-Point Operations: Adding Non-Pipelined Floating Point Units The MIPS pipeline with three additional unpipelined, floating-point functional units (FP FUs) (In Appendix A) #54 Lec # 2 Fall 2014 8-27-2014

Extending The MIPS Pipeline: Multiple Outstanding Floating Point Operations Latency = 6 Initiation Interval = 1 Pipelined Integer Unit Floating Point (FP)/Integer Multiply Latency = 0 Initiation Interval = 1 Hazards: RAW, WAW possible WAR Not Possible Structural: Possible Control: Possible IF ID EX MEM WB FP Adder Latency = 3 Initiation Interval = 1 Pipelined In-Order = Start of instruction execution done in program order FP/Integer Divider Super-pipelined CPU: A pipelined CPU with pipelined FP units Latency = 24 Initiation Interval = 25 Non-pipelined In-Order Single-Issue MIPS Pipeline with FP Support (In Appendix A) Pipelined CPU with pipelined FP units = Super-pipelined CPU #55 Lec # 2 Fall 2014 8-27-2014

Latencies and Initiation Intervals For Functional Units (FUs( FUs) Functional Unit Latency Initiation Interval Integer ALU 0 1 Data Memory 1 1 (Integer and FP Loads) FP add 3 1 FP multiply 6 1 (also integer multiply) FP divide 24 25 (also integer divide) Shown in last slide Latency usually equals stall cycles when full forwarding is used (In Appendix A) #56 Lec # 2 Fall 2014 8-27-2014

Pipeline Characteristics With FP Support Instructions are still processed in-order in IF, ID, EX at the rate of one instruction per cycle. Longer RAW hazard stalls likely due to long FP latencies. Structural hazards possible due to varying instruction times and FP latencies: FP unit may not be available (not pipelined?) ; divide in this case. MEM, WB reached by several instructions simultaneously. WAW hazards can occur since it is possible for instructions to reach WB out-of-order. WAR hazards impossible, since register reads occur inorder in ID. i.e Before a following instruction overwrites value Provided no WAW hazard results Instructions can be allowed to complete out-of-order requiring special measures to enforce precise exceptions. (In Appendix A) Order = Program order #57 Lec # 2 Fall 2014 8-27-2014

FP Operations Pipeline Timing Example FP Multiply = 7 EX cycles FP ADD = 4 EX Cycles CC 1 CC 2 CC 3 CC 4 CC 5 CC 6 CC 7 CC 8 CC 9 CC 10 CC 11 Program Order MUL.D IF ID M1 M2 M3 M4 M5 M6 M7 MEM WB ADD.D IF ID A1 A2 A3 A4 MEM WB L.D S.D IF ID EX MEM WB IF ID EX MEM WB Example illustrating that instructions can reach WB stage and Complete Out of order (i.e out of program order). Thus Write-After-Write (WAW) hazards can occur in this pipeline All above instructions are assumed independent Potential WAW Hazard Example (In Appendix A) When run on In-Order Single-Issue MIPS Pipeline with FP Support With FU latencies/initiation intervals given in slides 54-55 #58 Lec # 2 Fall 2014 8-27-2014

FP Code RAW Hazard Stalls Example (with full data forwarding in place) Program Order As indicated in slides 54-55: FP Multiply Functional Unit has 7 EX cycles (and 6 cycle latency 6 = 7-1) FP Add Functional Unit has 4 EX cycles (and 3 cycle latency 3 = 4-1) L.D F4, 0(R2) CC 1 CC 2 CC 3 CC 4 CC 5 CC 6 CC 7 CC 8 CC 9 CC 10 CC 11 CC12 CC13 CC14 CC15 CC16 CC17 CC18 IF ID EX MEM WB MUL.D F0, F4, F6 STALL IF ID M1 M2 M3 M4 M5 M6 M7 MEM WB ADD.D F2, F0, F8 STALL STALL STALL STALL STALL STALL STALL IF ID A1 A2 A3 A4 MEM WB S.D F2, 0(R2) IF STALL STALL STALL STALL STALL STALL STALL STALL STALL ID EX MEM WB 6 stall cycles which equals latency of FP multiply functional unit (In Appendix A) When run on In-Order Single-Issue MIPS Pipeline with FP Support With FP latencies/initiation intervals given in slides 54-55 Third stall due to structural hazard in MEM stage #59 Lec # 2 Fall 2014 8-27-2014

FP Code Structural Hazards Example CC 1 CC 2 CC 3 CC 4 CC 5 CC 6 CC 7 CC 8 CC 9 CC 10 CC 11 Program Order MULTD F0, F4, F6... (integer) IF ID M1 M2 M3 M4 M5 M6 M7 MEM WB IF ID EX MEM WB... (integer) IF ID EX MEM WB ADDD F2, F4, F6 IF ID A1 A2 A3 A4 MEM WB... (integer) IF ID EX MEM WB... (integer) IF ID EX MEM WB LD F2, 0(R2) IF ID EX MEM WB When run on In-Order Single-Issue MIPS Pipeline with FP Support With FP latencies/initiation intervals given in slides 54-55 #60 Lec # 2 Fall 2014 8-27-2014

Maintaining Precise Exceptions in Multicycle Pipelining In the MIPS code segment: DIV.D F0, F2, F4 ADD.D F10, F10, F8 Already Done SUB.D F12, F12, F14 The ADD.D, SUB.D instructions can complete before DIV.D is completed causing out-of-order execution completion. If DIV.D causes a floating-point arithmetic exception, precise exception handling is harder since both ADD.D, SUB.D have already completed. Four approaches have been proposed to remedy this type of situation: 1 Ignore the problem and settle for imprecise exception. 2 Buffer the results of the operation until all the operations issues earlier are done. (large buffers, multiplexers, comparators) e.g Stall WB 3 A history file keeps track of the original values of registers (CYBER180/190, VAX) Used to restore original register values if needed 4 A Future file keeps the newer value of a register; when all earlier instructions have completed the main register file is updated from the future file. On an exception the main register file has the precise values for the interrupted state. (In Appendix A) i.e. with FP support Exception Generated #61 Lec # 2 Fall 2014 8-27-2014 i.e Force in-order completion