MCU R&D Strategies for the Smart Society

MCU R&D Strategies for the Smart Society Renesas Electronics America Inc.

Renesas Technology & Solution Portfolio 2

Smart Society Paradigm From sporadic to CONTINUOUS measurement Energy is limited INFORMATION OVERLOAD is an opportunity for PATTERN RECOGNITION Soon the amount of data in the world will QUADRUPLE every day -IBM PRIVACY is the new ATOMIC BOMB More THINGS connected to the internet than PEOPLE REALTIME is the new PRIME TIME Source: The conversation prism by Brian Solis & LESS3 3

Data is the Key Between now and 2020, the amount of digital information created and replicated in the world will grow to an almost inconceivable 35 trillion gigabytes, as all major forms of media -voice, TV, radio, print -complete the journey from analog to digital This explosive growth means that by 2020, our Digital Universe will be 44 times as big as it was in 2009. -IDC data is the NEW OIL 4

Trends of CPU Performance MIPS 1000 100 10 25MHz 40MHz 80MHz 200MHz 32-bit Dual-core 1 0.1 8-bit 10MHz 16MHz 16/32-bit 0.01 2MHz 16-bit 1980 1990 2000 2010 Year 5

Trends of Embedded Memory Capacity MB 10 1 x8 0.1 x8 0.01 x8 1980 1990 2000 2010 Year 6

Agenda Renesas innovative Microcontroller Technologies Process technology Architecture (Performance and Power consumption) Innovative integration Summary & Q/A By the end of this session you will be able to: Understand the Renesas microcontroller technologies and solutions driving the smart society concept 7

Embedded Flash Technology Roadmap Memory Structure 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 NOR (Split-gate) NOR 130nm 50MHz NOR 40MHz 130nm Low power op. Low voltage Tech. ES Max. read freq. MP MONOS * RC03F (Former Renesas Tech.) MONOS 100MHz 90nm UX6LF (Former NECEL) Unified flash (RV40F) for RH850 & RX600 MONOS 120MHz 40nm * MONOS: Metal Oxide Nitride Oxide Silicon MONOS 100MHz 90nm Large capacity High speed Renesas MCUs are the first with 40 nm embedded flash! 8

World First 40nm Flash MCU Transistor / mm 2 40nm 320MHz CPU 120MHz Flash ~ 8MByte Lowest power consumption 55nm Other Option A 65nm Other Option B 90nm Previous generation 100 80 60 40 Technology node Leading Flash Process for Next Generation Automotive & Industrial 9

No. 1 MCU Supplier in the World Firmly maintained the world s No.1 MCU market share of 27% in CY2011 Dominant position in automotive MCU unchanged with the M US$ CY2011 Generalpurpose MCU * world s No.1 share 2,147 WW MCU #1 27% share 8-bit MCU #1: 17% share 16-bit MCU #1: 27% share 32-bit MCU #1: 38% share WW Automotive MCU #1 42% share Deepened relationships with carmakers Collaborating in BCP Automotive MCU 2,150 454 740 764 1,055 1,052 783 512 782 431 574 506 61 233 150 369 16 274 6 Renesas Freescale Infineon Atmel STMicro Microchip TI Samsung Fujitsu NXP *General-purpose MCU: MCUs for applications excluding automobiles Source: IHS isuppli, Annual 2011 Semiconductor Market Share 10

Microcontroller and Microprocessor Line-up 2010 2012 32-bit 1200 DMIPS, Superscalar Automotive & Industrial, 65nm 600µA/MHz, 1.5µA standby 500 DMIPS, Low Power Automotive & Industrial, 90nm 600µA/MHz, 1.5µA standby 1200 DMIPS, Performance Automotive, 40nm 500µA/MHz, 35µA deep standby 165 DMIPS, FPU, DSC Industrial, 90nm 500µA/MHz, 1.6µA deep standby 165 DMIPS, FPU, DSC Industrial, 40nm 200µA/MHz, 0.3µA deep standby 8/16-bit 25 DMIPS, Low Power Industrial & Automotive, 150nm 190µA/MHz, 0.3µA standby 10 DMIPS, Capacitive Touch Wide Industrial Format & LCDs Automotive, 130nm 350µA/MHz, 1µA standby 44 DMIPS, True Low Power Industrial & Automotive, 130nm 144µA/MHz, 0.2µA standby 11

Microcontroller and Microprocessor Line-up 2010 2012 32-bit 1200 DMIPS, Superscalar Automotive & Industrial, 65nm 600µA/MHz, 1.5µA standby 500 DMIPS, Low Power Automotive & Industrial, 90nm 600µA/MHz, 1.5µA standby 32-Bit High Performance, High Scalability & High Reliability 1200 DMIPS, Performance Automotive, 40nm 500µA/MHz, 35µA deep standby 165 DMIPS, FPU, DSC Industrial, 90nm 500µA/MHz, 1.6µA deep standby 165 DMIPS, FPU, DSC Industrial, 40nm 200µA/MHz, 0.3µA deep standby 8/16-bit 25 DMIPS, Low Power Industrial & Automotive, 150nm 190µA/MHz, 0.3µA standby 10 DMIPS, Capacitive Touch Wide Industrial Format & LCDs Automotive, 130nm 350µA/MHz, 1µA standby 44 DMIPS, True Low Power Industrial & Automotive, 130nm 144µA/MHz, 0.2µA standby 12

High-end, 32-bit CPU Roadmap Succession of V850 and SH Architecture V850E2M +MPU High Performance and Low power G3M +FPU(IEEE754-2008) +Branch prediction, +SIMD, +Multi-Core V850E1 * 5-stage V850E2 * 7-Stage * dual-issue V850E2R +FPU SH2A Good Performance and Low Power G3K * 5-stage SH2 E2S * 5-stage SH1 13

RH850 Architecture (Example CPU Core and Pipeline) Example RH850 CPU 96 MHz CPU Core 2.x DMIPS/MHz 5-STAGE PIPELINE Flash Memory TICK TICK TICK TICK TICK TICK TICK TICK TICK 32x 32bit General Purpose Registers Memory Protect Unit 32bit Floating Point Unit (Optional) 128 bit path Instruction F D E M W F D E F D F M E D F F W M E D D F W M E E D F W M M E D F W Q u e 1 Q u e 2 Inst Capable to Flash 120MHz Achieves : 32x32 +64 MAC, 64b Result One Clock-Per-Instruction (CPI) HARVARD ARCHITECTURE SRAM 32 x 32 DIV or MULT, 32bit or 64bit Result Interrupt Control On-Chip Debug 39 bit path Operand (Data) Data 5 STAGES OF PIPELINE F = FETCH INSTRUCTION D = DECODE INSTRUCTION E = EXECUTE INSTRUCTION M = READ OR WRITE MEMORY W = WRITE BACK TO REGISTER 14

RH850 Architecture System Interface PIPELINE Buffer 128b 128b instruction INST 64 bits RH850 MCU RH850 BUFFER 32b DATA Bus Master 32 bits Internal Main Bus 1/ System interconnect SRAM, 120MHz Access Flash Memory, 120MHz Access 32 bits Bus Bridge Bus Bridge DMAC (bus master) Peripheral Busses to Spread Bandwidth Loading Communication (CSI, CAN, SCI,LIN, I2C, Flex Ray) Timers (TAUA, TAU J, OST, CMT) Analog GPIO System Control (DMA, E2P, ICU, LVD, RTC, WDG, CLKS) 15

RH850: 40nm MCU Series for Vehicle Control High Mid Low Powertrain 320MHz Dual core w/ Lockstep I/O CPU 240MHz Dual core w/ls I/O processor 160MHz Single core w/ls EV/HEV 240MHz Dual core w/ LS 240MHz Single core w/ LS High Reliability Platform Chassis & Safety 240MHz Dual core w/ LS x2 240MHz Single core w/ LS 160MHz Single Core Air Bag 240MHz Single core w/ LS 120/160MHz Single core Low Power 80MHz Single Core Low Power Body 120MHz Multi Core Low Cyclic Power 120MHz Single Core Low Power 80MHz Single Core Low Power Low Power Platform 16

RH850/F1x Line-up RH850/F1U Triple-Core 160MHz 8MB 6MB RH850/F1H Dual Core 120MHz 4MB 3MB RH850/F1M Single core 120MHz 2MB 1.5MB RH850/F1L Single core 80MHz 1MB 768KB 512KB 384KB 256KB 48 64 80 100 144 176 208 272 357 QFP BGA 17

Microcontroller and Microprocessor Line-up 2010 2012 32-bit 1200 DMIPS, Superscalar Automotive & Industrial, 65nm 600µA/MHz, 1.5µA standby 500 DMIPS, Low Power 32-Bit High Performance DSP, FPU with High Integration 165 DMIPS, FPU, DSC Automotive & Industrial, 90nm 600µA/MHz, 1.5µA standby Industrial, 90nm 200µA/MHz, 0.3µA standby 1200 DMIPS, Performance Automotive, 40nm 500µA/MHz, 35µA deep standby 32-Bit High Efficiency Ultra Low Power and Low Voltage 165 DMIPS, FPU, DSC Industrial, 40nm 200µA/MHz, 0.3µA standby 8/16-bit 25 DMIPS, Low Power Industrial & Automotive, 150nm 190µA/MHz, 0.3µA standby 10 DMIPS, Capacitive Touch Wide Industrial Format & LCDs Automotive, 130nm 350µA/MHz, 1µA standby 44 DMIPS, True Low Power Industrial & Automotive, 130nm 144µA/MHz, 0.2µA standby 18

RX Architecture CPU Core and Pipeline RX600 CISC CPU 100MHz CPU Core 1.65 DMIPS/MHz 9 x 32bit Control Registers 16 x 32bit General Purpose Registers Memory Protect Unit 32bit Floating Point Unit 16x16 or 32x32 MAC, 48bit or 80bit Result 32 x 32 DIV or MULT, 32bit or 64bit Result Interrupt Control On-Chip Debug 64bit path Instruction 32bit path Operand (Data) TICK TICK 5-STAGE PIPELINE TICK E TICK TICK F D E M W F D E M F D E F D F TICK F W M E D TICK D F W M E E ENHANCED HARVARD ARCHITECTURE 5 STAGES OF PIPELINE F = FETCH INSTRUCTION D = DECODE INSTRUCTION E = EXECUTE INSTRUCTION M = READ OR WRITE MEMORY W = WRITE BACK TO REGISTER TICK E D F W M TICK M E D F W Achieves One Clock-Per-Instruction (CPI) PRE-FETCH QUEUE (PFQ) 64bits 64bits 64bits 64bits Holds 4 to 32 Instructions for Slower Memory WRITE BUFFER Buffer Only for Writes For Slow Memory Inst Data Typically Flash Memory 64 RX Flash is 10 nsec, or 100 MHz zero-wait Memory Interface RX SRAM is also 10 nsec 32 Typically SRAM 19

Advanced Bus Architecture for High Data Throughput 20

RX vs. M4: Performance, Power & Peripherals 21

RX vs. M4: Performance, Power & Peripherals 22

RX600 Series: High Performance Roadmap 100 MHz, Single Cycle Flash 90 nm Process Up to 120 MHz 40 nm Process 23

RX200 Series: Low Power Roadmap ELC RX210 Comparator 50MHz 128BK-512KB ELC RX210 Comparator 50MHz 64KB- 256KB ELC RX220 Comparator 32MHz 256KB ELC RX210 Comparator 50MHz 1MB ELC RX211 Comparator 50MHz USB AES RX211 24 bit ADC 50MHz 512KB 24

RX: Scalable Lineup 25

Next Generation RX 26

RX CPU Architecture Roadmap High Performance Low Power Small Code Size Higher Performance/MHz 4.0 Coremark/MHz 400MHz~ RX-v2 (240MHz~) Next RX-v1 (200MHz~) RX600, RX200, RX100 2.76 Coremark/MHz 0.68 Automark/MHz RX64x 3.30 Coremark/MHz 0.78 Automark/MHz Smaller gate count Smaller code size 2009 2012 2015 27

RX Family Roadmap: Next Generation RX100 32MHz Lowest Power 32-bit platform in the Industry RX200 50MHz Low power, Up to 1MB Flash, 1.62 to 5.5v, 24-bit ADC, Security RX600 100/120MHz Up to 4MB DSC, FPU, Connectivity RX700 240MHz Up to 8MB Dual Ethernet, DSP, LCD 28

Industry Leading Low Power 32-bit Platform 32-bit 32-bit Performance Integration Eco-System Higher power consumption 8/16-bit <1$ price point Lowest Power Fast wake up Analog integration Scalability RX-L (32-bit) 1.56 DMIPS/MHz performance 155uA/DMIPS in active & 0.1uA in standby <$1 price point RX scalability Similar eco-system 29

RX-L: Lowest Power 32-bit Family Best in class Performance Best in class Power efficiency RX-L 1.56DMIPS/MHz RX-L 155µA/DMIPS Cortex M4 1.25DMIPS/MHz Company B Cortex M0 200µA/DMIPS Cortex M3 1.25DMIPS/MHz Company A Cortex M3 300µA/DMIPS Cortex M0 0.9DMIPS/MHz 30

RX100: Unique Differentiators Lowest Power 32-bit MCU Lowest DC off set, lowest power at 1 MHz, faster wake up (<5us), <155uA/DMIPS active, 0.1uA standby Memory & Package 8KB to 2MB Flash memory, Smaller 3x3mm QFN/WPP package for space critical applications Innovative integration ELC, Asynchronous Timers to reduce power consumption Safety features IEC60730 are critical for medical and Industrial Flexibility of layout PMC to offer maximum number of I/O, Semi- programmability of I/Os and reduction of external noise circuitry Bridge between Digital and Analog world 12-bit, 24-bit A/Ds, 10-bit D/As, Op-Amps, Comparators, Temp sense, Capacitive touch etc. 31

RX700: 40nm, 240MHz Industrial Applications High Performance 120MHz/240Mhz operation with 120MHz single cycle Flash Innovative Integration 4MB Flash, 512KB RAM, IEE1588 Dual Ethernet, Trusted ELC, 2MSPS ADC, Data Capture Unit, SDIO, MMC etc. Safety Features IEC60730, AES security, CRC, DOC, CSD etc. Flexibility of layout PMC to offer maximum number of I/O, Semi-programmability of I/Os and reduction of external noise circuitry, Event Link Controller Flexible package size 64 pin to 256 pin package variants Bridge between digital and Analog world 12-bit, 24-bit A/Ds, 10-bit D/As, Op-Amps, Comparators, Temp sense, etc. 32

Microcontroller and Microprocessor Line-up 2010 2012 32-bit 1200 DMIPS, Superscalar Automotive & Industrial, 65nm 600µA/MHz, 1.5µA standby 500 DMIPS, Low Power Automotive & Industrial, 90nm 600µA/MHz, 1.5µA standby 8/16-Bit True Low Power High Efficiency & Integration 1200 DMIPS, Performance Automotive, 40nm 500µA/MHz, 35µA deep standby 165 DMIPS, FPU, DSC Industrial, 90nm 200µA/MHz, 0.3µA standby 165 DMIPS, FPU, DSC Industrial, 40nm 200µA/MHz, 0.3µA standby 8/16-bit 25 DMIPS, Low Power Industrial & Automotive, 150nm 190µA/MHz, 0.3µA standby 10 DMIPS, Capacitive Touch Wide Industrial Format & LCDs Automotive, 130nm 350µA/MHz, 1µA standby 44 DMIPS, True Low Power Industrial & Automotive, 130nm 144µA/MHz, 0.2µA standby 33

Low-end CPU Core Roadmap RL78 Renesas New Low end core performs up to 40.6DMIPS RL78/G14 core hits 44DMIPS with DSP instructions R8C Architecture R8C 10 DMIPS RL78 Architecture RL78/G14 core RL78 16bit, 44DMIPS 16bit, 40.6DMIPS MAC/MUL/DIV instructions 78K Architecture 78K0R 16bit, 31.2DMIPS Renesas New Low end core Compact 78K0 8bit, 2.9DMIPS 78K0S 8bit,1.1DMIPS 34

RL78 CPU Core Register Banks 0-3: 16-bit (Register Pair) MUL/MAC /DIV. ALU Bank 3 Bank 2 Bank 1 Bank 0 ES CS System Bus Interface Internal Buses Addr./ Data Bus Address Bus Control Signals 16-Bit Barrel Shifter Bit SP PC Interrupt Controller PSW RL78/G14 only 35

RL78 CPU Low Power Technique Automatically Adjusted Decode + Address operation MEM operation + Write Ex) 1byte : HL ADD 3-stage pipe line ADD A, [HL] - Instruction : - Address Operation - Data Operation : Selected Path Fetch ID MEM Fetch Instruction Decoder 1st- Byte 2nd- Byte Address Operator BR$ HL +Byte RAM Data Operator Add Bit Mul Write Current reduction! 25% 50% Decoder Operator Judge 1 or 2 instruction bytes 2nd-byte decoder turned on, only when the instruction is judged as 2 bytes instruction Only the operator which will be used in a instruction will be turned on. 66uA/MHz at basic operation (NOP) 36

Flash Operation Modes Flash modes realize an optimal power consumption HS (High-speed) mode: 32MHz (VDD = 2.7 to 5.5V) 16MHz (VDD = 2.4 to 5.5V) 2.1V (Active, Halt) & 1.8V(STOP) regulator LS (Low-speed) mode: 8MHz (VDD = 1.8 to 5.5V) 1.8V regulator LV (Low-voltage) mode: 4MHz (VDD = 1.6 to 5.5V) 1.8V regulator MCU current VDD VSS 1.7mA 1.7mA HS 8MHz 30% down 40% down 1.2mA LS 8MHz Regulator System Reg RL78 CPU, Peripherals 1.3mA HS 4MHz I/O Etc. 0.8mA LS 4MHz 1.2mA LV 4MHz 37

Active Current Advantage to Competition Typ. Value Max. Value Power Consumption [ma] 12 10 8 6 4 2 0 Competition RL78 0 10 20 30 12 RL78/G13 (VDD=2.0V/3.0V/5.0V) RL78/G13 10 (Basic Operation) A MCU-1 8 (VDD=3.6V) Power Consumption [ma] A MCU-1 (VDD=3V) 6 A MCU-1 (VDD=2.2V) 4 A MCU-2 (VDD=3.0V) A MCU-3 2 (VDD=3.0V) A MCU-3 (VDD=2.2V) 0 Competition RL78 0 10 20 30 RL78/G13 (VDD=2.0V/3.0V/5.0V) A MCU-1 (VDD=3.6V) A MCU-1 (VDD=3V) A MCU-1 (VDD=2.2V) A MCU-2 (VDD=3.0V) A MCU-3 (VDD=3.0V) A MCU-3 (VDD=2.2V) Operation Frequency [MHz] Operation Frequency [MHz] 38

Fast Wake-up is Good, but doesn t Always Have an Effect Fast wake-up is critical when active time is <30uS RL78 1.2mA 42 mausec 72 mausec 150 mausec Better - Assuming current consumption during wake up is the same as during the Active - Active mode: 8MHz, 3V A MCU-3 25usec 2.0mA 22 mausec 72 mausec 204 mausec No good 1usec Wake up time Active Time Condition 10usec 30usec 35usec 100usec Simple Monitoring - Simple Status check (1 ADC, Port check etc.) - Increment Standard Timer for Real Time Real Application functions - Glass Break detector :35usec - Smock detector : 400usec - Health care applications : msec to sec - Remote controller : 100msec - UART 1 byte @ 9600bps = 1.04 msec - EEPROM storage ; msec order 39

RL78: Roadmap Product Category SEG LCD ASSP GENERAL G13 (Standard) 20-128 pin, 16-512 KB F12 (Auto Body) I1A (Lighting) L12 (LCD Standard) 32-64 pin, 8-32 KB G14 (High Function) 30-100 pin, 16-256 KB G1A (Enhanced Analog) 25-64 pin, 16-64 KB D1x (Auto Dashboard) L1x (USB, Enhanced Analog) L1x (High Function) G12 (Lite) 20-30 pin, 2-16 KB G1x (Entry) Sub 20 pins G1x (USB) Metering RF4CE Capacitive Touch Schedule is preliminary and subject to change ~ CY 2012 CY 2013~ 40

Scalability: RL78 Line-up (Over 300 products from 2KB to 512KB of flash memory) 41

RL78: Next Generation Concept 42

SMART15 Concept Smart Power Smart Analog SMART Integration Asynchronous Architecture Intelligent connection between Analogto-Analog & Analog-to-Digital) SMART Data Transfer Controller SMART Snooze (in combination with more peripherals) 16/24-bit ADC & 12-bit DAC SMART integration: RF, Touch, Eink Display, BAN Intelligent-Wakeup (Quick wakeup + lowest current) Fast Comp, Op-Amps Super SAFE: DOC, CAC, MPU 43

RL78/SMART15: Roadmap Concept Next Generation Process Application Specific 130um process ASSP Lighting Remote WCP Meter sub Ghz RL78 HMI Core GP with LCD G15 GP-Next (20-100 pin) W/ Touch W/LCD General Purpose G12 G10 G13 G14 GP-L next 10-20-pin 44

Summary What should engineers care about? 45

Questions? 46

Enabling The Smart Society Challenge: Digital revolution is fuelling the exponential demand to manage the society more smarter and in a eco friendly way. Solution: In order to address the complex requirements of the Smart Society a scalable microcontroller portfolio which is supported by a rich eco system would be the most important selection criteria. 47

Renesas Electronics America Inc.