Keysight Technologies Understanding x1149 Integrity Test. Application Note

Keysight Technologies Understanding x1149 Integrity Test Application Note

Introduction This application note describes in detail what the Keysight x1149 Boundary Scan Analyzer performs during the Integrity test. In each new x1149 project, the x1149 test program generator will automatically generate a suite of tests called Infrastructure tests that consist of the following: Disable test Integrity test ID Code test User Code test BReg Length test The Infrastructure tests check on the fundamental functions of the TAP Register within the Boundary Scan device as well as along the boundary scan chains. This includes the basic functions of the TAP controller (a state machine) in the device, the connectivity of the TAP interface of each device in the chain to the board under test as well as the connectivity to the JTAG interface to the tester. When the Infrastructure tests pass, it means that the boundary scan devices on the chains are functioning correctly and are ready for the x1149 to execute boundary scan tests. When the Infrastructure tests fail, it may mean that there is a connectivity problem on the board, or that the boundary scan function on any of the device on the chain is not functioning as expected (according to the BSDL). Therefore, it is not necessary, in normal boundary scan test operation, to continue execution of the boundary scan tests when the Infrastructure tests fail, since the boundary scan test will also fail. This will save on test time by reducing the number of tests executed on defective boards. Executing the Infrastructure test is also a good debug tool to diagnose the defects found on the boundary scan chain pertaining to the JTAG interface. Each test step in the Infrastructure test isolates the basic functions of the TAP as well as each TAP pin (TCK, TMS, TDI, TDO). It is recommended to execute the Infrastructure tests at the beginning of the boundary test suite to ensure that the boundary scan chains are ready for testing. As a minimum, the Integrity and possibly, the BReg Length test should be executed. Feature Disable Integrity ID Code User Code BReg Length Description Table 1. x1149 Infrastructure Tests Puts all drivers of the boundary scan devices in the chain into tri-state mode (disabled) to allow other chains or device tests to occur without bus conflicts. Checks if the TDO and TDI signals have stuck-at 0 or 1 issue. It also checks the length of the chain and the length of the Instruction Register. Checks the content of the ID code registers of all devices in the chain. Checks the content of the User code registers of all devices in the chain. Checks the boundary register length for each device in the chain. This document will explain in detail what each step (or scan) within the Integrity is doing and how users can interpret the results. Users will be able to pinpoint the failing device and possible root causes of failure in order to perform the necessary remedy steps.

03 Keysight Understanding x1149 Integrity Test Application Note Contents 1.0 Introduction 3 1.1 Bravo board as a reference 4 1.2 BSDL file for 74bct8244 device (U1 & U2) 5 1.3 BSDL file for xc95144 device (U5) 6 1.4 16-States Diagram of TAP Controller 7 2.0 Integrity test 8 2.1 Start Sequence 9 2.2 TDO Wiggle 10 2.3 TDI Wiggle 13 2.4 IR_Scan & Chain Length 15 2.5 IR_Length 20 2.6 IR_Capture 22 2.7 End Sequence 24 3.0 Fault Simulation 25 3.1 TCK Open Fault 25 3.2 TMS Open Fault 27 3.3 TDI Open Fault 29 3.4 TDO Open Fault 31 3.5 J2 Open Fault (Broken Chain) 32 3.6 J3 Open Fault (Broken Chain) 35 4.0 Conclusion 37

04 Keysight Understanding x1149 Integrity Test Application Note 1.1 Bravo board as a reference In this document, we will be using a demo board called Bravo as a reference when describing how the Integrity test works on the x1149. The next few sections describe the boundary scan design on the Bravo board. X1149 Controller X1149 TAP/IO Port TD1 TCK TMS U1 (74bct8244) U2 (74bct8244) U5 (xc95144) TDO Figure 1. Boundary Scan block diagram of Bravo board On the Bravo board, there are 3 Boundary Scan devices configured as U1 U2 U5 in a chain. U1 and U2 are 74bct8244 (octal buffer with boundary scan capability) U5 is xc95144 (Xilinx CPLD) In the following sections, let s take a glimpse at the BSDL files of these devices to better understand the devices, as well as highlight the important information in the BSDL that are used to generate the Infrastructure tests

05 Keysight Understanding x1149 Integrity Test Application Note 1.2 BSDL file for 74bct8244 device (U1 & U2) In this document, we will be using a demo board called Bravo as a reference when describing how the Integrity test works on the x1149. The next few sections describe the boundary scan design on the Bravo board. Figure 2. 74bct8244 BSDL file Summary information: Instruction Length is 8 Instruction Capture is 1000 0001 Boundary Cell Length is 18

06 Keysight Understanding x1149 Integrity Test Application Note 1.3 BSDL file for xc95144 device (U5) Figure 3. xc95144 BSDL file

07 Keysight Understanding x1149 Integrity Test Application Note 1.4 16-States Diagram of TAP Controller 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select DR-Scan 1 Select IR-Scan 1 1 0 Capture-DR 0 1 0 Capture-IR 0 Shift-DR 1 Exit1-DR 1 0 Shift-IR 1 Exit1-IR 1 0 0 0 Pause-DR 0 Pause-IR 0 0 1 Exit2-DR 0 1 Exit2-IR 1 1 Update-DR 1 0 Update-IR 1 0 Figure 4. 16-States diagram of TAP Controller All boundary scan compliant devices have a state machine called a TAP controller built into it that is used to control the boundary scan execution on the device. The TAP controller is a 16-state machine controlled by the Test Mode Select (TMS) and Test Clock (TCK) inputs, which controls the flow of data bits to the Instruction Register (IR) and the Data Registers (DR). The TAP Controller can be thought of as the control centre of a boundary-scan device. The TAP Controller State Diagram, as shown in the figure above, allows you to track the sequence of any boundary-scan test through the TAP Controller. This state diagram applies to all components that comply with IEEE Standard 1149.1. Each position in the Data Register and Instruction Register columns represents a state of the TAP Controller. The states in the two columns vary only by the suffixes. These suffixes identify the column and the register operation that they affect. DR is the Data Registers column; data passed through this column affect the operation and contents of the data registers. All boundary-scan devices must contain the Boundary Register or Bypass Register; optional registers include IDCODE or USERCODE Registers as well as other design-specific registers that comply with the IEEE standard. IR is the Instruction Register column; instructions passed through this column affect the operation and contents of the Instruction Register, which is a mandatory component of every boundary-scan device. Along the data flow lines connecting each tap state, you see a number: a 0 or a 1. These numbers are the bit states of the TMS input signal required to move from one state to the next. The TMS bit is shifted through the state diagram at each period of the TCK.

08 Keysight Understanding x1149 Integrity Test Application Note 2.0 Integrity test Figure 5. Waveform viewer for Integrity test Following are the 6 scans within the Integrity test: 1. Tdo_Wiggle 2. Tdi_Wiggle 3. IR_Scan 4. Chain_Length 5. IR_Length 6. IR_Capture Figure 6. Oscilloscope capture for Integrity test The actual signals on TCK, TMS, TDI & TDO are captured by an oscilloscope, as shown above, during an Integrity test. The 6 scans within the Integrity test is bordered by Start and End Sequences.

09 Keysight Understanding x1149 Integrity Test Application Note 2.1 Start Sequence Figure 7. Scope capture on Start sequence In the Start sequence, the x1149 will first clock 5 TCK cycles with TMS held High 1. This will force the TAP Controller back to Test-Logic-Reset state (refer to 16-States Diagram of TAP Controller) regardless which state it is in ensuring that subsequent test steps start from a known state. The x1149 will then clock another TCK cycle with TMS held Low 0. This sets the TAP Controller in Run-Test-Idle state.

10 Keysight Understanding x1149 Integrity Test Application Note 2.2 TDO Wiggle Figure 8. Tdo_Wiggle on Waveform Viewer The above figure is taken from the Waveform Viewer on the x1149 application. It shows the execution of the Tdo_Wiggle scan, which is Scan #0 of the Integrity test. In this view, the first bit starts at the right of the screen, instead of from the left as in the oscilloscope waveform capture. The purpose of the Tdo_Wiggle scan is to check that the TDO signal is able to toggle high and low. This ensures no opens or shorts at TDO. Since the IEEE1149.1 standard dictates that the least 2 significant bits of the Instruction Capture register is fixed at 01 binary, we are using this known condition in the Tdo_Wiggle scan. When we shift the default bits in the Instruction Capture of the last device in the chain through TDO, and detect 01 at TDO, while ignoring the rest of the instructions, we know that TDO is able to toggle high and low.

11 Keysight Understanding x1149 Integrity Test Application Note Figure 9. Tdo_Wiggle scope capture Let s see what it looks like with TCK and TMS signals added. For this, please refer to the oscilloscope waveform capture. Here, you can see, from the TCK and TMS signals, that the TAP Controller will switch to the Shift-IR state, then to the Exit-IR, then to Update-IR and finally back to Run-Test-Idle state. For each scan of the Integrity test, the x1149 software will automatically move the TAP Controller back to Run-Test-Idle state at the end of the scan. Let s view the Shift-IR scan in more detail below.

12 Keysight Understanding x1149 Integrity Test Application Note Figure 10. Tdo_Wiggle scope capture (zoom-in) A total of 24 cycles of 1 s will be clocked into the chain. This is because the total length of the Instruction Capture registers for the 3 devices in the chain is 24 bits (8 + 8 + 8). So, we need 24 cycles of TCK to clock all the instructions out of the registers. The x1149 will look for the first 2 bits coming out from TDO, which are the least 2 significant bits ( 01 binary) of Instruction Capture register of the last boundary scan device (U5) in the chain. Remember that the first bit on the oscilloscope waveform starts from the left instead of from the right as in the waveform in the Waveform Viewer of the x1149 software. Apart from ensuring that the TDO is able to toggle between high and low signals, this scan also checks that the TAP controllers in each device are able to step through the 16 states correctly using TCK and TMS. Therefore, no shorts or opens faults are expected on TDO as well as TCK and TMS.

13 Keysight Understanding x1149 Integrity Test Application Note 2.3 TDI Wiggle Figure 11. Tdi_Wiggle on Waveform Viewer The purpose of Tdi_Wiggle scan (Scan #1) is to check that the TDI signal is able to toggle high and low. This ensures no opens at TDI. To do this, we shift in, via TDI, a series of fixed test patterns of 0 s and 1 s into the instruction registers. Then shift the instructions out through TDO to check that they are 0 s and 1 s according to how we input them. This is shown in the waveform capture taken from the x1149 software. You can see in TDI that we are inputting 0 s followed by 1 s, from the left to the right of the waveform. At the TDO output, we should see similar 0 s and 1 s but offset by 1 set of data from the TDI. Figure 12. Tdi_Wiggle scope capture Here is the TDI-Wiggle as captured from the oscilloscope. We have added TCK and TMS for more clarity. The waveform capture shows the full execution of the test. From the previous Tdo_Wiggle scan (Scan #0), the TAP Controller is at Run-Test-Idle state. In the Tdi_Wiggle scan, the TAP Controller will transition to Shift-IR state, followed by 3 sets of instruction bits of 0 s, 0 s & 1 s, then to Exit-IR, then to Update-IR and finally back to Run-Test- Idle state.

14 Keysight Understanding x1149 Integrity Test Application Note Figure 13. Tdi_Wiggle scope capture (zoom-in) First, we shift in a set of 0 s, to fill up the instruction registers in the chain. Then, we shift in a set of 1 s to replace all the bits in the instruction registers with 1 s. This pushes the first set of 0 s to TDO in order for us to check the data. Following which, we shift in a second and final set of 1 s in order to push the first set of 1 s to TDO in order for us to check the data. When we correctly detect both 0 s and 1 s at the TDO, this shows that TDI is able to input the data as expected, so there are no opens at TDI. The number of bits that we shift in for each set is equal to the total length of the Instruction Registers in the entire Boundary Scan Chain. On the Bravo board, the total length of the Instruction Registers in the chain is 24bits (U1=8 bits, U2=8 bits, U5=8 bits).

15 Keysight Understanding x1149 Integrity Test Application Note 2.4 IR_Scan & Chain Length Figure 14. IR_Scan on Waveform Viewer Figure 15. Chain_Length on Waveform Viewer The next 2 scans in the Integrity test suite are the IR_Scan and Chain_Length scans (Scan #2 and Scan #3). Together, they check for the correct number of boundary scan devices in the chain. The IR_Scan scan puts all Boundary Scan devices in the chain in Bypass mode, so that we can count the number of devices in the chains by the number of Bypass bits seen at TDO. The Chain-length scan shifts in a known test pattern immediately after the Bypass bits so that we are sure which is the last Bypass bit seen at TDO. The above waveform capture from the x1149 Waveform Viewer shows, from the right, on the Bravo board the TD0 output 3 Bypass bits followed immediately by 1234.

16 Keysight Understanding x1149 Integrity Test Application Note Figure 16. IR_Scan & Chain_Length scope capture Here are both the IR_Scan and Chain_Length scans on the Bravo board captured from the oscilloscope Figure 17. IR_Scan scope capture When we zoom into the IR_Scan, you will see that the TAP Controller will transit to Shift-IR state, clock in the instruction opcode for BYPASS to place all Boundary Scan devices in the chain in Bypass mode, then to Update-IR and finally back to Run-Test-Idle state.

17 Keysight Understanding x1149 Integrity Test Application Note Figure 18. Zoom-in view of IR_Scan scope capture To put the 3 devices in the chain in Bypass mode, the BYPASS opcode will be shifted into the all of the instruction registers. Remembering that the Instructure Register length of all the devices in the chain is 24 bits (U1=8 bits, U2=8 bits, U5=8 bits), we will clock 24 1 s in, since the BYPASS opcodes are all 1 s, by default, according to the IEEE 1149.1 standard. This allows us to check whether the chain on the Bravo board has 3 devices as expected, and will flag a failure when there are less devices. To cater for the event when there are more than 3 devices, we shift another 24 bits of 1 s into the chain, so that any additional devices will also be put into Bypass mode and output the respective Bypass bit at TDO for us to check.

18 Keysight Understanding x1149 Integrity Test Application Note Figure 19. Chain_Length scope capture In the Chain_Length scan, the TAP Controller will transit to Shift-DR state, clock in the fixed test pattern 1234 hex value, then to Exit-DR, then to Pause-DR, then to Update-IR and finally back to Run-Test-Idle state. Let s zoom in deeper to look at the TDI and TDO bits in more detail in the next figure.

19 Keysight Understanding x1149 Integrity Test Application Note Figure 20. Chain_Length scope capture (zoom-in) As the Chain_Length scan starts shifting in the 1234 test pattern into the chain via TDI, TDO starts to first output the 3 Bypass bits. This is followed immediately with the 1234 pattern that is shifted in. It is expected to see only 3 Bypass bits, because the Bravo board only has 3 devices in the chain. In event of a fault condition where there are only 2 devices in the chain, the TDO will only see 2 Bypass bits followed by 1234. In a fault condition when there are 4 devices in the chain, since we shifted in a double instruction register width of 1 s during the IR_Scan stage, the extra device would also be put in Bypass mode and this we would see 4 Bypass bits at TDO instead of just 3. In order to clock out both the Bypass bits and the 1234 test pattern, TCK needs to clock a total of 19 cycles; 3 Bypass bits and 16 bits from 1234 test pattern. After shifting in the 16-bit 1234 test pattern, TDI will add 3 more bits of 1 s, to make a total of 19 bits. This is how the IR_Scan and Chain_Length scans check the number of devices on the chain. In this process, the data registers are also checked.

20 Keysight Understanding x1149 Integrity Test Application Note 2.5 IR_Length Figure 21. IR_Length on Waveform Viewer The purpose of the IR_Length scan is to check for the correct total length of the Instruction Register of all the boundary scan devices in the chain. This is done by shifting into the Instruction registers a known pattern, a set of 0 s, followed by another set of known pattern, a set of 1 s. The test is passed when the transition between the 2 patterns is detected at the right location as the data is output to TDO. The transition at the correct position indicates the correct length of the instruction register. In the figure above, you can see the transition from 0 to 1 on TDO, in the waveform captured from x1149 s Waveform Viewer. If the location of the 0 to 1 transition is at the correct position, it means that the total length of the instruction registers in the chain are expected, if the transition occurs earlier, it means that the total length of the instruction registers is shorter than expected. If the transition occurs later, it means that the total length of the instruction registers is longer than expected. To check if the Instruction Register length is longer than expected, we clock 2 sets of 0 s and 1 s, so that we can detect the late positon of the transition from 0 to 1 when the total length of the instruction registers is longer than expected.

21 Keysight Understanding x1149 Integrity Test Application Note Figure 22. IR_Length scope capture Let s illustrate this using the Bravo board. The total length of the instruction registers in the chain is 24 bits (8 + 8 + 8) for the 3 devices on the chain. In the Shift-IR state, we first shift in 24 bits of 0 s. This action will shift the default Instructions (INSTRUCTION_CAPTURE) out of TDO, which we can observe. In the IR_Length scan, this output is ignored. The next set of 24 bits of 0 s is then shifted into the instruction registers. This time, we would see the first set of 0 s output through TDO. This is where the test starts tracking TDO. Next, a set of 24 bits of 1 s is shifted into the instruction registers. This will shift the second set of 0 s out of TDO. If the instruction register length is as expected, we should see a full set of 24 bits of 0 s output at TDO. If the instruction register length is shorter than expected, we should less than 24 bits of 0 s output at TDO. Finally, the last set of 24 bits of 1 s is shifted into the instruction registers. This will shift the first set of 1 s out of TDO. If the instruction register length is longer than expected, we should see a number of 0 s followed by 1 s output through TDO. Shifting in redundant bits in the test allows us to check for all faults on the instruction register length.

22 Keysight Understanding x1149 Integrity Test Application Note 2.6 IR_Capture Figure 23. IR_Capture on Waveform Viewer The IR_Capture scan is the final check in the Integrity test suite. This scan checks that the default INSTRUCTION_CAPTURE opcode can be read correctly be each device individually. This check provides future diagnostics when devices within the chain are failing. This is especially useful for long chains. It pinpoints which device within the chain is having problems entering into boundary scan mode, since the TAP controller is unable to step through the states to clock out the INSTRUCTION_CAPTURE instruction bits. To do this, the IR_Capture scan shifts in the IDCODE opcode or the BYPASS opcode, if the IDCODE opcode is not available for that device, and checks that the expected INSTRUCTION_ CAPTURE instruction bits appear at TDO when they are clocked out.

23 Keysight Understanding x1149 Integrity Test Application Note Figure 24. IR_Capture scope capture In this case of Bravo board, U1 & U2 (74bct8244 Octal Buffer) do not have IDCODE opcodes. Hence, the BYPASS opcode are used for U1 & U2 while the IDCODE opcode is used for U5 (xc95144 Xilinx CPLD). Once entered into the Shift-IR state, the x1149 will start shifting in the IDCODE and BYPASS opcodes for the devices in the chain. At the same time, the x1149 will be checking the TDO; expecting the values of the INSTRUCTION_CAPTURE instruction bits of the devices. The expected INSTRUCTION_CAPTURE bits as defined in the BSDL files: U5 U1 & U2

24 Keysight Understanding x1149 Integrity Test Application Note 2.7 End Sequence Figure 25. End sequence scope capture The Integrity Test suite ends with the End Sequence. This is 3 TCK clock cycles with TMS held High 1. Since each scan ends at Run-Test-Idle state, this effectively brings the TAP state to the Test-Logic-Reset state, ending the test in a known reset state.

25 Keysight Understanding x1149 Integrity Test Application Note 3.0 Fault Simulation This section of the document describes several different fault scenarios and their corresponding Integrity test failures, using the Bravo board. From these fault injection scenarios, the user can appreciate the various faults that the Integrity Test is capable of diagnosing. For ease of understanding, each scenario below is based on single faults not from multiple faults. The symptoms from multiple fault scenarios would be the combination of the single fault scenarios. 3.1 TCK Open Fault X1149 Controller X1149 TAP/IO Port TD1 TCK TMS U1 (74bct8244) U2 (74bct8244) U5 (xc95144) TDO Open fault on TCK Figure 26. Open fault on TCK Let us consider an open fault on the TCK signal. What failures and how many failures will you expect if Integrity test is run?

26 Keysight Understanding x1149 Integrity Test Application Note Figure 27. Repair Ticket for open fault on TCK With an open fault on TCK signal, nothing can be clocked into the chain. Hence, you will expect all scans (Tdo_Wiggle, Tdi_Wiggle, IR_Scan & Chain_Length, IR_Length and IR_Capture) to fail. The above Repair Ticket shows the Integrity test failure with an open fault on TCK signal. Notice that x1149 software will separate the IR_Capture scan failures for each of the boundary scan devices in the chain. In this case for Bravo board, as indicated in the failure ticket, failure # 5 of 7 is for : U5 failure # 6 of 7 is for : U2 failure # 7 of 7 is for : U1

27 Keysight Understanding x1149 Integrity Test Application Note 3.2 TMS Open Fault X1149 Controller X1149 TAP/IO Port TD1 TCK TMS U1 (74bct8244) U2 (74bct8244) U5 (xc95144) TDO Open fault on TMS Figure 28. Open fault on TMS Let us consider an open fault on the TMS signal. With reference from previous Repair Ticket information (based on open fault on TCK signal), what failures and how many failures will you expect if Integrity test is run?

28 Keysight Understanding x1149 Integrity Test Application Note Figure 29. Repair Ticket for open fault on TMS With an open fault on TMS signal, the TAP Controller will not be able to transit correctly throughout the different states. Again, you will expect all scans (Tdo_Wiggle, Tdi_Wiggle, IR_Scan & Chain_Length, IR_Length and IR_Capture) to fail. The above Repair Ticket shows the Integrity test failure with an open fault on TMS signal. In most cases TMS pin is pulled up via a resistor. In this case, the TMS will always be held high. This will result in the TAP controller not being able to transit into the proper states as required by the Integrity tests, thus the tests will also fail.

29 Keysight Understanding x1149 Integrity Test Application Note 3.3 TDI Open Fault Open fault on TDI X1149 Controller X1149 TAP/IO Port TD1 TCK TMS U1 (74bct8244) U2 (74bct8244) U5 (xc95144) TDO Figure 30. Open fault on TDI Let us consider an open fault on the TDI signal (TDI of the 1st boundary scan device in the chain). What and how many failures will you expect if Integrity test is run? Figure 31. Repair Ticket for open fault on TDI

30 Keysight Understanding x1149 Integrity Test Application Note Did you manage to answer correctly? Only 3 failures occur when Integrity test is run. 1. Tdi_Wiggle 2. Chain_Length 3. IR_Length Tdo_Wiggle and IR_Capture scans will pass with an open fault on TDI signal. Explanation: TDI signal is usually pulled up on the board or in the device. In event that it is not pulled up (very uncommon), or floating, an unknown state of either a 1 or a 0 can be registered at TDI in every TCK clock. For the Tdo_Wiggle scan, as long as the TCK and TMS signals are driven properly, the least 2 significant bits, 01, of the INSTRUCTION_CAPTURE value of the last boundary scan device (U5, in the case of the Bravo board) will be clocked out correctly. Hence, Tdo_Wiggle scan will pass, since TDI does not affect the outcome of the scan. For the Tdi_Wiggle scan, with an open fault on TDI, the necessary stream of 0 s and 1 s bits cannot be driven into the boundary scan chain, resulting in mismatch on the expected TDO. Hence, a failure. For the case of the Bravo board, since the TDI is pull high, the output of TDO is also always high. For the Chain_Length scan, since TDI is pulled high, all 1 s are driven into the instruction register. This coincides with the BYPASS opcode and will be placed in devices in Bypass mode. But, the test pattern of 1234 hex value will not propagate through correctly. Hence, the failure ticket shows a failure at the 1234 hex value but not the 3 Bypass bits. For the IR_Length scan, with an open fault on TDI, the necessary stream of 0 s and 1 s bits again cannot be driven into the chain, resulting in mismatch on the expected TDO. Hence, a failure. For the IR_Capture scan, similar to the Tdo_Wiggle scan explanation, as long as the TCK and TMS signals are driven properly, the content of all INSTRUCTION_CAPTURE registers will still be clocked out correctly. Hence, IR_Capture scans for all devices will pass.

31 Keysight Understanding x1149 Integrity Test Application Note 3.4 TDO Open Fault X1149 Controller X1149 TAP/IO Port TD1 TCK TMS U1 (74bct8244) U2 (74bct8244) U5 (xc95144) TDO Open fault on TDO Figure 32. Open fault on TDO Let us consider an open fault on the TDO signal (TDO of the last boundary scan device in the chain). What and how many failures will you expect if Integrity test is run? Figure 33. Repair Ticket for open fault on TDO With an open fault on TDO signal, the TDO will either stuck high or low. Hence, one will expect all scans (Tdo_Wiggle, Tdi_Wiggle, IR_Scan & Chain_Length, IR_Length and IR_Capture) to fail.

32 Keysight Understanding x1149 Integrity Test Application Note 3.5 J2 Open Fault (Broken Chain) X1149 Controller X1149 TAP/IO Port TD1 TCK TMS U1 (74bct8244) U2 (74bct8244) U5 (xc95144) TDO Figure 34. Broken chain between U1 & U2 There is a Jumper J2 on Bravo board which connects U1-TDO to U2-TDI. The Jumper J2 can be removed to simulated a broken boundary scan chain between U1 & U2. Now, let us consider a broken chain between U1 & U2 as shown in above diagram. What and how many failures will you expect if Integrity test is run?

33 Keysight Understanding x1149 Integrity Test Application Note Figure 35. Repair Ticket for broken chain between U1 & U2 Notice that Tdo_Wiggle passes. Chain Length scan detects 2 devices. IR_Capture detects failure on U1. IR_Capture passes for U2 and U5.

34 Keysight Understanding x1149 Integrity Test Application Note Did you manage to answer correctly? There are only 4 failures when Integrity test is run. 1. Tdi_Wiggle 2. Chain_Length 3. IR_Length 4. IR_Capture (for U1) Tdo_Wiggle and IR_Capture (for U2 & U5) scans will pass in this scenario. Explanation: The open fault lies between U1-TDO and U2-TDI. Hence, U1 is unable to propagate any signal to U2 and U5. For the Tdo_Wiggle scan, the TCK and TMS signals are driven properly to U5, the content of the INSTRUCTION_CAPTURE register value of U5 will be clocked out correctly. Hence, Tdo_Wiggle scan passes. For the Tdi_Wiggle scan, with an open fault between U1-TDO and U2-TDI, the necessary stream of 0 s and 1 s bits are unable to clock through to U2 & U5, resulting in mismatch on the expected TDO. Hence, a failure. For the Chain_Length scan, U1 will register the BYPASS opcode from the chain TDI. With a floating U2-TDI, U2 and U5 continue to register all 1 s input (due to the internal pullup in U2). This coincides with the BYPASS opcode and they will be placed in Bypass mode. However, the fixed test pattern of 1234 hex value will not propagate correctly through to U2 & U5. The Bypass bit 0 of U1 is also unable to propagate through U2 and U5 to chain TDO. Hence, only the 2 Bypass bits (from U2 & U5) are correctly detected, but not the expected Bypass bit 0 from U1, and the expected 1234 hex test pattern fails on all devices. For the IR_Length scan, with an open fault between U1-TDO and U2-TDI, the necessary stream of 0 s and 1 s bits are unable to clock through to U2 & U5, resulting in mismatch on the expected TDO. Hence, a failure. For the IR_Capture scan, the content of INSTRUCTION_CAPTURE register of U1 is unable to propagate through U2 & U5 to chain TDO. The x1149 software is able to clock out content from U2 & U5 and pass them, but will fail on U1. From the above Repair Ticket, the fault clearly lies between U1-TDO to U2-TDI or U1 boundary scan device cannot enter Boundary Scan mode.

35 Keysight Understanding x1149 Integrity Test Application Note 3.6 J3 Open Fault (Broken Chain) X1149 Controller X1149 TAP/IO Port TD1 TCK TMS U1 (74bct8244) U2 (74bct8244) U5 (xc95144) TDO Figure 36. Broken chain between U2 & U5 There is a Jumper J3 on Bravo board which connects U1-TDO to U2-TDI. The Jumper J3 can be removed to simulated a broken boundary scan chain between U2 & U5. Now, let us consider a broken chain between U2 & U5 as shown in above diagram. What failures and how many failures will you expect if Integrity test is run?

36 Keysight Understanding x1149 Integrity Test Application Note Figure 37. Repair Ticket for broken chain between U2 & U5 Notice that Tdo_Wiggle passes. Chain Length scan detects 1 device. IR_Capture detects failure on U1 and U2. IR_Capture passes for U5. Did you manage to answer correctly? There are only 5 failures when Integrity test is run. 1. Tdi_Wiggle 2. Chain_Length 3. IR_Length 4. IR_Capture (for U1) 5. IR_Capture (for U2) Tdo_Wiggle and IR_Capture (for U5) scans will pass in this scenario.

37 Keysight Understanding x1149 Integrity Test Application Note Explanation: The open fault lies between U2-TDO and U5-TDI. Meaning U1 and U2 are unable to propagate any data to U5. For the Tdo_Wiggle scan, the TCK and TMS signals are driven properly to U5, the content of the INSTRUCTION_CAPTURE register value of U5 will be clocked out correctly. Hence, Tdo_Wiggle scan passes. For the Tdi_Wiggle scan, with an open fault between U2-TDO and U5-TDI, the necessary stream of 0 s and 1 s bits are unable to clock through to U5, resulting in mismatch on the expected TDO. Hence, a failure. For the Chain_Length scan, U1 and U2 will correctly register the BYPASS opcode from TDI, but since there is an open between U2-TDO and U5-TDI, the Bypass bit does not get propagated to TDO. U5 will register all 1 s at TDI, due to internal pullup in U5, and that coincides with the BYPASS opcode and will be placed in Bypass mode. However, since there is an open between U2-TDO and U5-TDI, the fixed test pattern of 1234 hex value will not propagate correctly through to U5. The Bypass bit 0 of U1 and U2 are also unable to propagate through U5 to chain TDO. Hence, only the 1 Bypass bit (from U5) is detected, so, only one device is detected in the chain. The expected 1234 hex test pattern also fails. For the IR_Length scan, with an open fault between U2-TDO and U5-TDI, the necessary stream of 0 s and 1 s bits are unable to clock through to U5, resulting in mismatch on the expected TDO. Hence, a failure. For the IR_Capture scan, the content of INSTRUCTION_CAPTURE registers of U1 & U2 are unable to propagate through U5 to chain TDO. The x1149 software is able to clock out content from U5 and pass it, but will fail on U1 & U2. From the above Repair Ticket, the fault clearly lies between U2-TDO and U5-TDI or U2 boundary scan device cannot enter boundary scan mode. 4.0 Conclusion Integrity test is part of the Infrastructure tests generated by the x1149 software. You should always ensure that the Infrastructure tests are passed before moving on to execute or debug the other boundary scan tests such as Interconnect, Interconnect_Dot6, Pullup_Pulldown, Silicon Nail tests. With the Integrity test being executed first for any boundary scan chain test, it will filter any fundamental boundary scan failure associated with the boundary scan chain. Integrity test checks for shorts or opens faults on JTAG signals, the number of boundary scan devices in the chain, the length of INSTRUCTION_CAPTURE registers and whether each boundary scan device is able to enter Boundary Scan mode. When a fault occurs, the detailed information on the Repair Ticket, allows you to diagnose and pinpoint on the root causes of failure, to which JTAG pin is at fault. This is especially helpful in cases of long chain with multiple boundary scan devices.

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