Chapter 4 Computer Architecture
Figure 4.1 Input device Central processing unit Main memory Output device Bus Data flow Control
Figure 4.2 Central processing unit () Status bits ( ) Accumulator ( ) Index register ( ) Program counter ( ) Stack pointer ( ) Instruction register ( )
Figure 4.3 Main memory 0000 0001 0002 0003 0004 0005. 0006 FFFE FFFF
Figure 4.4 Main memory 0000 0003 0004 0007 000A 000B 000D..
Figure 4.5 0 0 0 0 0 0 1 0 000B 1 1 0 1 0 0 0 1 000C (a) The content in binary. 02 D1 000B 000C (b) The content in hexadecimal. 000B 02D1 (c) The content in a machine language listing.
Figure 4.6 Instruction Specifier Instruction 0000 0000 Stop execution 0000 0001 Return from trap 0000 0010 Move stack pointer (SP) to accumulator (A) 0000 0011 Move NZVC flags to accumulator (A) 0000 010a Branch unconditional 0000 011a Branch if less than or equal to 0000 100a Branch if less than 0000 101a Branch if equal to 0000 110a Branch if not equal to 0000 111a Branch if greater than or equal to 0001 000a Branch if greater than 0001 001a Branch if V 0001 010a Branch if C 0001 011a Call subroutine
Figure 4.6 (Continued) 0001 100r Bitwise invert register r 0001 101r Negate register r 0001 110r Arithmetic shift left register r 0001 111r Arithmetic shift right register r 0010 000r Rotate left register r 0010 001r Rotate right register r 0010 01n Unimplemented opcode, unary trap 0010 1aaa Unimplemented opcode, nonunary trap 0011 0aaa Unimplemented opcode, nonunary trap 0011 1aaa Unimplemented opcode, nonunary trap 0100 0aaa Unimplemented opcode, nonunary trap 0100 1aaa Character input 0101 0aaa Character output 0101 1nn Return from call with n local bytes
Figure 4.6 (Continued) 0110 0aaa Add to stack pointer (SP) 0110 1aaa Subtract from stack pointer (SP) 0111 raaa Add to register r 1000 raaa Subtract from register r 1001 raaa Bitwise AND to register r 1010 raaa Bitwise OR to register r 1011 raaa Compare register r 1100 raaa Load register r from memory 1101 raaa Load byte register r from memory 1110 raaa Store register r to memory 1111 raaa Store byte register r to memory
Figure 4.7 Instruction specifier Operand specifier (a) The two parts of a nonunary instruction Instruction specifier (b) A unary instruction
Figure 4.8 aaa 000 001 010 011 100 101 110 111 Addressing mode Immediate Direct Indirect Stack-relative Stack-relative deferred Indexed Stack-indexed Stack-indexed deferred (a) The addressing-aaa field.
Figure 4.8 (Continued) a Addressing mode r Register 0 1 Immediate Indexed 0 1 Accumulator, A Index register, X (b) The addressing-a field. (c) The register-r field.
Figure 4.9 Main memory 10001101 01A3 00011110 01A6 00000011 01A4 010011 10 01A5
The stop instruction Instruction specifier: 0000 0000 Causes the computer to stop
The load instruction Instruction specifier: 1100 raaa Loads one word (two bytes) from memory to register r r Oprnd ; N r < 0, Z r = 0
Figure 4.10, 4.11 Instruction specifier Opcode r aaa Operand specifier 1 1 0 0 0 0 0 1 C 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 4 A NZ A 036D 92EF C1004A NZ 10 004A Load accumulator A 92EF 92EF 004A (a) Before (b) After
The store instruction Instruction specifier: 1110 raaa Stores one word (two bytes) from register r to memory Oprnd r
Figure 4.12, 4.13 Instruction specifier Opcode r aaa Operand specifier 1 1 1 0 1 0 0 1 E 9 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 4 A X 16BC F082 E9004A X 16BC 004A Store index register 16BC 004A (a) Before (b) After
The add instruction Instruction specifier: 0111 raaa Adds one word (two bytes) from memory to register r r r + Oprnd ; N r < 0, Z r = 0, V {overflow}, C {carry}
Figure 4.14, 4.15 Instruction specifier Opcode r aaa Operand specifier 0 1 1 1 1 0 0 1 7 9 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 4 A NZVC X 0005 FFF9 004A 79004A Add index register NZVC 1000 X FFFE FFF9 004A (a) Before (b) After
The subtract instruction Instruction specifier: 1000 raaa Subtracts one word (two bytes) from memory from register r r r Oprnd ; N r < 0, Z r = 0, V {overflow}, C {carry}
Figure 4.16, 4.17 Instruction specifier Opcode r aaa Operand specifier 1 0 0 0 0 0 0 1 8 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 4 A NZVC A 0003 0009 004A 81004A Subtract accumulator NZVC 1000 A FFF4 FFFA 0009 004A (a) Before (b) After
The and instruction Instruction specifier: 1001 raaa ANDs one word (two bytes) from memory to register r r r Oprnd ; N r < 0, Z r = 0
Figure 4.18, 4.19 Instruction specifier Opcode r aaa 1 0 0 1 1 0 0 1 9 9 Operand specifier 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 4 A NZ X 5DC3 00FF 004A 99004A Add And index register NZ 00 X 00C3 00FF 004A (a) Before (b) After
The or instruction Instruction specifier: 1010 raaa ORs one word (two bytes) from memory to register r r r Oprnd ; N r < 0, Z r = 0
Figure 4.20 NZ X 5DC3 00FF 004A A9004A Or index register NZ 00 X 5DFF 00FF 004A (a) Before (b) After
The not instruction Instruction specifier: 0001 100r Bit-wise NOT operation on register r Each 0 changed to 1, each 1 changed to 0 r r ; N r < 0, Z r = 0
Figure 4.21, 4.22 Instruction specifier Opcode r 0 0 0 1 1 0 0 0 1 8 NZ AX 0003 18 Not accumulator NZ 10 XA FFFC (a) Before (b) After
The negate instruction Instruction specifier: 0001 101r Negate (take two s complement of) register r r r ; N r < 0, Z r = 0
Figure 4.23 NZ A X 0003 1A Negate accumulator NZ 10 A X FFFD (a) Before (b) After
The load byte instruction Instruction specifier: 1101 raaa Loads one byte from memory to the right half of register r r 8..15 byte Oprnd ; N r < 0, Z r = 0
Figure 4.24, 4.25 Instruction specifier Opcode r aaa Operand specifier 1 1 0 1 0 0 0 1 D 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 4 A NZ A 036D 92 004A D1004A Load byte accumulator NZ 00 A 0392 92 004A (a) Before (b) After
The store byte instruction Instruction specifier: 1111 raaa Stores one byte from the right half of register r to memory byte Oprnd r 8..15
Figure 4.26 XA 036D 92 F1004A Store byte A 036D 004A accumulator 6D 004A (a) Before (b) After
The character input instruction Instruction specifier: 0100 1aaa Stores one ASCII byte from the input device to memory byte Oprnd {character input}
Figure 4.27, 4.28 Instruction specifier Opcode aaa 0 1 0 0 1 0 0 1 4 9 Operand specifier 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 4 A Input Input W 92 004A 49004A Character input W 57 004A (a) Before (b) After
The character output instruction Instruction specifier: 0101 0aaa Sends one ASCII byte from memory to the output device {character output} byte Oprnd
Figure 4.29 Output Output 48 004A 51004A Character output 48 004A H (a) Before (b) After
The von Neumann execution cycle Fetch instruction from [PC] Decode the instruction fetched Increment PC Execute the instruction fetched Repeat
Load the machine language program Initialize PC and SP do { Fetch the next instruction Decode the instruction specifier Increment PC Execute the instruction fetched } while (the stop instruction does not execute) Figure 4.30
Figure 4.31 Load the machine language program into memory starting at address 0000 PC 0000 SP [FFF8] do { Fetch the instruction specifier at address in PC PC PC + 1 Decode the instruction specifier if (the instruction is not unary) { Fetch the operand specifier at address in PC PC PC + 2 } Execute the instruction fetched } while ((the stop instruction does not execute) && (the instruction is legal))
Figure 4.32 Address Machine Language (bin) 0000 0101 0001 0000 0000 0000 0111 0003 0101 0001 0000 0000 0000 1000 0006 0000 0000 0007 0100 1000 0008 0110 1001 Address Machine Language (hex) 0000 510007 ;Character output 0003 510008 ;Character output 0006 00 ;Stop 0007 48 ;ASCII H character 0008 69 ;ASCII i character Output Hi
Figure 4.33 PC IR 0000?????? 0003?????????? 0006?? Output PC???? 0007???????? IR?????? 0008?? 0000 0003 0006 0007 0008 510007 510008 00 48 69 Output (a) Initial state before loading. (b) Program loaded into main memory. PC IR 0000?????? 0000 0003 0006 0007 0008 510007 510008 00 48 69 Output PC IR 0000 510007 0000 0003 0006 0007 0008 510007 510008 00 48 69 Output (c) 0000 (hex) (d) Fetch
Figure 4.33 (Continued) PC IR 0000 510007 0003 510008 0003 0006 00 Output PC 0003 0007 48 510007 IR 510007 0008 69 0000 0003 0006 0007 0008 510007 510008 00 48 69 Output (e) Increment. (f) Execute. Character sent to output device. PC IR 0000 510007 0003 510008 0003 0006 00 Output PC 0006 0007 48 510008 IR 510008 0008 69 0000 0003 0006 0007 0008 510007 510008 00 48 69 Output (g) Fetch. (h) Increment.
Figure 4.33 (Continued) PC IR 0006 510008 0000 0003 0006 0007 0008 510007 510008 00 48 69 Output PC IR 0006 00???? 0000 0003 0006 0007 0008 510007 510008 00 48 69 Output (i) Execute. Character sent to output device. (j) Fetch PC IR 0000 510007 0003 510008 0007 0006 00 Output PC 0007 0007 48 00???? IR 00???? 0008 69 0000 0003 0006 0007 0008 510007 510008 00 48 69 Output (k) Increment PC. (l) Execute. The computer halts.
Figure 4.34 Address Machine Language (bin) 0000 0100 1001 0000 0000 0000 1101 0003 0100 1001 0000 0000 0000 1110 0006 0101 0001 0000 0000 0000 1110 0009 0101 0001 0000 0000 0000 1101 000C 0000 0000 Address Machine Language (hex) 0000 49000D ;Character input 0003 49000E ;Character input 0006 51000E ;Character output 0009 51000D ;Character output 000C 00 ;Stop Input up Output pu
Figure 4.35 Address Machine Language (bin) 0000 1100 0001 0000 0000 0001 0001 0003 0111 0001 0000 0000 0001 0011 0006 1010 0001 0000 0000 0001 0101 0009 1111 0001 0000 0000 0001 0000 000C 0101 0001 0000 0000 0001 0000 000F 0000 0000 0010 0000 0000 0011 0000 0000 0000 0101 0013 0000 0000 0000 0011 0015 0000 0000 0011 0000 Address Machine Language (hex) 0000 C10011 ;A := first number 0003 710013 ;Add the two numbers 0006 A10015 ;Convert sum to character 0009 F10010 ;Store the character 000C 510010 ;Output the character 000F 00 ;Stop 0010 00 ;Character to output 0011 0005 ;Decimal 5 0013 0003 ;Decimal 3 0015 0030 ;Mask for ASCII char Output 8
Figure 4.36 Address Machine Language (bin) 0000 1101 0001 0000 0000 0001 1101 0003 1111 0001 0000 0000 0000 1001 0006 1100 0001 0000 0000 0001 0111 0009 0111 0001 0000 0000 0001 1001 000C 1010 0001 0000 0000 0001 1011 000F 1111 0001 0000 0000 0001 0110 0012 0101 0001 0000 0000 0001 0110 0015 0000 0000 0016 0000 0000 0017 0000 0000 0000 0101 0019 0000 0000 0000 0011 001B 0000 0000 0011 0000 001D 1000 0001
Figure 4.36 (Continued) Address Machine Language (hex) 0000 D1001D ;Load byte accumulator 0003 F10009 ;Store byte accumulator 0006 C10017 ;A := first number 0009 710019 ;Add the two numbers 000C A1001B ;Convert sum to character 000F F10016 ;Store the character 0012 510016 ;Output the character 0015 00 ;Stop 0016 00 ;Character to output 0017 0005 ;Decimal 5 0019 0003 ;Decimal 3 001B 0030 ;Mask for ASCII char 001D 81 ;Byte to modify instruction Output 2
Figure 4.37 0000 FBCE FBCF Application program Operating system FFFF
ory devices Read/Write memory Also called Random-Access ory (RAM) Can load from RAM and store to RAM Read-Only memory (ROM) Can load from ROM Cannot store to ROM RAM and ROM are both random
Figure 4.38 0000 FBCE FBCF FC56 FC57 FFFF Application program Operating system RAM Operating system ROM RAM ROM
Figure 4.39 0000 Applications program User stack FBCF System stack FC4F FC57 I/O buffer Loader FC9B Trap handler FFF8 FFFA FFFC FFFE FBCF FC4F FC57 FC9B
The load option SP [FFFA] PC [FFFC] Start the von Neumann cycle
Figure 4.40 SP PC???????? FFFA FFFC 7C4F 7C57 SP PC FC4F???? FFFA FFFC FC4F FC57 (a) Initial state. (b) SP [FFFA] SP PC FC4F FC57 FFFA FFFC FC4F FC57 (c) PC [FFFC]
The execute option SP [FFF8] PC 0000 Start the von Neumann cycle