BOOLEAN ALGEBRA. 1. State & Verify Laws by using :

Similar documents
X Y Z F=X+Y+Z

UNIT-4 BOOLEAN LOGIC. NOT Operator Operates on single variable. It gives the complement value of variable.

Unit-IV Boolean Algebra

Menu. Algebraic Simplification - Boolean Algebra EEL3701 EEL3701. MSOP, MPOS, Simplification

Experiment 3: Logic Simplification

Chapter 2 Boolean algebra and Logic Gates

QUESTION BANK FOR TEST

Philadelphia University Faculty of Information Technology Department of Computer Science. Computer Logic Design. By Dareen Hamoudeh.

2.6 BOOLEAN FUNCTIONS

LSN 4 Boolean Algebra & Logic Simplification. ECT 224 Digital Computer Fundamentals. Department of Engineering Technology

Computer Science. Unit-4: Introduction to Boolean Algebra

ENGINEERS ACADEMY. 7. Given Boolean theorem. (a) A B A C B C A B A C. (b) AB AC BC AB BC. (c) AB AC BC A B A C B C.

Gate Level Minimization

Standard Forms of Expression. Minterms and Maxterms

2.1 Binary Logic and Gates

Assignment (3-6) Boolean Algebra and Logic Simplification - General Questions

Binary logic. Dr.Abu-Arqoub

Objectives: 1- Bolean Algebra. Eng. Ayman Metwali

Code No: R Set No. 1

Lecture 4: Implementation AND, OR, NOT Gates and Complement

Code No: R Set No. 1

Chapter 2. Boolean Expressions:

Chapter 3 Simplification of Boolean functions

IT 201 Digital System Design Module II Notes

Chapter 2: Combinational Systems

CS February 17

DKT 122/3 DIGITAL SYSTEM 1

Experiment 4 Boolean Functions Implementation

Lecture 5. Chapter 2: Sections 4-7

Chapter 3. Gate-Level Minimization. Outlines

Combinational Logic Circuits

Code No: 07A3EC03 Set No. 1

Variable, Complement, and Literal are terms used in Boolean Algebra.

Code No: R Set No. 1

CS470: Computer Architecture. AMD Quad Core

UNIT 2 BOOLEAN ALGEBRA

ELCT201: DIGITAL LOGIC DESIGN

Boolean algebra. June 17, Howard Huang 1

Circuit analysis summary

Boolean Algebra and Logic Gates

Announcements. Chapter 2 - Part 1 1

Bawar Abid Abdalla. Assistant Lecturer Software Engineering Department Koya University

Gate Level Minimization Map Method

CSCI 220: Computer Architecture I Instructor: Pranava K. Jha. Simplification of Boolean Functions using a Karnaugh Map

Boolean Algebra. BME208 Logic Circuits Yalçın İŞLER

1. Mark the correct statement(s)

DSAS Laboratory no 4. Laboratory 4. Logic forms

Digital Logic Design (CEN-120) (3+1)

Gate-Level Minimization

Introduction to Computer Architecture

Computer Organization

SYNERGY INSTITUTE OF ENGINEERING & TECHNOLOGY,DHENKANAL LECTURE NOTES ON DIGITAL ELECTRONICS CIRCUIT(SUBJECT CODE:PCEC4202)

Definitions. 03 Logic networks Boolean algebra. Boolean set: B 0,

CMPE223/CMSE222 Digital Logic

2008 The McGraw-Hill Companies, Inc. All rights reserved.

Simplification of Boolean Functions

Introduction to Boolean logic and Logical Gates

SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road QUESTION BANK (DESCRIPTIVE)

ELCT201: DIGITAL LOGIC DESIGN

Gate-Level Minimization. BME208 Logic Circuits Yalçın İŞLER

B.Tech II Year I Semester (R13) Regular Examinations December 2014 DIGITAL LOGIC DESIGN

Combinational Logic & Circuits

ECE380 Digital Logic

Digital Logic Lecture 7 Gate Level Minimization

R.M.D. ENGINEERING COLLEGE R.S.M. Nagar, Kavaraipettai

Bawar Abid Abdalla. Assistant Lecturer Software Engineering Department Koya University

GATE Exercises on Boolean Logic

SWITCHING THEORY AND LOGIC CIRCUITS

Summary. Boolean Addition

Combinational Logic Circuits

Module -7. Karnaugh Maps

Gate-Level Minimization

CS8803: Advanced Digital Design for Embedded Hardware

To write Boolean functions in their standard Min and Max terms format. To simplify Boolean expressions using Karnaugh Map.

ENGIN 112. Intro to Electrical and Computer Engineering

Karnaugh Maps. Kiril Solovey. Tel-Aviv University, Israel. April 8, Kiril Solovey (TAU) Karnaugh Maps April 8, / 22

ISC 2007 COMPUTER SCIENCE PAPER 1 THEORY PART I Answer all questions in this part

ENGIN 112 Intro to Electrical and Computer Engineering

Switching Theory & Logic Design/Digital Logic Design Question Bank

Digital logic fundamentals. Question Bank. Unit I


數位系統 Digital Systems 朝陽科技大學資工系. Speaker: Fuw-Yi Yang 楊伏夷. 伏夷非征番, 道德經察政章 (Chapter 58) 伏者潛藏也道紀章 (Chapter 14) 道無形象, 視之不可見者曰夷

Boolean Logic CS.352.F12

Date Performed: Marks Obtained: /10. Group Members (ID):. Experiment # 04. Boolean Expression Simplification and Implementation

Chapter 3. Boolean Algebra and Digital Logic

DHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING AND TECHNOLOGY

9/10/2016. The Dual Form Swaps 0/1 and AND/OR. ECE 120: Introduction to Computing. Every Boolean Expression Has a Dual Form

EEE130 Digital Electronics I Lecture #4_1

CHAPTER-2 STRUCTURE OF BOOLEAN FUNCTION USING GATES, K-Map and Quine-McCluskey

Gate-Level Minimization

DIGITAL CIRCUIT LOGIC UNIT 5: KARNAUGH MAPS (K-MAPS)

Gate-Level Minimization

Computer Engineering Chapter 3 Boolean Algebra

R10. II B. Tech I Semester, Supplementary Examinations, May

ISC 2009 COMPUTER SCIENCE PAPER 1 THEORY PART I Answer all questions in this part

Department of Electrical Engineering McGill University ECSE 221 Introduction to Computer Engineering Assignment 2 Combinational Logic

NODIA AND COMPANY. GATE SOLVED PAPER Computer Science Engineering Digital Logic. Copyright By NODIA & COMPANY

ISC 2011 COMPUTER SCIENCE PAPER 1 THEORY

Digital Logic Design. Outline

Specifying logic functions

Transcription:

BOOLEAN ALGEBRA. State & Verify Laws by using :. State and algebraically verify Absorption Laws. (2) Absorption law states that (i) X + XY = X and (ii) X(X + Y) = X (i) X + XY = X LHS = X + XY = X( + Y) = X. [ + Y = ] = X = RHS. Hence proved. (ii) X(X + Y) = X LHS = X(X + Y) = X. X + XY = X + XY = X( + Y) = X. = X = RHS. Hence proved. [ mark for the statement] [ mark for proving it algebraically]

2. State and verify Distributive Laws algebraically. (2) Distributive law state that (a) X(Y +Z) = XY + XZ (b) X + YZ = (X + Y)(X + Z) now proof for st no. is as simple as we can see = XY + XZ = X(Y +Z) L.H.S=R.H.S. now proof for 2nd. law R.H.S. = (X + Y)(X + Z) = XX + XZ + XY + YZ = X + XZ + XY + YZ (XX = X Indempotence law) = X + XY + XZ + YZ = X( + Y) + Z(X + Y) = X. + Z(X + Y) ( + Y = property of and ) = X + XZ + YZ) (X. = X property of and ) = X( + Z) + YZ = X. + YZ ( + Z = property of and ) = X. + YZ (X. = X property of and ) = L.H.S. Hence proved. 3. State and verify Demorgan's Laws algebraically. (2) 4. Prove algebraically the third distributive law X + X Y = X + Y. L.H.S. = X + X Y = X. + X Y (X. = X property of and ) = X( + Y) + X Y ( + Y = property of and ) = X + XY + X Y = X + Y(X + X ) = X + Y. (X + X = complementarity law) = X + Y (Y. = Y property of and ) = R.H.S. Hence proved. 2

2. Verify the following algebraically: (2). (A +B ).(A +B)=A.B+A.B LHS (A + B ). (A+B) = A.A + A.B + A.B + B.B = + A.B + A.B + = A.B + A.B = RHS (Verified) 2. Verify the following using Boolean Laws. X + Y'= X.Y+X.Y'+X'.Y' L.H.S =X + Y =X.(Y+Y )+ (X + X ).Y =X.Y + X.Y + X.Y +X.Y =X.Y + X.Y + X.Y =R.H.S OR R.H.S =X.Y + X.Y + X.Y =X.(Y + Y )+ X.Y =X. + X.Y =X + X.Y =X + Y =L.H.S 3. 4. Verify the following using Truth Table. (2). U. (U' +V) = (U + V) 2. X+Y. Z=(X+Y).(X+Z) 3. X+ (Y+Z) = (X+Y) + Z 4. A(B + B C + B C ) = A 5. A + A B = A + B' 6. (x + y + z).(x + y + z) = y + z 7. A B C + A BC + AB C = A C + B C 5. Name the law shown below and verify it using a truth table. (2). A+B.C= (A+B).(A+C) - > Distributive Law 2. X+X.Y=X+Y -> third distributive law 3

6. What does duality principle state? What is its usage in Boolean algebra? The principle of duality states that starting with a Boolean relation, another Boolean relation can be derived by :. Changing each OR sign(+) to an AND sign(.). 2. Changing each AND sign(.) to an OR sign(+). 3. Replacing each by and each by. Principle of duality is use in Boolean algebra to complement the Boolean expression. 7. Write dual of the following Boolean Expression : (a) (x + y ) (b) xy + xy + x y (c) a + a b + b (d) (x + y + z)(x + y) (a) xy (b) (x + y)(x + y )(x + y) (c) a. (a + b). b (d) xy z + xy 8. Write the equivalent expression for the following Logical Circuit: (2) 4

9. Draw a logical Circuit Diagram for the following Boolean Expression: 2. (U + V').W' + Z 2. Draw the logic circuit for F=AB' + CD'. Draw a logical Circuit Diagram for the following Boolean Expression by using NOR gate and NAND Gate 5

. CANONICAL SOP AND POS. What do you mean by canonical form of a Boolean expression? Which of the following are canonical? (i) ab + bc (ii) abc + a bc + ab c (iii) (a + b)(a +b ) (iv) (a + b + c)(a + b + c)(a + b +c ) (v) ab + bc + ca Boolean Expression composed entirely either of Minterms or maxterms is referred to as canonical form of a Boolean expression. (i)non canonical (ii) canonical (iii) canonical (iv) canonical (v) Non canonical 6

Type : Q:.(i) Express P+Q R in canonical SOP form. () (ii) X + X Y + X Z = X(Y + Y )(Z + Z ) + X Y(Z + Z ) + X Z ( (Y + Y ) = (XY + XY )(Z + Z ) + X YZ + X YZ + X YZ + X Y Z = Z(XY + XY ) + Z (XY + XY ) + X YZ + X YZ + X YZ + X Y Z = XYZ + XY Z + XYZ + XY Z + X YZ + X YZ + X YZ + X Y Z By removing duplicate terms we get canonical Sum of=product form : XYZ + XY Z + XYZ + XY Z + X YZ + X YZ + X Y Z Q: 2.(i) Express P+Q R in POS form. () : P+Q R = (P + Q ) ).(P + R) [Distributive Law] = (P + Q + RR )(P + R + QQ ) = (P + Q + R)(P + Q + R ) (P + R + Q)(P + R + Q ) [Distributive Law] = (P + Q + R)(P + Q + R ) (P + R + Q) [ By Removing the duplicate terms] (ii) (X + Y)(Y + Z)(X + Z) = (X + Y + ZZ )(XX + Y + Z)(X + YY + Z) = (X + Y + Z)(X + Y + Z )(X + Y + Z)(X + Y + Z)(X + Y + Z)(X + Y + Z) By removing duplicate terms we get canonical Product of Sum form: (X + Y + Z)(X + Y + Z )( X + Y + Z)( X + Y + Z) Type 2: Q: 3 7

Type 3: Q: 4 Convert the following Boolean expression into its equivalent Canonical Product of Sum form: X.Y. Z + X.Y.Z + X.Y.Z () X.Y.Z + X.Y.Z + X.Y.Z X Y Z F POS X + Y + Z X + Y + Z X + Y + Z X + Y + Z X + Y + Z F( (X,Y,Z) = (X + Y + Z)( X + Y + Z )( X + Y + Z) ( X + Y + Z)( X + Y + Z ) Type 4: Q.5 2. K MAP Following each question carry 3 marks: ) 8

2) ) Reduce the following Boolean Expression using K-Map: F(A,B,C,D)= (,,2,4,5,6,8,) 2) Reduce the following Boolean Expression using K-Map: F(U,V,W,Z)= (,,2,4,5,6,8,) 9

3) Reduce the following Boolean Expression using K-Map: F(A,B,C,D)= π(,,2,4,5,6,8,) 4) Reduce the following Boolean Expression using K-Map: F (X, Y, Z, W) = (,,3,4,5,7,9,,,3,5) 5) Reduce the following Boolean expression using K map: F(M,N,O,P)= (,,3,4,5,6,7,9,,,3,5) 6) Obtain simplified form for a Boolean expression F(x,y,z,w) = Σ(,3,4,5,7,9,,2,3,5) using K Map 7) F(P,Q,R,S)= (,3,5,6,7,,2,5) 8) F(P, Q,R, S) = Σ (3,5,7,,,3,5) 9) F(X,Y,Z,W) = Σ (,3,4,5,7,,3,5) ) F(P,Q,R,S)= π (,3,5,6,7,,2,5) ) F(P, Q, R, S) = Σ(, 2, 3, 5,6, 7, 9,, 2, 3, 5) 2) F (A,B,C,D) = (,,3,4,5,7,8,,2,4,5) 3) F (A,B,C,D) = π(5,6,7,8,9,2,3,4,5) 4) F (X,Y,Z,W) = (,,4,5,7,8,9,2,3,5) 5) F (A,B,C,D) = (,2,3,4,6,7,8,,2) 6) F(U,V,W,Z)= π 7) F(P,Q,R,S)=Σ(l,3,5,8,,2,5) 8) F(U,V,W,Z) = (,, 2, 3, 4,, ) 9) F(P, Q, R, S) = (,,2,4,5,6,8, 2) 2) F(A,B,C,D)= (,3,4,5,6,7,2,3) 2) F (U, V, W, Z) = II (,, 3, 5, 6, 7, 5) 22) F(X,Y,Z,W) = Σ(,,6,8,9,l,,2,5)