Appendix A File Formats A.1 Benchmarks Tables A.1 and A.2 present benchmark parameters for two-level logic (in ESPRESSO format) set and finite-state tables (in KISS2 format) set respectively. A.2 ESPRESSO Format A pla format is a format developed for physical description of Programmable Logic Arrays. To be exact espresso format is used in the book which is an input format for ESPRESSO minimizer. An espresso format is slightly different than pla format. Notation: lines beginning with a # are comments and are ignored, lines beginning with a. contain control information about the pla. Control information contained in the pla:.i <number> number of inputs,.o <number> number of outputs,.p <number> number of product terms (pterms),.e (.end) The end of the pla description. Optionally:.phase <vec> specifies polarity of each output function, where: <vec> is a string of as many 0 s or 1 s as there are output functions (a 1 specifies that the ON -set of the corresponding output function should be used, and a 0 specifies that the OFF -set of the corresponding output function should be minimized). The description of function is contained with one line per product term, where output part represent: 1 for ON-set, 0 for OFF-set, x, X, or - for DC-set.
164 A File Formats Table A.1 FSM bechmarks Benchmark Inputs Outputs Products States bbara 4 2 60 10 bbsse 7 7 56 16 bbtas 2 2 24 6 beecount 3 4 28 7 cse 7 7 91 16 dk14 3 5 56 7 dk15 3 5 32 4 dk16 2 3 108 27 dk17 2 3 32 8 dk27 1 2 14 7 dk512 1 3 30 15 ex1 9 19 138 20 ex4 6 9 21 14 ex6 5 8 34 8 keyb 7 2 170 19 lion 2 1 11 4 lion9 2 1 25 9 mark1 5 16 22 15 mc 3 5 10 4 opus 5 6 22 10 planet 7 19 115 48 pma 8 8 73 24 s1 8 6 107 20 s1488 8 19 251 48 s1494 8 19 250 48 s208 11 2 153 18 s27 4 1 34 6 s386 7 7 64 13 s420 19 2 137 18 s510 19 7 77 47 s820 18 19 232 25 s832 18 19 245 25 sand 11 9 184 32 sse 7 7 56 16 styr 9 10 166 30 tav 4 4 49 4 tbk 6 3 1569 32 tma 7 6 44 20 train11 2 1 25 11 train4 2 1 14 4
A.2 ESPRESSO Format 165 Table A.2 Two-level benchmarks Benchmark Inputs Outputs Products 5xp1 7 10 75 b12 15 9 431 bw 5 28 87 clip 9 5 167 con1 7 2 9 duke2 22 29 87 ex1010 10 10 810 f51m 8 8 76 inc 7 9 34 ldd 9 19 93 misex1 8 7 32 misex2 25 18 29 pcle 19 9 25 rd53 5 3 32 rd73 7 3 141 rd84 8 4 256 root 8 5 256 sao2 10 4 58 sqn 7 3 96 sqr6 6 12 64 squar5 5 8 32 table3 14 14 175 vg2 25 8 110 x2 10 7 35 Z4m1 7 4 59 Z5xp1 7 10 128 Control information may also contain more general set of parameters. There are two used in the book:.ilb <labels> left-bottom-and plane labels,.ob <labels> left-bottom-or plane labels. Example (xor5.pla):.i 5.o 1.ilb d c b a e.ob xor5.p 16 11111 1 01110 1 10110 1 00111 1 11010 1
166 A File Formats 01011 1 10011 1 00010 1 11100 1 01101 1 10101 1 00100 1 11001 1 01000 1 10000 1 00001 1.e For more detailed information see: Yang S. (1991) Logic Synthesis and Optimization Benchmarks User Guide. Microelectronic Center of North Carolina, Version 3.0, http://www.cbl.ncsu.edu:16080/benchmarks/lgsynth91/ A.3 KISS Format A kiss2 format is a format developed for FSM benchmarks. Control information contained in the kiss2:.i <number> number of inputs,.o <number> number of outputs,.p <number> number of products,.s <number> number of internal states,.r <label> reset state. The description of the FSM is contained with one line per product term. Usually, the product term is symbolic. Input part of the implicant form: input vector and present state. Output part of the implicant form: next state and output vector. Input and output vectors are represented like in espresso format. For example: 1--- state_a state_b 0000 A kiss2 define don t care states as:. A present-state don t-care condition indicates that no matter what state you are in, a specified input produces a transition to a given next state and output condition. For example: 1--- * RESET 0000
A.3 KISS Format 167 Example (dk27.kiss2):.i 1.o 2.p 14.s 7 0 START state6 00 0 state2 state5 00 0 state3 state5 00 0 state4 state6 00 0 state5 START 10 0 state6 START 01 0 state7 state5 00 1 state6 state2 01 1 state5 state2 10 1 state4 state6 10 1 state7 state6 10 1 START state4 00 1 state2 state3 00 1 state3 state7 00 For more detailed information see: Yang S. (1991) Logic Synthesis and Optimization Benchmarks User Guide. Microelectronic Center of North Carolina, Version 3.0, http://www.cbl.ncsu.edu:16080/benchmarks/lgsynth91/
Appendix B ESPRESSO Minimizer An ESPRESSO-II is a boolean minimization program. It takes as input a two-level representation of a two-valued (or multiple-valued) Boolean function, and produces a minimal equivalent representation. Options allow for using an exact minimization algorithm, for choosing an optimal phase assignment for the output functions, and for choosing an optimal assignment of the inputs to input decoders. Command line is as follows: espresso [options] [file] Some (used by authors) command line options are: -Dcheck Checks that the function is a partition of the entire space (i.e., that the ON-set, OFF-set and DC-set are pairwise disjoint, and that their union is the Universe). -Dexact Exact minimization algorithm (guarantees minimum number of product terms, and heuristically minimizes number of literals). Potentially expensive. -Dopo Perform output phase optimization (i.e., determine which functions to complement to reduce the number of terms needed to implement the function). After choosing an assignment of phases for the outputs, the function is minimized. A simple algorithm is used which may become very expensive for a large number of outputs (e.g., more than 40). -Dopoall Minimize the function with all possible phase assignments. A range of outputs to cycle through can be given with -rn-m (the default is to use all outputs). The option -S1 will perform an exact minimization for each phase assignment. Be warned that opoall requires an exponential number of minimizations. -Dso Minimize each function one at a time as a single-output function. Terms will not be shared among the functions. The option -S1 will perform an exact minimization for each single-output function.
170 B ESPRESSO Minimizer -Dso both Minimize each function one at a time as a single-output function, but choose the function or its complement based on which has fewer terms. The option -S1 will perform an exact minimization for each single-output function and its complement to determine which has fewer terms. For more details see: Brayton R., Hachtel G., McMullen C., Sangiovanni-Vincentelli A. (1984) Logic Minimization Algorithms for VLSI Synthesis. Kluwer Academic Publishers Rudell R., Sangiovanni-Vincentelli A. (1985) Espresso-MV: Algorithms for Multiple-Valued Logic Minimization. Proc. Cust. Int. Circ. Conf., Portland Rudell R. (1986) Multiple-Valued Minimization for PLA Synthesis. Master s Report, University of California, Berkeley Rudell R., Sangiovanni-Vincentelli A. (1986) Exact Minimization of Multiple-Valued Functions for PLA Optimization. Int. Conf. Comp. Aid. Des., Santa Clara
Index G(Y,Ū),74 card(y ),10 μ-range, 10 ξ f -cell-level, 18 algorithm ao, 81 aocs, 110 ec, 110 i (JEDI), 129 ih (NOVA), 127 ioh (NOVA), 127 mb, 51 ml, 59 o (JEDI), 129 one-hot+zero, 57 ov, 67 so, 98 socs, 116 ufcs, 120 benchmark, 123, 163 binary counter, 112 cascaded feedback, 78 cell-level, 18 chromatic number, 44 columns incompatibility, 42 congruence, 79 CPLD, 3, 12 cube, 10 DC-set, 9 discriminant Δ y,74 disjoint conditions, 34 distance, 10 encoding function, 11 encoding vector, 11 espresso, 2, 123 espresso format, 9, 163 exchange of codes, 109 FPGA, 3, 12 FSM, 1, 11, 88 fulfilled PMC, 30 fulfilled SMC, 33 functional description, 142 graph coloring, 42 graph of outputs, 75 half-mutual-covering implicants, 93, 95 HDL, 140 high impedance state, 89 implementation, 140 incompatibility graph G(V, E), 43 ISCAS 85, 123 ISCAS 89, 123 JEDI, 129 kiss format, 11, 166 kiss2, 123 LGSynth91, 123 literal, 9 logic allocator, 12
172 Index logic synthesis, 1 MCNC, 123 minterm, 9 multi-output implicant, 9 multiplexer, 87 non-disjoint conditions, 35 NOVA, 127 OFF-set, 9 ON-set, 9 one-cell-level, 18, 87 output function, 11 PAL, 13 parallel expander, 14 partition variable, 90 PIA, 12 pla format, 163 primary graph of outputs, 74 primary merging condition, 29 product term, 9 range of discriminant μ ( Δ y ),74 reduced graph of outputs, 75 remainder, 79 satisfied PMC, 30 satisfied SMC, 33 secondary merging condition, 32 set of remainders R, 79 shared expander, 14 speed optimization, 92 state assignment, 11 state encoding, 11 state weight, 12 STT, 11 sum-of-products, 14, 87, 92 symbolic implicant, 11 table partitioning, 42 technology mapping, 1, 5, 71, 72, 88 technology-dependent optimization, 2, 79, 92, 101 technology-independent optimization, 1 term expansion, 88 parallel-cascaded, 15 series-cascaded, 15 with tri-state buffers, 90 term partitioning, 96 transition function, 11 tri-state buffer, 13, 87, 90, 92 two-level minimization, 2, 4, 71, 72, 92 two-level splitting minimization, 92 ultra fast FSM, 117 variable, 9 vector, 9 VHDL, 140 void conditions, 36