Accessing On-chip Instruments Through the Life-time of Systems ERIK LARSSON

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Transcription:

Accessing On-chip Instruments Through the Life-time of Systems ERIK LARSSON

Motivation We know: Electronics is used everywhere Transistors increase in number and decrease in size It leads to: Many possible defects New defects, such as ageing Can be handled with: More embedded (on-chip) instruments Lead to: Communication with instruments becomes important In this talk: How IEEE 687 enables such communication through the lifetime; from manufacturing test to reliability handling during operation

Our everyday lives.

includes much electronics,

which is characterized by Increasing transistor counts Decreasing transistor sizes An example: SUN M7 billion transistors 2 nm technology

and problems Ageing: a working IC slowly degrades and becomes defective after some time in operation No Trouble Found (NTF): a system seems defective in operation but when taken for repair no problem can be found. Example [ACC8]: Total cost of consumer electronics returns and repairs in USA was estimated at $3.8 billion in 27 For a typical $ billion dollar consumer electronic device manufacturer and large retailer, a % reduction in No Trouble Found returns can add up to approximately $37 million in shared savings. [ACC7] Accenture Research: Big Trouble with No Trouble Found Returns

need more effort Manufacturing problems which cause more effort: post-silicon validation, debug, wafer sort, package test, burn-in, printed circuit board (PCB) bring-up, and test of PCB assemblies. Reliability issues which cause more effort: monitor activity, making configuration, clock control, power management, fault detection, memory built-in self-test (BIST), logic BIST.

which can be handled with Embedded (on-chip) instruments: Memory built-in self-test (BIST), logic BIST, trace buffers, monitor activity, making configuration, clock control, power management, fault detection, The number of embedded instruments increases [FRO9] Can be in range of [POS5] [FRO9] Embedded Instrumentation: Its Importance and Adoption in the Test & Measurement Marketplace. [Online]. Available: http://www.frost.com/prod/servlet/ cio/2638885 [POS5] K. Posse, Component Manufacturer Perspective, in Proc. IEEE Int l Test Conf. (ITC), Oct. 25.

to be accessed through the lifetime At manufacturing (offline) In-situ test (operation) At repair-shop (offline) In general, when you buy an IC, you also get ways to access embedded instruments, for example BIST. Let s run the memory BIST

to be accessed through the lifetime At manufacturing IC users: (offline) In-situ test fantastic (operation) At repair-shop (offline) In general, when you buy an IC, you also get ways to access embedded IC manufacturer: instruments, not for sure example I want to BIST. enable access, at least not to everything Let s run the memory BIST

An embedded instrument A temperature sensor Enable Wait a while Get temperature Temp[3:] Temperature Sensor En

placed in an IC Temp[3:] Temperature Sensor En

enable, wait,. Temp[3:] Temperature Sensor En

get temperature Temp[3:] Temperature Sensor En

more instruments, but too many pins Temp[3:] Temperature Sensor En Temp[3:] Temperature Sensor En Temp[3:] Temperature Sensor En Temp[3:] Temperature Sensor En

With scan-chains, fewer pins Shift/capture Temp[3:] Scan-chain Temperature Sensor En

Retarget from parallel to seriell Temp[3:] Scan-chain Temperature Sensor En

Set to shift Shift Scan-chain Temp[3:] En Temperature Sensor

Start shifting Shift Scan-chain Temp[3:] En Temperature Sensor

Set to capture Capture Temp[3:] Scan-chain Temperature Sensor En

capture Capture Temp[3:] Scan-chain En Temperature Sensor

Many instruments Shift Scan-chain Scan-chain Temperature Sensor Temperature Sensor

Many instruments Shift Scan-chain Scan-chain Temperature Temperature Much time overhead Sensor all Sensor instrument are always on the scan-path

Simpler illustration Shift Scan-chain Scan-chain X Temperature Sensor X Temperature Sensor

Simpler illustration Shift Instrument Instrument 2

IEEE 49. Functional I/O BSC BSC BSC Core logic BSC BSC BSC Functional I/O BSC BSC Custom Register Bypass IR Decoder TMS TCK Instruction Register TAP Controller TRST

IEEE 49. Functional I/O BSC BSC BSC Core logic BSC BSC BSC Functional I/O BSC BSC Custom Register Bypass IR Decoder Step TMS TCK Instruction Register TAP Controller TRST

IEEE 49. Functional I/O BSC BSC BSC Core logic BSC BSC BSC Functional I/O BSC BSC INSTR Custom Register Bypass Select instruction for custom register IR Decoder Instruction Register Step TMS TCK TAP Controller TRST

IEEE 49. Functional I/O BSC BSC BSC Core logic BSC BSC BSC Functional I/O BSC BSC Custom Register Bypass IR Decoder Step 2 TMS TCK Instruction Register TAP Controller TRST

IEEE 49. Functional I/O BSC BSC BSC Core logic BSC BSC BSC Functional I/O BSC BSC Custom Register Bypass IR Decoder Step 2 TMS TCK Instruction Register TAP Controller TRST

IEEE 49. Custom Register Bypass Instrument Instrument 2

IEEE 49. Custom Register Bypass Instrument Instrument 2 Alternative : One custom register with both instruments Instrument Instrument 2

IEEE 49. Custom Register Bypass Instrument Instrument 2 Alternative : One custom register with both instruments Instrument Instrument 2 Alternative 2: One custom register per instrument Instrument Instrument 2

IEEE 49. Custom Register Bypass Instrument Instrument 2 Alternative : One custom register with both instruments Instrument Instrument 2 Alternative 2: One custom register per instrument Instrument Instrument 2

IEEE 49. Custom Register Bypass Instrument Instrument 2 Alternative : One custom register with both instruments Instrument Instrument 2 Alternative 2: One custom register per instrument Instrument Instrument 2

IEEE 49. Custom Register Bypass Instrument Instrument 2 Alternative : One custom register with both instruments Alternative : Instrument Instrument All instruments 2 are always accessed Alternative 2: One custom register per instrument Alternative 2: Instrument Cannot access both Instrument 2 instruments at the same time

IEEE 687 Custom Register Bypass Instrument Instrument 2 Custom Register C C C 2 I I2

IEEE 687 Custom Register C C C 2 I I2 Access this instrument

IEEE 687 Custom Register C C C 2 I I2 This scan-path must be active

IEEE 687 Custom Register C C C 2 I I2

IEEE 687 Custom Register C C C 2 I I2 Train ride #

IEEE 687 Custom Register C C C 2 I I2 Train ride #

IEEE 687 Custom Register C C C 2 I I2 Train ride #2 Train ride #

IEEE 687 Custom Register C C C 2 I I2 Train ride #2 Train ride #

IEEE 687 Custom Register C C C 2 I I2 Train ride #3 Train ride #2 Train ride #

IEEE 687 Custom Register C C 2 C Each train ride is a Capture- Shi2- Update I I2 (CSU) opera7on Control data in always included Train ride #3 Train ride #2 Train ride #

IEEE 687 Custom Register C C 2 C 3 DFT C 4 C 5 C 6 Sensor Debug

IEEE 687 Introduced two languages: Instrument Connectivity Language (ICL) Procedural Description language (PDL) ICL PDL

IEEE 687 PDL ICL iwrite DFT x; iapply; C C 2 C 3 iwrite DFT xf; iwrite Sensor 8; iapply; DFT iread DFT x8; iapply; iread Sensor ; iapply; C 4 C 5 C 6 Sensor Debug

IEEE 687 PDL ICL iwrite DFT x; iapply; C C 2 C 3 iwrite DFT xf; iwrite Sensor 8; iapply; DFT iread DFT x8; iapply; iread Sensor ; iapply; C 4 C 5 C 6 Sensor Debug

IEEE 687 PDL ICL iwrite DFT x; iapply; C C 2 C 3 iwrite DFT xf; iwrite Sensor 8; iapply; DFT iread DFT x8; iapply; iread Sensor ; iapply; C 4 C 5 C 6 Sensor Debug

IEEE 687 PDL ICL iwrite DFT x; iapply; C C 2 C 3 iwrite DFT xf; iwrite Sensor 8; iapply; DFT iread DFT x8; iapply; iread Sensor ; iapply; C 4 C 5 C 6 Sensor Debug

IEEE 687 PDL ICL iwrite DFT x; iapply; C C 2 C 3 iwrite DFT xf; iwrite Sensor 8; iapply; DFT iread DFT x8; iapply; iread Sensor ; iapply; C 4 C 5 C 6 Sensor Debug

IEEE 687 PDL ICL iwrite DFT x; iapply; C C 2 C 3 iwrite DFT xf; iwrite Sensor 8; iapply; iread DFT x8; iapply; Optimize: access to instrument C 4 C 5 C 6 DFT iread Sensor ; iapply; Sensor Debug

IEEE 687 Let s run the memory BIST

IEEE 687 Let s run the memory BIST Give the description of how instruments are connected (ICL) Give the description of operation to do on instruments (PDL)

IEEE 687 Let s run the memory BIST Give the description of how instruments are connected (ICL) Give the description of operation to do on instruments (PDL) Retarget Chiplevel format

IEEE 687 Let s run the memory BIST Give him the description of how instruments are connected (ICL) IC manufacturer: not sure I want to enable access, at least not to everything Retarget Give him the description of operation to do on instruments (PDL) Chiplevel format

IEEE 687 PDL ICL iwrite DFT x; iapply; C C 2 C 3 iwrite DFT xf; iwrite Sensor 8; iapply; DFT iread DFT x8; iapply; iread Sensor ; iapply; C 4 C 5 C 6 Sensor Debug

IEEE 687 PDL ICL iwrite DFT x; iapply; C C 2 C 3 iwrite DFT xf; iwrite Sensor 8; iapply; DFT iread DFT x8; iapply; iread Sensor ; iapply; C 4 C 5 C 6 Sensor Debug

IEEE 687 ICL C C 2 C 3 DFT C 4 C 5 C 6 Sensor Debug

IEEE 687 ICL C C 2 C 3 DFT C 4 C 5 C 6 Sensor FF Sensor Debug

IEEE 687 ICL C C 2 C 3 DFT C 4 C 5 C 6 Sensor FF Sensor Debug

IEEE 687 ICL C C 2 C 3 IC manufacturer: acceptable (???) DFT C 4 C 5 C 6 Sensor FF Sensor Debug

IEEE 687 for Reliability (In-Situ) Let s run the memory BIST A fault is detected and corrected

Infrastructure for Fault Handling? Functional infrastructure No extra cost, as it already exists, but adding fault handling traffic can degrade performance, both the functional and the fault handling. Predictability might be damaged as it is difficult to know when faults occur. Stand-alone infrastructure Adds an extra cost, unless an existing infrastructure such as IEEE 687 is reused, but is IEEE 687 good enough in terms of time to:» Detect that faults have occurred» Localize where the faults are

MASTER CPU Fault handling TAP SIB Custom Register System-Level SIB SIB Component Type-Level DSP SIB SIB SIB Component-Level CPU CPU CPU M 2 M M

MASTER CPU Fault handling TAP SIB System-Level SIB SIB Component Type-Level DSP SIB SIB SIB Component-Level CPU CPU CPU M 2 M M

MASTER CPU Fault handling TAP SIB System-Level SIB SIB Component Type-Level DSP SIB SIB SIB Component-Level CPU CPU CPU M 2 M M

MASTER CPU Fault handling TAP SIB System-Level SIB SIB Component Type-Level DSP SIB SIB SIB Component-Level CPU CPU CPU M 2 M M

MASTER CPU Fault handling TAP SIB System-Level SIB SIB Component Type-Level DSP SIB SIB SIB Component-Level CPU CPU CPU M 2 M M

MASTER CPU Fault handling TAP SIB SIB System-Level SIB SIB M SIB Error propagation network Component Type-Level DSP M SIB SIB SIB SIB CPU CPU CPU M 2 M M M Component-Level

MASTER CPU Fault handling TAP SIB SIB System-Level SIB SIB M SIB Error propagation network Component Type-Level DSP M SIB SIB SIB SIB CPU CPU CPU M 2 M M M Component-Level

MASTER CPU Fault handling TAP SIB SIB System-Level SIB SIB M SIB Error propagation network Component Type-Level DSP M SIB SIB SIB SIB CPU CPU CPU M 2 M M M Component-Level

MASTER CPU Fault handling TAP SIB SIB System-Level SIB SIB M SIB Error propagation network Component Type-Level DSP M SIB SIB SIB SIB CPU CPU CPU M 2 M M M Component-Level

MASTER CPU Fault handling TAP SIB SIB System-Level Time for fault detection: Good SIB SIB M SIB Error propagation network Component Type-Level DSP SIB SIB SIB SIB M Time for fault localization: Not so good* *will be addressed at ETS 6 CPU CPU CPU M 2 M M M Component-Level

Is there a future for IEEE 687? Tool vendors Industrial papers/case studies A. L. Crouch, IJTAG: The Path to Organized Instrument Connectivity, in Proc. IEEE Int l Test Conf. (ITC), Oct. 27, pp.. J. Rearick and A. Volz, A Case Study of Using IEEE P687 (IJTAG) for High-Speed Serial I/O Characterization and Testing, in Proc. IEEE Int l Test Conf. (ITC), Oct. 26, pp. 8. J. Rearick et al., IJTAG (Internal JTAG): A Step Toward a DFT Standard, in Proc. IEEE Int l Test Conf. (ITC), 25. K.Posse et al., IEEEP687:Toward Standardized Access of Embedded Instrumentation, in Proc. IEEE Int l Test Conf. (ITC), 26, pp. 8.

Is there research on IEEE 687? Optimization of access F. G. Zadegan et al., Access Time Analysis for IEEE P687, IEEE Transactions on Computers, vol. 6, no., pp. 459 472, Oct. 22. R. Baranowski, M. A. Kochte, and H.-J. Wunderlich, Scan Pattern Retargeting and Merging with Reduced Access Time, in Proceedings of IEEE European Test Symposium (ETS 3). IEEE Computer Society, 23, pp. 39 45. R.Cantoro, M. Montazeri, M.S.Reorda,F.G. Zadegan,and E.Larsson, On the Testability of IEEE 687 Networks, 25. [Online]. Available:http://lup.lub.lu.se/record/834/file/ 83425.pdf R. Krenz-Baath, F. Zadegan, and E. Larsson, Access time minimization in ieee 687 networks, in Test Conference (ITC), 25 IEEE International, Oct 25, pp.. Srinivasa Shashank NUTHAKKI, RAJIT KARMAKAR, Santanu CHATTOPADHYAY, Krishnendu CHAKRABARTY, Optimization of the IEEE 687 Access Network for Hybrid Access Schedules, VTS 5

IEEE 687 Custom Register C C C 2 I I2 Train ride #3 Train ride #2 Train ride #

Is there research on IEEE 687? Security T. Payakapan, S. Kan, K. Pham, K. Yang, J.-F. Cote, M. Keim, and J. Dworak, A case study: Leverage ieee 687 based method to automate modeling, verification, and test access for embedded instruments in a server processor, in Test Conference (ITC), 25 IEEE International, Oct 25, pp. J. Dworak, Z. Conroy, A. Crouch, and J. Potter, Board security enhance- ment using new locking sib-based architectures, in Test Conference (ITC), 24 IEEE International, Oct 24, pp.. J. Dworak and A. Crouch, A call to action: Securing ieee 687 and the need for an ieee test security standard, in VLSI Test Symposium (VTS), 25 IEEE 33rd, April 25, pp. 4. R. Baranowski, M. Kochte, and H.-J. Wunderlich, Securing access to reconfigurable scan networks, in Test Symposium (ATS), Asian, Nov 23, pp. 295 3. R. Baranowski, M. Kochte, and H.-J. Wunderlich, Fine-grained access management in reconfigurable scan networks, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 34, no. 6, pp. 937 946, June 25.

Is there research on IEEE 687? In-situ access K. Petersen, D. Nikolov, U. Ingelsson, G. Carlsson, F. Zadegan, and E. Larsson, Fault injection and fault handling: An mpsoc demonstrator using ieee p687, in On-Line Testing Symposium (IOLTS), 24 IEEE 2th International, July 24, pp. 7 75. A. Jutman, S. Devadze, and K. Shibin, Effective Scalable IEEE 687 Instrumentation Network for Fault Management, IEEE Design & Test, vol. 3, no. 5, pp. 26 35, Oct 23. K. Shibin, S. Devadze, and A. Jutman, Asynchronous Fault Detection in IEEE P687 Instrument Network, in IEEE 23rd North Atlantic Test Workshop (NATW), May 24, pp. 73 78. F. Ghani Zadegan, D. Nikolov, and E. Larsson, A self-reconfiguring ieee 687 network for fault monitoring, in Test Symposiutm (ETS), 26 IEEE European, May 26, pp. 6.

Conclusions Transistors increase in number and are becoming smaller, which leads to many possible defects and new defect types (ageing) will develop, more embedded instrumentation is needed. With PDL and ICL IEEE 687 becomes an attractive way to handle and connect embedded instruments used for manufacturing test purposes and in-situ reliability purposes

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