Multi-Channel Ultrasound Toolbox: A Flexible Modular Approach for Real- Time Array Imaging and Automated Inspection David Lines 1, James Wharrie 1 and John Hottenroth 2 1 Diagnostic Sonar Ltd. Baird Road, Kirkton Campus, Livingston, West Lothian, EH54 7BX, UK (+44) 1506-411877; fax (+44) 1506-412410; e-mail dave.lines@diagnosticsonar.com 2 National Instruments, Inc. 11500 N. Mopac Expressway, Austin, TX 78759-3504, USA (512) 683-6247; e-mail john.hottenroth@ni.com INTRODUCTION High data rates in multi-channel ultrasound acquisition systems usually require significant customization, which increases cost and reduces flexibility. This paper investigates the possibility of harnessing the flexibility of Field Programmable Gate Arrays (FPGAs) in a standard PC instrumentation platform to interface with the latest generation of multi-channel ultrasound digitizers. The FPGA provides very high performance that can be reconfigured under software control to provide a flexible platform, handling applications from array imaging to multi-channel automated inspection systems. A system has been developed with off-the-shelf components, which combines 32 channels of high-speed analog acquisition with a high performance FPGA for real-time, deterministic processing. This system has been interfaced to an array via multi-channel pulser-receivers with custom FPGA code developed using LabVIEW. The modular nature of both hardware and software allowed development of a scalable and customizable instrument that can acquire data from a linear array and process the data to provide a real-time image dynamically focused on both transmit and receive. The paper discusses how a novel combination of hardware and software modules can be used to build systems quickly that achieve high performance multi-channel ultrasound acquisition and processing, while being flexible enough to address a wide range of applications. BACKGROUND Ultrasound Flaw Detectors followed the now-familiar evolution from analogue to digital in the late 1980s and this was followed by the introduction of PC-based acquisition cards. In these an ultrasonic pulser and low noise receiver are combined with a high speed digitizer, allowing the standard processing functions such as filtering, rectification and gating to be implemented in software. The main deployment of these boards has been in online inspection applications or laboratory environments where the benefits of flexibility outweigh the advantages of smaller size and lower cost offered by mass-produced dedicated instrumentation. Ultrasonic Phased Array imagers use many channels in a highly synchronized parallel configuration. Consequently, the PC-based implementations use large numbers of boards and the systems are bulky and expensive which limits their deployment. The parallel data streams from all the channels are combined in a receive beamformer to produce the pulse-echo beams that make up the image. The data bus bandwidth required is a major constraint in PC-based implementations, despite the acceleration produced by the serial PCI express architecture. This bottleneck will become progressively more severe as the number of channels increases, especially with the introduction of 2D arrays. The traditional approach of increasing the width of the data bus produces limited benefit because the constraint is then the number of pins on the components and connectors. Medical ultrasound evolved from NDT in the 1950s but, with its significantly larger market, it soon became the driving force for many of the innovations in ultrasonic instrumentation. Highly integrated analogue front ends (AFEs) combine low-noise preamplifiers, variable gain amplifiers, filtering and digitizing for multiple channels in
the same device. The digitized outputs are in serial form to avoid the pin out constraint. These can be fed into the deserializer inputs of a Field Programmable Gate Array (FPGA) which can implement the parallel processing of the receive beamformer on a single integrated circuit. These architectural innovations were crucial to the reduction in size and cost for dedicated phased array systems but also provide a route to implement on a PC-based platform. This paper discusses such a flexible and scalable implementation. FLEXIBLE MULTI-CHANNEL DESIGN The key enabling technology is the AFE integrated circuit, which combines much of the analogue conditioning and the digitizer for multiple channels. These devices are available from a number of semiconductor manufacturers but all have the common feature each digitized output is a synchronous Double Data Rate (DDR) serial stream on a pair of pins using the Low-Voltage Differential Signaling (LVDS) standard. 50MHz sampling at 12bit resolution clocks the data out at 6x the sample rate i.e. 300MHz. This requires the destination components to be close and connected with matched track lengths across all outputs from the same device. Typically the AFEs integrate 8 channels in a single package. There are alternative approaches for the receiving and processing of the serial streams and these options are now discussed. Potential Beamformer Solutions The introduction of serial busses, such as PCI express, has driven semiconductor manufacturers to include dedicated de-serializing blocks on the input pins of their devices. The following processing options all have this capability: Application Specific Integrated Circuits (ASICs). Digital Signal Processors (DSPs) Field Programmable Gate Array (FPGAs). ASICs are customized integrated circuits and are able to achieve the ultimate in performance. However, the development costs are high, their functionality is fixed and so are only used where the market is for very large quantities and/or where there is no alternative. DSPs are used in medical ultrasound imaging systems but primarily for the back-end processing which acts on the beamformed data. They are best suited to complex processing algorithms on a relatively limited number of channels. Graphics Processor Units (GPUs) are special case DSPs that are optimized for display processing and the parallel architectures offer significant processing power at relatively low cost. However, the data still has to be transferred into the host and so does nothing to resolve the back-plane bandwidth constraints. FPGAs are similar to ASICs but comprise a massive array of small configurable logic blocks with user-defined connection paths between them. As with the ASIC approach, it is relatively simple for them to implement the high level of parallel processing as required for the beamformer, but with the major advantage that the functionality is reconfigurable. FPGAs are often used as a front-end processor in medical ultrasound imagers to produce the beamformed data used by the DSPs. FPGAs therefore offer an architecture that is well suited to the processing of the AFE data streams but with the flexibility that the ASIC does not offer. The use of FPGAs to process ultrasound NDT data streams has been described (Darlington et al, 1997). The FPGA was on a PCI-format HOTworks card and the IO pins of the device were connected to the PCI bus, two banks of onboard RAM and, by means of sockets, to a user-defined mezzanine board. The mezzanine card included a single channel ultrasonic pulser, receiver and digitizer and the parallel data stream was fed direct to the FPGA. This formed part of a commercial phased array imager and the concept of combining custom interface hardware with commercial, off the shelf (COTS) FPGA boards, had been proven to work. Traditionally, programming the FPGA requires a high level of expertise in Hardware Definition Languages (e.g. VHDL). However, recent developments with FPGA development tools and modular hardware enable leveraging the benefits of FPGAs for NDT applications (hardware-based processing, customizability, flexibility) without needing
to become an expert in traditional FPGA programming languages. The introduction of the multi-channel AFEs, and the availability of FPGAs with integral de-serializers, suggested that the time was right to revisit the original architecture but with many more channels. Hardware Implementation To explore the potential benefits of this architecture, we used National Instruments (NI) FlexRIO modular FPGA hardware programmed with LabVIEW FPGA, a graphical design language that allows the FPGA circuitry to be designed without needing to know VHDL coding or board design. We were able to simulate and debug the actions of the code in the standard LabVIEW software environment before deploying into the FPGA hardware with a high degree of confidence since we can use the same basic programming language for the FPGA programming. NI FlexRIO combines interchangeable, customizable I/O adapter modules with a user-programmable FPGA module in an industry-standard PXI (PCI extensions for Instrumentation) or PXI express platform. Modular FPGA-based I/O has been shown (Goodman et al., 2009) to be well suited for high performance NDT applications. The FlexRIO FPGA Modules are fitted in the chassis and communicate with custom hardware in an Adapter Module mounted on the front panel, as shown in Figure 1. For the I/O, we used the NI 5752, a 32 channel adapter module that combines four Texas Instruments AFE5801 chips. Each AFE handles 8 channels, providing 5dB to +31dB digitally controlled swept gain, and programmable filtering before digitizing at 50MSPS to 12bits. The 32 simultaneous data streams are de-serialized in the FPGA for processing or buffering before transfer to the host PC. The FPGA also has access to 2 digital inputs and 16 digital outputs and the latter can be used to control external pulsers. The AFE s differential inputs can handle up to 2V pkpk and so require protection from the transmitter if the elements are used in pulse-echo configuration directly into the AFE. Figure 1: NI 5752 32 channel adapter module connected with FlexRIO FPGA module (a) and in chassis with pulser/receiver interface (b) Single Board Configurations While the ideal system would have a large number of transmit channels and receive channels in the same device so that a whole system can be implemented with minimal number of components, there are inevitable practical compromises, including the FPGA s size and number of available pins, the requirement to provide an interface to some dedicated high-speed external storage for buffering the data, and the package count and power-dissipation of the external digital and analogue hardware for the pulsers and receivers.
It was therefore appropriate to look at the ways in which a typical implementation of 16 digital output channels and 32 analogue receive channels can be configured. These include: 32 element steered array (16 channel transmit/32 channel dynamic focus receive) 64/128/256 element multiplexed linear array (up to 28 channel transmit/32 channel dynamic focus receive) 32 element Full Raw Data acquisition (32 element dynamic focus transmit/32 element dynamic focus receive) 32 element steered array Each of the 16 digital output lines is used to generate the transmit excitation stream with appropriate delay to produce the desired transmit focus. These streams are routed to 16 external high voltage pulsers that are connected to 16 elements of the array. All 32 elements of the array are connected via transmit/receive protection switches and low-noise preamplifiers to the 32 differential inputs of the AFEs. The most likely scenario would have the transmitters exciting the center 16 elements of the array where the reduction in transmit resolution is traded for increased depth of field a benefit for the conventional arrangement of fixed transmit focus and dynamic receive focus. Where resolution is important, the transmitters could be routed to excite alternate receive elements. Here transmit resolution is retained but at the expense of grating lobes. Combinations of these extremes are possible. 64/128/256 element multiplexed linear array The system can be extended to work with the 64, 128 or more elements of a linear step-scanned array by means of a high voltage multiplexer between the elements and the transmitters and receivers. Unless an additional PXI card is used to control the multiplexers, some of the digital output lines will have to be diverted from driving transmit streams. The minimal control requirement would use 2 lines, leaving 14 for the transmit streams. If steering is required then this would mean 14 channel transmit/32 channel receive with similar considerations as for the 32 element steered array. However, these linearly scanned arrays are usually optimized for longest scan length and the large elements are not suitable for significant steering. If the beams are always normal to the array surface then the transmit delays are symmetric around the center of the transmit aperture and 14 drive signals can produce a transmit aperture of 28 elements. 32 element Full Raw Data (FRD) acquisition This configuration uses a different imaging technique termed Full Raw Data acquisition and processing (Lines 2006 and Lines et al. 2006) and is similar to that known as Full Matrix Capture (FMC) and Total Focusing Method (TFM). In this technique, one element (or occasionally more) is fired at a time and the data streams for all 32 channels are collected. The process is repeated with the transmit aperture position being progressively switched through all possible locations, resulting in an FRD data set of up to 32 x 32 streams for a 32 element array. The many benefits have been discussed in these references, but the key one is that every point in the reconstructed image is in optimal focus equivalent to dynamic focus on transmit as well as receive. If all the streams are recorded, then beam steering and position dependent material velocity correction can be applied as post-processing operations. The limited number of elements used on transmission (often just one) means that the 16 digital outputs are more than sufficient for the excitation signals and also the multiplexer controls. The 32 channel parallel acquisition means that a complete FRD frame for a 32 element array takes just 32 pulses. With receive multiplexing, this technique is extendable to the 64/128 element arrays. Single Board Results Existing multi-channel hardware, for pulsers, multiplexers and receivers, has been interfaced to the single FlexRIO system as shown in Figure 1b. This was used in 32 channel FRD mode with a 3.5Mz 32 element 0.059" (1.5mm) pitch array on a steel test piece with 1.5mm side-drilled holes, shown in Figure 2. The results are in Figure 3.
Figure 2: Steel test block Figure 3: Cascade A-scan plot (a) and FRD reconstructed B-scan (b) and 3D view (c) Figure 3a shows 32 out of the 1024 acquired RF streams as a cascade plot here displaying the pulse-echo responses from the 32 elements. Figure 3b shows the FRD reconstruction from those data streams corresponding to the region of the test pattern and Figure 3c shows the same data as a 3D profile. As shown in Figure 2, the gap between the closest pair of targets is around one wavelength and will pose a serious challenge to any imaging system. However, the focusing capability of the FRD reconstruction is able to produce a good rendition of the test pattern. The reconstructed beam direction was for 0 which corresponds to a horizontal beam, incident from the left in the B-scan. As a result, the nearest hole receives the full energy whilst the others are in its acoustic shadow showing the variation in amplitude. Figure 4 shows the same data set processed for 0, -20 and +20 incident beam angles and shows how the echo amplitude from each hole varies as it is moved out of the acoustic shadow. Figure 4: FRD reconstruction of the same data set with beam angles of 0 (a), -20 (b) and +20 (c) The same array was also used with a 21.5mm acrylic delay line on a 10mm thick Carbon Fiber Composite sample with 1mm and 2mm side-drilled holes, as shown in Figure 5a. Figure 5b is the 3D view of the corresponding FRD
reconstructed image for 0 angle of incidence, and clearly shows the echoes and back wall shadowing for both of the side-drilled holes. Figure 5: Array on CFC test piece (a) and 3D view of FRD reconstruction at 0 (b) SCALABLE MULTI-CHANNEL DESIGN The options outlined in the previous section illustrate the flexibility of the 32 channel acquisition module. However, there are applications where more than 32 channels are required, and the number of these will increase as 2D arrays become more common. Increasing the number of channels for conventional multi-channel online inspection systems was relatively straightforward solved by adding more slots in parallel. However phased arrays require tight synchronizing between all the excitation and reception channels and so any scalable architecture has to address this. Scalable architectures The limited number of digital outputs was discussed as an issue for the single FlexRIO system and solutions were presented in the previous section. A potential solution to this challenge that still leverages the modular FPGA components has been explored in the scalable architecture shown in Figure 6. Figure 6: Scalable 32 channel multiplexed module in chassis (a) and Adapter Modules (b) The existing FlexRIO FPGA module + 32 channel digitizer Adapter Module remains as before. A second FlexRIO FPGA module is used to generate the excitation signals for the 32 channel pulser Adapter Module (T32). A PXI format programmable High Voltage Power Supply completes the boards within the chassis and a third Adapter Module (R32) contains the transmit/receive protection switches and low-noise preamplifiers.
Transducer interfacing Flexibility has been a major benefit of the FPGA-based system and one of the main barriers to extending this was resolving how to address the multiple configuration requirements, including: pulse-echo vs. pitch-catch vs. throughtransmission; direct element interfacing vs. multiplexed; array vs. multiple discrete transducers. A further complication is the lack of any standard for the type of array connector let alone any agreement on pin assignments with each manufacturer having proprietary array interfaces. Multiplexed configurations allow the use of arrays with many hundreds of elements and connector density becomes a significant factor, especially when the front panel of the Adapter Modules are usually dedicated to inter-board connections. The solution, illustrated in Figure 6, has high-density connectors in the top surface of the T32 and R32 Adapter Modules interface to a user-customizable printed circuit board. This can be a plain interconnect board for direct coupled steered arrays or can include the multiplexers for step-scanned linear arrays. It is easy to provide a pair of array connectors one for transmit and one for receive for pitch-catch or through-transmission imaging. A 64 channel system would have the 3 board set repeated and the array connector interface can extend over the 6 slots and this approach is scalable over multiples of 32 channels. Synchronizing The transmitter sequencers are typically clocked at a multiple of the receiver sample clock for maximum temporal resolution whilst maintaining synchronous sampling. This can easily be achieved for a 32 channel module by generating the sample clock on the Transmit FlexRIO and passing it to the external clock input of the digitizer. For multiple 32 channel modules, it is best to exploit the synchronizing capability of the PXI express chassis. The master timing is generated by the board in the Star Trigger Slot and distributed to the Transmit FlexRIOs for each 32 channel module. Configurations This 32 transmit/32 receive module has integrated all of the external pulser-receivers and multiplexers outlined in the single FlexRIO implementation section and so is able to implement all of the configurations described. Indeed, the transmit aperture capability is now no longer constrained as the 16 digital output limitation no longer applies. Although it is likely that systems requiring 64 or more channels can use multiples of the 3 slot module, this is not always necessary. The reasoning is as follows: Multiple T32 modules are needed if more than 32 different element delays are required for any single excitation Multiple R32 modules are needed if acquisition constraints require more than 32 simultaneous receive channels. The alternative is to pulse two or more times with the same transmit focus and use receive multiplexing to achieve the same result by combining the data over the multiple pulses. Software/Firmware Software and FPGA firmware has been written to test out the acquisition and processing for the different architectures as illustrated in the results presented in the previous sections. The FRD reconstruction algorithms have been implemented in LabVIEW on the host PC and these have been progressively refined using the real data. Once the functionality was proven, the coding was optimized for speed in a format that was compatible with implementing on the FPGA. Data was passed though this optimized code and verified against results using the original code. This optimized code is able to acquire and process the FRD data above at frame rates between 5Hz and 20Hz, depending on the number of data points, using a dual-core processor host PC laptop with MXI-express connection to the PXI chassis. Transfer of the 32 x 32 A-scans across the PXI bus and then over the MXI-express link, will be a considerable bottleneck. Speed increases, without code changes, would result from using an embedded controller in a PXI-express chassis. Transfer of this code to the FPGA should offer further significant speed increases (even for PXI chassis) as the only back-plane transfers would be the processed image and the reconstruction would benefit from the massive parallelism of the targeted computation in the FPGA.
The software includes ray-tracing capability for deriving beamformer delay parameters for typical array inspection configurations and simulation software for predicting the resulting beam profile. To maximize the software flexibility of the system, it would be beneficial to have various levels of access including: Top level access via the Graphical User Interface as a standalone instrument without any programming High level access via DLL calls to access setup routines and to retrieve image data Low level access to the FPGA interface for developing customized code Combinations of the above e.g. using existing code as examples for developing and verifying custom code CONCLUSIONS High data rates, resulting in data bus bottlenecks, have been identified as a reason for the lack of flexible, off-theshelf solutions for multi-channel ultrasound acquisition systems and particularly for arrays. The availability of FPGAs in a standard PC instrumentation platform, interfacing with the latest generation of multi-channel ultrasound digitizers, has been proposed as a solution. A system has been developed with off-the-shelf components, which combines 32 channels of high-speed analog acquisition with a high performance FPGA for real-time deterministic processing. This system has been interfaced to an array via multi-channel pulser-receivers with custom FPGA code developed using LabVIEW. The modular nature of both hardware and software has allowed development of a flexible and scalable instrument that can be further customized if necessary. Potential configuration and processing options have been reviewed and images acquired using one of these techniques have been presented. The whole development process from specification of the architecture, through interfacing the hardware and coding of both FPGA and user interface to produce the 3D images took less than three months, demonstrating both the speed and capabilities of this approach. The practical issues in combining multiple modules have been discussed and a scalable architecture defined. The result is a novel combination of hardware and software modules that achieves high performance multi-channel ultrasound acquisition and processing, whilst being flexible enough to address a wide range of applications and demonstrating the benefits of FPGAs for real-time array imaging. REFERENCES 1. Darlington, D.J, Douglas R. Campbell and David I.A. Lines, Reconfigurable FPGAs for data compression in ultrasonic non-destructive testing, Proceedings of IEE Colloquium on DSP Chips in Real Time measurement and Control, University of Leicester, 25th September 1997. 2. Goodman R.L., John Hottenroth and Scott E. Black, Taking Advantage of Next Generation Processing Technologies Multi-core Processors and FPGAs, Proceedings of ASNT Fall Conference 2009, Columbus, Ohio, October 19-23, 2009. 3. Lines, D.I.A., Rapid distributed data collection with arrays - the next step beyond Full Waveform Capture, INSIGHT, Vol.48, No.2, February 2006, pp.84-88. 4. Lines, D.I.A., Irene Pettigrew, Katherine Kirk, Sandy Cochran and Jesse Skramstad, Rapid Distributed Data Collection and Processing with Arrays - the next step beyond Full Waveform Capture, Proceedings of 9th Joint FAA/DoD/NASA Conference on Aging Aircraft, Atlanta, 6-9 March 2006.