University of Wisconsin - Madison EE/omp ci 352 Digital ystems Fundamentals Kewal K. aluja and u Hen Hu pring 2002 hapter 3 Part 2 ombinational Logic Design Originals by: harles R. Kime and Tom Kamisnski Modified for course use by: Kewal K. aluja and u Hen Hu Functional Blocks: Addition Binary addition occurs frequently in digital and computer systems. In this section, we: Develop a Half-Adder (HA), a 2-input bitwise addition functional block, Develop a Full-Adder (), a 3-input bitwise addition functional block, Iterate full-adders using a ripple-carry to perform parallel binary addition, and Develop a arry-look-ahead AdderLA to improve performance. hapter 3-2 2 Functional Block: Half-Adder Logic implification: Half-Adder A 2-input, -bit width binary adder that produces the following values: 0 0 + + 0 + + 0 + 0 0 0 0 0 A half adder adds two bits to produce a two-bit sum. The sum is expressed as a 0 0 0 0 sum bit, and a carry bit,. 0 0 The half adder can be specified 0 0 as a combined truth table 0 for and : The K-Map for, is: This is a pretty trivial map! By inspection: = + = = ( + ) ( + ) and = = (( ) ) These equations lead to several implementations. 2 0 3 0 2 3 hapter 3-2 3 hapter 3-2 4 Five Implementations: Half-Adder Implementations: Half-Adder We can derive following sets of equations for a half - adder: (a) = + (d) = ( + ) = (b) ( ) ( ) (c) = = = + + (e) = = ( ) = + ( + ) = (a), (b), and (e) are OP, PO, and OR implementations for. In (c), the function is used as a term in the AND- NOR implementation of, and in (d), the function is used in a PO term for. The most common half adder implementation (e) is: = = A NAND only implementation (equivalent to equation d) is: = ( + ) = (( ) ) hapter 3-2 5 hapter 3-2 6
Functional Block: Full-Adder Design: Full-Adder A full adder is similar to a half adder, but includes a carry-in bit from lower stages. Like the half-adder, it computes a sum bit, and a carry bit,. For a carry-in (Z) of zero, it is the same as the half-adder: For a carry- in (Z) of one: Z 0 0 0 0 0 0 + + 0 + + 0 + 0 0 0 0 0 Z 0 0 + + 0 + + 0 + 0 0 0 Full-Adder Function Table: Full-Adder K-Map: Z 0 3 2 4 5 7 6 Z 0 3 2 4 5 7 6 Z 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 hapter 3-2 7 hapter 3-2 8 Design: Full-Adder Implementation: Full Adder From the K-Map, we get: = Z + Z + Z + Z = + Z + Z The function is the three-bit OR function (Odd Function): = Z The arry bit is if both and are (the sum is 2), or if the sum is and a carry-in (Z) occurs. Thus can be re-written as: = + ( )Z The term is carry generate. The term is carry propagate. hapter 3-2 9 Full Adder chematic i Here,, and Z, and (from the previous pages) are A, B, i and o respectively. Also, G = Generate and P = Propagate. Note: This is really a combination of a 3-bit odd function (for = sum) and arry logic: (G = Generate) OR (P =Propagate AND i = arry In) o = G + P i A B G P o hapter 3-2 0 Parallel Binary Adders 4-bit Ripple-arry Binary Adder To add more than one bit, we "bundle" sets of logical signals together and build devices that operate on the whole set in parallel. Example: 4-bit binary adder: Adds an input vector "A(3..0) " to "B(3..0) to get a sum (3..0) thus: Output Note: the carry out of tage i arry becomes the carry in of tage i+. Description ubscript 3 2 0 Name Input arry 0 0 i Augend 0 A i Addend 0 0 B i um 0 i 0 0 i+ hapter 3-2 A four-bit Full Adder made from four -bit Full Adders: A(3) B(3) (4) (3) (2) () (0) (3) (2) Here is a Full-Adder from before: A(2) A() A(0) B(2) B() B(0) () o P i (0) G A B hapter 3-2 2 2
arry Propagation & Delay arry Look-Ahead One problem with the addition of binary numbers is the length of time to propagate the ripple carry from the least significant bit to the most significant bit. The gate-level propagation path for a 4-bit ripple carry adder of the last example: (4) Note: The "long path" is from A(0) or B(0) though the network to either (4) or (3). A(3) B(3) (3) A(2) A() A(0) B(2) B() B(0) (3) (2) () (2) () (0) (0) hapter 3-2 3 Given tage i from a Full Adder, we know that there will be a carry generated when A i = B i = "", whether or not there is a carry-in. Alternately, there will be a carry propagated if the Gi "Half-um" is "" and a carry-in, i occurs. These two signal conditions are called Generate denoted as G i, and Propagate denoted as P i respectively and are shown here: i+ Ai Bi i Pi i hapter 3-2 4 arry Look-Ahead (ontinued) arry Look-Ahead (ontinued) By defining the equations for the Full Adder in term of the P i and G i, we have: P i = Ai Bi Gi = Ai Bi And the output sum (i) and carry (i+) is defined as: i = Pi i i+ = Gi + Pi i tarting the stage numbering at zero, we have: 4 = G3 G2 G P G0 P P0 0 where 0 is a carry in to the least significant bit. Look at the following addition examples, all of which generate a carry of out of the third stage: xxx +xxx xxxx xx +0xx 0xxx x +00x 00xx +000 000x +0000 0000 Generate a carry in tage3. Generate a carry in tage 2 and propagate it through stage 3. Generate a carry in tage and propagate it through stage 2 & stage 3. Generate a carry in stage 0 and propagate it through tage, stage 2, & stage 3. Use a carry into stage 0 and propagate it through stage 0, tage, stage 2 & stage 3. hapter 3-2 5 hapter 3-2 6 Group arry Look-Ahead Logic omplements Figure 3-28 in the text shows how to implement a carry lookahead circuit for four bits. This could be extended to more than four bits. In practice, though, it becomes more difficult to implement this over more than a few bits. The concept can be extended another level by considering a Group Generate (G 0-3 ) and Group Propagate (P 0-3 ) logic condition: G0-3 = G3 G2 G P P0 G0 P0-3 = P3 P P0 Using these two equations: 4 = G0-3 + P0-30 Thus, it is possible to have four 4-bit adders use one of the same carry look-ahead circuits to add 6 bits! ubtraction of numbers requires a different algorithm from that for addition Adding the complement of a number is equivalent to subtraction We will discuss two complements: Diminished Radix omplement Radix omplement ubtraction will be done by adding the complement of the subtrahend hapter 3-2 7 hapter 3-2 8 3
Diminished Radix omplement Given a number N in Base r having n digits, the (r ) s-complement (called the Diminished Radix omplement) is defined as: (r n ) N Example: For r = 0, N = 2340, n = 4 (4 digits),we have: (r n ) = 0,000 = 99990 The 9's complement of 2340 is then: 99990-2340 = 87650 Binary 's omplement For r = 2, N = 000 2, n = 8 (8 digits): (r n ) = 256 - = 255 0 or 2 The 's complement of 000 2 is then: 000 00000 ince the 2 n factor consists of all 's and since 0 = and = 0, the one's complement is obtained by complementing each individual bit(bitwise NOT). hapter 3-2 9 hapter 3-2 20 Radix omplement Binary 2's omplement Given a number N in Base r having n digits, the r's complement (called the radix complement) is defined as: r n N for N 0 and 0 for N = 0 The radix complement is obtained by adding to the diminished radix complement Example: For r = 0, N = 234 0, n = 4 (4 digits), we have: r n = 0,000 0 The 0's complement of 234 is then 0,000-234 = 8766 0 or 8765 + (9's complement plus ) For r = 2, N = 000 2, n = 8 (8 digits), we have: (r n ) = 2560 or 000000002 The 2's complement of 000 is then: 00000000 000 0000 Note the result is the 's complement plus hapter 3-2 2 hapter 3-2 22 Alternate 2 s omplement ubtraction with Radix omplements Given: an n -bit binary number, beginning at the right and proceeding left: opy all least significant 0 s opy the first omplement all bits thereafter. 2 s omplement Example: 00000 opy underlined bits: 00 and complement bits to the left: 0000 For n-digit, unsignednumbers M and N, find M - N in base r: Add the r's complement of the subtrahend N to the minuend M: M + (r n - N) = M - N + r n If M > N, the sum produces end carry r n which is discarded; from above, M - N remains. If M < N, the sum does not produce an end carry and, from above, is equal to r n - ( N - M ), the r's complement of ( N - M ). To obtain the result - (N M), take the r's complement of the sum and place a - in front. hapter 3-2 23 hapter 3-2 24 4
Unsigned 0 s omplement ubtraction Example Unsigned 0 s omplement ubtraction Example 2 Find 543 0 23 0 543 543 23 0 s comp + 877 420 The carry of indicates that no correction of the result is required. Find 23 0 543 0 23 0 23 0 s comp 543 + 457 0 s comp 580 520 The carry of 0 indicates that a correction of the result is required. Result = (520) hapter 3-2 25 hapter 3-2 26 Unsigned 2 s omplement ubtraction Example Unsigned 2 s omplement ubtraction Example 2 Find 00000 2 00000 2 00000 00000 00000 2 s comp+ 00 000000 The carry of indicates that no correction of the result is required. Find 00000 2 00000 2 00000 000000 00000 2 s comp+ 0000 2 s comp 0 000000 The carry of 0 indicates that a correction of the result is required. Result = (000000) hapter 3-2 27 hapter 3-2 28 ubtraction with Diminished Radix omplement Unsigned s omplement ubtraction Example For n-digit, unsigned numbers M and N, find M - N in base r: Add the (r - )'s complement of the subtrahend N to the minuend M: M + (r n - - N) = M - N + r n - If M > N, the result is excess by r n -. The end carry r n when discarded removes r n, leaving a result short by. To fix this shortage, whenever and end carry occurs we all in the LB position. This is called end-around carry. If M < N, the sum does not produce an end carry and, from above, is equal to r n - - ( N - M ), the r - 's complement of ( N - M ). To obtain the result - (N M), take the r - 's complement of the sum and place a - in front. Find 00000 2 00000 2 00000 00000 00000 s comp+ 000 0000000 + 000000 The end-around carry occurs. hapter 3-2 29 hapter 3-2 30 5
Unsigned s omplement ubtraction Example 2 igned Integers Find 00000 2 00000 2 00000 000000 00000 s comp+ 000 s comp 00 000000 The carry of 0 indicates that a correction of the result is required. Result = (000000) hapter 3-2 3 Positive numbers and zero can be represented by unsigned n-digit, radix r numbers. We need a representation for negative numbers. To represent a sign (+ or ) we need exactly one more bit of information ( binary digit gives 2 = 2 elements which is exactly what is needed). ince computers use binary numbers, by convention, (and, for convenience), the most significant bit is interpreted as a sign bit: s a n 2 a 2 a a 0 where: s = 0 for Positive numbers s = for Negative numbers and a i = 0 or represent in some form the magnitude. hapter 3-2 32 igned Integer Representations igned-magnitude here the n digits are interpreted as a positive magnitude. igned-omplement here the digits are interpreted as the rest of the complement of the number. There are two possibilities here: igned One's omplement Uses 's omplement Arithmetic igned Two's omplement Use 2's omplement Arithmetic igned Integer Representation Example r =2, n=3 Number ign-mag. 's omp. 2's omp. +3 0 0 0 +2 00 00 00 + 00 00 00 +0 000 000 000 0 00 0 0 2 0 0 0 3 00 0 4 00 hapter 3-2 33 hapter 3-2 34 igned-magnitude Arithmetic igned-omplement Arithmetic Addition: If signs are the same:. Add the magnitudes. 2. heck for overflow (a carry into the sign bit). 3. The sign of the result is the same. If the signs differ:. ubtract the subtrahend from the minuend 2. If a borrow occurs, take the two s complement of result and make the sign the complement ofthe sign of the minuend. 3. Overflow will never occur. ubtraction: omplement the sign bit of the number you are subtracting and follow the rules for addition. hapter 3-2 35 Addition:. Add the numbers including the sign bits, discarding a carry out of the sign bits (2's omplement), or using an end-around carry ('s omplement). 2. If the sign bits were the same for both numbers and the sign of the result is different, an overflow has occurred. 3. The sign of the result is computed in step. ubtraction: Form the complement of the number you are subtracting and follow the rules for addition. hapter 3-2 36 6
Examples igned-magnitude arithmetic igned 2 s complement arithmetic igned s complement arithmetic 2 s omplement Adder/ubtractor ubtraction can be accomplished by addition of the Two's omplement.. omplement each bit (One's omp.) 2. Add one to the result. The following circuit computes A - B: When the arry-in is, the 2 s comp of B is formed using ORs to form the s comp and adding the on (0). A(3) B(3) A(2) A() A(0) B(2) B() B(0) (0) (4) (3) (2) () o x y i hapter 3-2 37 (3) (2) () (0) hapter 3-2 38 Overflow Detection and comments Overflow detection example omments on hardware for ign-magnitude omplement-based Overflow detection hardware Binary Multiplication The binary digit multiplication table is trivial: (a b) b = 0 b = a = 0 0 0 a = 0 This is simply the Boolean AND function. Form larger products the same way we form larger products in base 0. hapter 3-2 39 hapter 3-2 40 Review of Decimal Multiplication Example: (237 x 49) Base 0 Perform base 0 multiplication by: omputing partial products, and Justifying and summing the partial products. To compute partial products: Multiply the row of multiplicand digits by each multiplier digit, one at a time. Partial product formation here require carries to be added more complex than binary Partial products are: 237 9, 237 4, and 237 Note that the partial product summation for n digit, base 0 numbers requires adding up to n digits (with carries). Note also n x m digit multiply generates up to an m+n digit result. 2 3 7 4 9 2 3 3 9 4 8 - + 2 3 7 - - 3 5 3 3 hapter 3-2 4 hapter 3-2 42 7
Binary Multiplication Algorithm We compute base 2 multiplication by: omputing partial products, and Justifying and summing the partial products. (same as decimal!) To compute partial products: Multiply the row of multiplicand digits by each multiplier digit, one at a time. With binary numbers, partial products are very simple! They are either: all zero (if the multiplier digit is zero), or the same as the multiplicand (if the multiplier digit is one). Note: No carries are added in partial product formation! hapter 3-2 43 Example: (0 x 0) Base 2 Partial products are: 0 x 0, 0 x, and 0 x Note that the partial product summation for n digit, base 2 numbers requires adding up to n digits (with carries) 0 in a column. 0 0 0 Note also n x m digit multiply generates up to an m + n digit result (same as decimal). 0 0 0 0 0 hapter 3-2 44 Multiplier Boolean Equations Multiplier Arrays Using Adders We can also make an n x m "block" multiplier and use that to form partial products. Example: 2 x 2 The logic equations for each partial-product binary digit are shown below: We need to "add" the columns b b 0 to get the product bits P0, a a 0 P,, and P3. (a 0 b ) (a 0 b 0 ) + (a b ) (a b 0 ) Note that some P 3 P 2 P P 0 columns may generate carries. An implementation of the 2 x 2 multiplier array is shown (Figure 3-33): A B HA o A B HA o b b0 a0 a hapter 3-2 45 P3 P P0 hapter 3-2 46 Multiplier Using Wide Adders A more "structured" way to develop an n m multiplier is to sum partial products using adder trees The partial products are formed using an n m array of AND gates Partial products are summed using m adders of width n bits Example: 4-bit by 3-bit adder Text Figure 3-34 shows a 4 3 = 2 element array of AND gates and 2 4-bit adders ellular Multiplier Arrays Another way to implement multipliers is to use an n m cellular array structure of uniform elements as shown: Each element computes a single bit product arry [ j, k ] equal to a i b j, and implements a single bit full adder olumn um from above ell [ j, k ] pp [ j, k ] b[ k ] a[ j ] A B arry [ j, (k - )] olumn um to below hapter 3-2 47 hapter 3-2 48 8
BD Addition A four-bit binary adder, with a correction circuit, can be used for BD digit addition. For the correction circuit: The BD code is correct if the sum is 9 or less The BD code is incorrect: if the adder output is 0,,2,3,4,5, or if the 4-bit adder produces a carry out We correct the sum by subtracting 0 (usually by the equivalent addition of 6 modulo 6) The Boolean equation with value for doing a correction: = K + Z Z 3 + Z2 Z3 If =, 00 is added; else 0000 is added. This can be done by adding 0 0. Also is the Output carry. BD Addition (ontinued) The resulting circuit (Figure 3-35): hapter 3-2 49 hapter 3-2 50 Overview of Verilog Part Objectives Objectives Verilog Basics Notation Keywords & onstructs Operators Types of Descriptions tructural Dataflow Boolean Equations onditions using Binary ombinations onditions using Binary Decisions Behavioral & Hierarchical Process (Procedural) not discussed To become familiar with the hardware description language (HDL) approach to specifying designs Be able to read a simple Verilog HDL description Be able to write a simple Verilog HDL description using a limited set of syntax and semantics Understanding the need for a hardware view when reading and writing an HDL hapter 3-2 5 hapter 3-2 52 Verilog Notation - Verilog Notation - 2 Verilog is: ase sensitive Based on the programming language omments ingle Line // [end of line] Multiple Line /* */ List element separator:, tatement terminator: ; Binary Values for onstants and Variables 0,x Unknown Z,z High impedance state (open circuit) onstants n b[integer]: b =, 8 b = 00000000, 4 b00= 00, 8 bxxxxxxxx, 8 bxxxx = 0000xxxx n h[integer]: 8 ha9 = 0000, 6 hf= 00000000000 Identifier Examples calar: A,,RUN,stop,m,n Vector: sel[0:2], f[0:5], A[3:0], UM[5:0], sum[5:0] hapter 3-2 53 hapter 3-2 54 9
Verilog Keywords & onstructs - Keywords are lower case module fundamental building block for Verilog designs Used to construct design hierarchy annot be nested ends a module not a statement => no ; Module Declaration module module_name (module_port, module_port, ); Example: module full_adder (A, B, c_in, c_out, ); Verilog Keywords & onstructs - 2 Input Declaration calar input list of input identifiers; Example: input A, B, c_in; Vector input[range] list of input identifiers; Example: input[5:0] A, B, data; Output Declaration calar Example: output c_out, OV, MINU; Vector Example: output[7:0] A, REG_IN, data_out; hapter 3-2 55 hapter 3-2 56 Verilog Keywords & onstructs - 3 Verilog Operators - Primitive Gates buf, not, and, or, nand, nor, xor, xnor yntax: gate_operator instance_identifier (output, input_, input_2, ) Examples: and A (F, A, B); //F = A B or O (w, a, b, c) O2 (x, b, c, d, e); //w=a+b+c,x=b+c+d+e Bitwise Operators ~ NOT & AND OR ^ OR ^~ or ~^ NOR Example: input[3:0] A, B; output[3:0] Z ; assign Z = A ~B; hapter 3-2 57 hapter 3-2 58 Verilog Operators - 2 tructural Verilog Arithmetic Operators +, -, (plus others) Logical & Relational Operators!, &&,, = =,!=, >=, <=, >, < (plus others) oncatenation & Replication Operators {identifier_, identifier_2, } {n{identifier}} Examples: {REG_IN[6:0],erial_in}, {8 { b0}} ircuits can be described by a netlist as a text alternative to a diagram - Example (ee Figure 3-59 in text): module fig359s (A0, B0, 0,, 0); input A0, B0, 0; output, 0; //even internal wires needed wire[:7] N; //Ports on primitive gates listed output port first not G (N[3],0), G2 (N[5],N[2]), G3 (N[6],N[3]); nand G4 (N[],A0,B0); nor G5 (N[2],A0,B0), G6 (,N[2],N[4]); and G7 (N[4],N[],N[3]), G8 (N[7],N[],N[5]); xor G9 (0,N[6],N[7]); hapter 3-2 59 hapter 3-2 60 0
Dataflow Verilog - Dataflow Verilog - 2 ircuit function can be described by assignstatements using Boolean equations (ee Figure 3-59 in text): module fig359d (A0, B0, 0,, 0); input A0, B0, 0; output, 0; wire[:2] N; assignn[] = ~(A0 & B0); /*Note: annot write ~& for NAND */ assignn[2] = ~(A0 B0); assign = ~((N[] & ~0) N[2]); assign0 = (~N[2] & N[])^(~(~0)); hapter 3-2 6 ircuit function can be described by assignstatements using the conditional operator with binary combinations as in a truth table (ee Figure 3-4 in text): module fig34dm (A, E_n, D_n); input[:0] A; input E_n; output[3:0] D_n; //onditional: ()? : Z - if is true, then,else Z assign D_n = {4{E_n}}&( (A == 2'b00)? 4'b0: (A == 2'b0)? 4'b0: (A == 2'b0)? 4'b0: (A == 2'b)? 4'b0: 4'bxxxx); hapter 3-2 62 Dataflow Verilog - 3 Behavioral & Hierarchical Verilog ircuit function can be described by assignstatements using the conditional operator for binary decisions on inputs(ee Figure 3-4 in text): module fig34dc (A, E_n, D_n); input[:0] A; input E_n; output[3:0] D_n; /* onditional: ()? : Z - if is true, then,else Z */ assignd_n = {4{E_n}} & (A[]? (A[0]? 4'h7 : 4'hB): (A[0]? 4'hD : 4'hE)); ircuit function can be described by assignstatements at higher than the logic level (ee Figure 3-3 in text): module addsub (A, B, R, sub) ; input [3:0] A, B ; output [3:0] R ;//ee Fig. 3-5 for carry out input sub ; wire [3:0] data_out; add A (A, data_out, sub, R); Mcomp (B, data_out, sub); hapter 3-2 63 hapter 3-2 64 Behavioral & Hierarchical Verilog ummary module add (,, _in, ); input [3:0], ; input _in; output [3:0] ; assign = + + {3'b0, _in}; module Mcomp (data_in, data_out, comp); input[3:0] data_in; input comp; output [3:0] data_out; assigndata_out = {4{comp}} ^ data_in; Analysis Forward backward trace through the circuit to obtain output equations or truth table Vice versa will also find the equations and truth table Know the functions performed by the following functional blocks: Decoders, Demultiplexers, Encoders, Multiplexers Know how to implement Boolean functions using: Multiplexers Decoders hapter 3-2 65 hapter 3-2 66