An Efficient Implementation of Fixed-Point LMS Adaptive Filter Using Verilog HDL

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1 An Efficient Implementation of Fixed-Point LMS Adaptive Filter Using Verilog HDL 1 R SURENDAR, PG Scholar In VLSI Design, 2 M.VENKATA KRISHNA, Asst. Professor, ECE Department, 3 DEVIREDDY VENKATARAMI REDDY ASSOCIATE.professor, HOD ECE Department, 1 rsuree13@gmail.com, 2 venkatakrishna.mandala@gmail.com, 3 dvenkataramireddy@gmail.com, Madhira Institute of Technology And Sciences, kodad, Nalgonda, Telangana. Abstract In this paper, we present the design optimization of one- and two-dimensional fullypipelined computing structures for area-delaypower-efficient implementation of finite impulse response (FIR) filter by systolic decomposition of distributed arithmetic (DA)- based inner-product computation. The systolic decomposition scheme is found to offer a flexible choice of the address length of the lookup-tables (LUT) for DA-based computation to decide on suitable area-time trade-off. It is observed that by using smaller address-lengths for DA-based computing units, it is possible to reduce the memory-size but on the other hand that leads to increase of adder complexity and the latency. For efficient DA-based realization of FIR filters of different orders, the flexible linear systolic design is implemented on a Xilinx Virtex-E XCV2000E FPGA using a hybrid combination of Handel-C and parameterizable VHDL cores. Various key performance metrics such as number of slices, maximum usable frequency, dynamic power consumption, energy density and energy throughput are estimated for different filter orders and address-lengths. Analysis of the results obtained indicate that performance metrics of the proposed implementation is broadly in line with theoretical expectations. It is found that the choice of address-length M=4 yields the best of area-delaypower-efficient realizations of the FIR filter for various filter orders. Moreover, the proposed FPGA implementation is found to involve significantly less area-delay complexity compared with the existing DA-based implementations of FIR filter. Keywords: Finite impulse response (FIR) filter, linear convolution, systolic array, field programmable gate arrays (FPGA),distributed arithmetic I. Introduction Finite impulse response (FIR) digital filters are extensively used due to their key role in various digital signal processing (DSP) pplications [1], [2]. Along with the advancement in very large scale integration (VLSI) technology as the DSP has become increasingly popular over the years, the highspeed realization of FIR filters with less power consumption has become much more demanding. Since the complexity of implementation grows with the filter order and the precision of computation, real-time realization of these filters with desired level of accuracy is a challenging task. Several attempts have, therefore, been made to develop dedicated and reconfigurable architectures for realization of FIR filters in application specific integrated circuits (ASIC) and field programmable gate arrays (FPGA) platforms. Systolic designs represent an attractive architectural paradigm for efficient hardware implementation of computation-intensive DSP applications, being supported by the features like simplicity, regularity and modularity of structure. Additionally, they also possess significant potential to yield high-throughput rate by exploiting high-level of concurrency using pipelining or parallel processing or both [3]. To utilize the advantages of systolic processing, several algorithms and architectures have been suggested for systolization of FIR filters [4] [7]. However, the multipliers in these structures require a large portion of the chiparea, and consequently enforce limitation on the maximum possible number of processing elements (PEs) that can be accommodated and the highest order of the filter that can be realized. Multiplierless distributed arithmetic (DA)-based technique, has gained substantial popularity, in recent years, for their high-

2 throughput processing capability, and increased regularity which results in cost-effective and area-time efficient computing structures. The main operations required for DA-based computation of inner-product are a sequence of look-up-table (LUT)-accesses followed by shift accumulation operations of the LUT output. DA-based computation is well-suited for FPGA realization, because the LUT as well as the shiftadd operations can be efficiently mapped to the LUT-based FPGA logic structures. In FIR filtering, one of the convolving sequences is derived from the input samples while the other sequence is derived from the fixed impulse response coefficients of the filter. This behavior of FIR filter makes it possible to use DA-based technique for memory-based realization. It yields faster output compared with the multiplier-accumulator-based designs because it stores the pre-computed partial results in the memory elements [8], which can be read out and accumulated to obtain the desired result. The memory requirement of DA-based implementation for FIR filters, however, increases exponentially with the filter order. DA was first introduced by Croisieret al [9]; and further developed by Peled and Lui [10] for efficient implementation of digital filters. Attempts are made to use offset-binary coding [11] to reduce the ROM size by a factor of 2. An LUT-less adder-based DA approach has been suggested by Yoo and Anderson, where memory-space is reduced at the cost of additional adders [12]. Memory-partitioning and multiple memory-bank approach along with flexible multi-bit data-access mechanisms are suggested for FIR filtering and inner-product computation in order to reduce the memorysize of DA-based implementation [13] [17]. Allredet alhave suggested an efficient DA-based implementation of least mean square (LMS) adaptive filter using a decomposition of DAbased FIR computation and subsequent memory decomposition [18]. All these structures, however, are not suitable for implementation of the FIR filters in systolic hardware since the partial products available from the partitioned memory modules are summed together by a network of output adders. A new tool for the automatic generation of highly parallelized FIR filters based on PARO design methodology is presented in [19], where the authors have performed hierarchical partitioning in order to balance the amount of local memory with external communication, and they have achieved higher throughput and smaller latencies by partial localization. A systolic decomposition technique is suggested in a recent paper for memory-efficient DA-based implementation of linear and circular convolutions [20]. In this paper we have extended further the work of [20] to obtain an area-delay-power-efficient implementation of FIR filter in FPGA platform. II. Adaptive Algorithms There are numerous methods for the performing weight update of an adaptive filter. There is the wiener filter, which is the optimum liner filter in terms of mean squared error, and several algorithms that attempt to approximate it, such as the method of steepest descent. There is also least-mean square algorithm, developed by Windrow and Hoff originally for use in artificial neural networks. Finally, there are other techniques such as the recursive-least square algorithm and the kalman filter. The choice of algorithm is highly dependent on the signals of interest and the operating environment, as well as the convergence time required and computation power available. A. Least Mean Square Algorithm The least mean square (LMS) algorithm is similar to the method of steepest-descent in that it adapts the weights by iteratively approaching the MSE minimum. Windrow and Hoff invented this technique in 1960 for use in training neural networks. The key is that instead of calculating the gradient at every time step, the LMS uses a rough approximation to the gradient. The structure of general LMS adaptive filter is shown in figure 1. Figure 1 LMS adaptive filter B. Delayed Least Mean Square Algorithm

3 A lot of work has been done to implement the DLMS algorithm in systolic architecture to increase the maximum usable frequency but, they involve an adaptation delay of N cycles for filter length N, which is quite high for larger order filters. Since the convergence performance degrades considerably for a large adaptation delay. We use a modified systolic architecture to reduce the adaptation delay. A transpose form LMS adaptive filter is suggested in, where the filter output at any instant depends on the delayed version of weights and the number of delays shown in figure 2. is the number of weights used in the LMS adaptive filter. When we have m cycles in the structure then (n-m) iterations are possible for given structure. Assuming that the latency of computation of error is n1 cycles, the error computed by the structure at the nth cycle is Update equation of the modified DLMS algorithm is given as Figure 2 Delayed LMS adaptive filter The weights of LMS adaptive filter during the nth iteration are updated according to the following equation The error at the output can be expressed as Where the input vector Xn, and the weight vector Wn at the nth iterations are, respectively, given by Dn is the desired response, Yn is the filter output and e n denotes the error computed during the nth iteration. µ is the step-size, and N Several methods have been adopted for implementing the LMS adaptive filters in the recent years. The multiplier based implementation require more number of MAC blocks as the filter order increases hence the complexity of implementation also increases. The memory based approach has high throughput processing capability and increased regularity which results in costeffective and area- time efficient computing structures. Here we are going to implement the fixed point implementation and optimization of the proposed DLMS adaptive filter. Adder tree is also proposed to reduce the hardware complexity without noticeable degradation of steady state MSE. The normalized LMS filter differs from conventional LMS filter in the way in which the step size for controlling the adjustments to the filters tap weight vector is defined. Where as in conventional the step size is a scalar parameter denoted by µ. The two important advantages are folded below. 1. The normalized LMS filter mitigates the gradient noise amplification problem, which can arise when tap input vector is large.

4 2. The rate of convergence of the normalized LMS filter is potentially faster than that of conventional LMS filter for both correlated and uncorrelated data. Adaptive noise canceller operating on a narrowband interfering signal component, a strong coupling develops between tap-weight vector filter and interfering signal, with the result that the mean square error of the LMS filter may be reduced below than that of the wiener filter. III. DLMS Algorithm The generalized DLMS is introduced in order to obtain an efficient LMS algorithm in VLSI circuits. It is well known that a pipelined architecture helps the efficient implementation of the LMS algorithm. This type of architecture requires delays in the processing. In this work, different types of delays are introduced into the architecture of LMS algorithm. The influence of these delays on the algorithm behavior is analyzed theoretically and by simulation. A. Error Computation Block The structure for error-computation unit of an N-tap DLMS adaptive filter is shown in fig 3. It consists of N number of 2-b partial product generators (PPG) corresponding to N multipliers and a cluster of L/2 binary adder trees, followed by a single shift add tree. Figure 3 Error Computation Block B.Partial Product Generator It consists of L/2 number of 2-to-3 decoders and the same number of AND/OR cells (AOC) shown in figure 4. Each of the 2-to-3 decoders takes a 2-b digit (u1u0) as input and produces three outputs b0 = u0.u1, b1 =.u0 u1, and b2 = u0 u1, such that b0 = 1 for (u1u0) = 1, b1 = 1 for (u1u0) = 2, and b2 = 1 for (u1u0) = 3. The decoder output b0, b1 and b2 along with w, 2w, and 3w are fed to an AOC, where w, 2w, and 3w are in 2 s complement representation and sign- extended to have (W + 2) bits each. To take care of the sign of the input samples while computing the partial product corresponding to the most significant digit (MSD), i.e.,(ul 1uL 2) of the input sample, the AOC (L/2 1) is fed with w, 2w, and w as input since (ul 1uL 2) can have four possible values 0, 1, 2, and 1.

5 Figure 4 Partial Product Generators C.AND OR Cells Each AOC consists of three AND cells and two OR cells. The structure and function of AND cells and each AND cell takes an n-bit input D and a single bit input b, and consists ofn AND gates. It distributes all the n bits of input D to its n AND gates as one of the inputs. The other inputs of all the n AND gates are fed with the single bit input b. each OR cell similarly takes a pair of n-bit input words and has n OR gates. A pair of bits in the same bit position in B and D is fed to the same OR gate. The output of an AOC is w, 2w, and 3wcorresponding to the decimal values 1, 2, and 3 of the 2-b input (u1u0), respectively. The decoder along with the AOC performs a multiplication of input operand w with a 2-b digit(u1u0), such that the PPG of Fig. 5 performs L/2 parallel multiplications of input word w with a 2-b digit to produce L/2 partial products of the product word wu. D.Adder Tree Figure 5 AND OR Cells Conventionally, the shift-add operation should performed on each PPG separately to obtain the product value and then added all the N product values to compute the desired inner product. However, the shift-add operation to obtain the product value increases the word length, and consequently increases the adder size of N 1 additions of the product values. To avoid such increase in word size of the adders, we add all the N partial products of the same place value from all the N PPGs by one adder tree as shown in figure 6. All the L/2 partial products generated by each of the N PPGs are thus added by (L/2) binary adder trees. The outputs of the L/2 adder trees are then added by a shift-add tree according to their place values. Each of the binary adder trees require log2 N stages of adders to add N partial product, and the shift add tree requires log2l 1 stages of adders to add L/2 output of L/2 binary adder trees.

6 Figure 6 Adder Trees E.Weight Update Block The weight-update block is shown in fig 7. It performs N multiply-accumulate operations of the form (µ e) xi+ wi to update N filter weights. The step size µ is taken as a negative power of 2 to realize the multiplication with recently available error only by a shift operation. Each of the MAC units therefore performs the multiplication of the shifted value of error with the delayed input samples xi followed by the additions with the corresponding old weight values wi. All the N multiplications for the MAC operations are performed by N PPGs, followed by N shift add trees. Each of the PPGs generates L/2 partial products corresponding to the product of the recently shifted error value µ e with L/2, the number of 2-b digits of the input word xi, where the sub expression 3µ e is shared within the multiplier. Since the scaled error (µ e) is multiplied with the entire N delayed input values in the weight update block, this sub expression can be shared across all the multipliers as well. This leads to substantial reduction of the adder complexity. The final outputs of MAC units constitute the desired updated weights to be used as inputs to the error computation block as well as the weight- update block for the next iteration Figure 7 Weight Updated Block F. Adaption Delay As show in fig 3, the adaption delay is decomposed into n1 and n2. The error computation block generates delayed error byn1-2 cycles, which is fed to the weight update block as shown in fig 3.5 after scaling by µ; then the input is delayed by one cycle before the PPG to make the total delay introduced by FIR filtering be n1. The weight update block generates Wn-1-n2, and the weights are delayed by n2+1 clock cycles. However it should be noted that the delay by one clock cycle is due to latch before the partial product generator, which is included in the delay of error computation block, i.e. n1. Therefore the delay generated in weight update block becomes n2. G. Fir Filter The FIR filter is a circuit that filters a digital signal (samples of numbers) and provides an output that is another digital signal with characteristics that are dependent on the response of the filter. The FIR filter is non recursive. It uses a finite duration of none zero input values and produces a finite duration of output values which are non-zero. FIR filters use addition to calculate their outputs just like averaging does. The primitive elements used in the design of a FIR filter are delays, multipliers and adders. The FIR filter consists of a series of delays, multiplications and additions to produce the

7 time domain output response. The impulse response of the FIR filter is the multiplication coefficients used. The phase of a FIR filter is linear. This is a dominant feature of the FIR filter. The frequency response of the FIR filter is the DFT (Discrete Fourier Transform) of the filters impulse response. H. Multipliers A multiplier that accept two numbers in digital form and gives their product in the same digital form, usually by making repeated additions; the multiplying process is simpler if the numbers are in binary form wherein digits are represented by a 0 or 1. A binary multiplier is an electronic circuit used in digital electronics, such as a computer, to multiply two binary numbers. It is build using binary adders. A variety of computer arithmetic techniques can be used to implement a digital multiplier. Most techniques involve computing a set of partial products, and then summing the partial products together. This process is similar to the method taught to primary school children for conducting long multiplication on base-10integers, but has been modified here for application to a base-2 (binary) numeral system. A binary computer does exactly the same, but with binary numbers. In binary encoding each long number is multiplied by one digit (either 0 or 1), and that is much easier than in decimal, as the product by 0 or 1 is just 0 or the same number. Therefore, the multiplication of two binary numbers comes down to calculating partial products, shifting them left, and then adding together (a binary addition). This is much simpler than in decimal system, as there is no table of multiplication to remember: just shift and addition. Older multiplier architectures employed a shifter and an accumulator to sum each partial product, often one partial product per cycle. The performance of Wallace tree implementation is sometimes improved by modified booth encoding one of the two multiplicands, which reduces the number of partial products that must be summed. I. Mutiplier And Accumulator A multiplier can be divided into three operational steps. The first is encoding in which a partial product is generated from the multiplicand(x) and the multiplier(y). The second is adder array or partial product compression to add all partial products and convert them into the form of sum and carry. The last is the final addition in which the final multiplication result is produced by adding the sum and the carry. IV.Simulation Results A novel PPG for efficient implementation of general multiplication and inner product computation have been implemented in delayed least mean square adaptive filter. For achieving lower adaptation delay by using an efficient addition scheme for inner product computation and to reduce critical paths. The simulation results for LMS filter brought out by using modelsim. Fixed point implementation of the proposed architecture, and derived an expression for the steady state error. Figure 8 Simulation output result for the LMS Filter The steady state analytical MSE matched with the simulation results. The fixed point we used here is N=8. A novel PPG implementation is made in order to reduce adaptation delay by using an efficient addition scheme for inner product computation. When we enable the SA0 input we get an analog form as shown in the figure 8 for certain movement of cursor. This is a bit level. Pruning without noticeable degradation of steady state performance. DLMS adaptive filter had a shorter critical path than the traditional system. Efficient addition scheme for inner

8 product computation reduced adaption delay which improved convergence performance and reduced critical path to support high input sample rates. Optimized balanced pipelining across time consuming blocks reduced adaption delay and power consumption. Area-delay product is reduced to 16% and Energy-delay product is reduced to 14%. Figure 9 Simulation Analog output result for the LMS filter Thus the wave form for the LMS adaptive filter as shown in figure 9 has been performed using Modelsim. V.Conclusion An area delay-power efficient with low adaptation-delay architecture for fixedpoint implementation of DLMS adaptive filter are achieved by using a novel PPG for efficient implementation of general multiplications and inner-product computation by common sub expression. From this, proposed strategy an optimized balanced pipelining across the time-consuming blocks is to reduce the adaptation delay and power consumption. The proposed structure involved significantly less adaptation delay and provided significant saving of ADP and EDP compared to the existing structures. The highest sampling rate that could be supported by the ASIC implementation of the proposed design. When the adaptive filter is required to be operated at a lower sampling rate, one can use the proposed design with a clock slower than the maximum usable frequency and a lower operating voltage to reduce the power consumption further. REFERENCES [1] Sang Yoon Park, and Pramod Kumar Meher- Low-Power, HighThroughput, and Low-Area Adaptive FIR Filter Based on Distributed Arithmetic -IEEE Transaction on Circuits And System-II: Experess Briefs, Vol. 60, NO. 6, JUNE 2013 [2] Meher P.K,Park S.Y,Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter with Low Adaptation-Delay VLSI Systems,IEEE Transaction- Vol PP,Issue 99,Feb 2011 [3] Jin-GyunChung,Kesheb K.Parhi- Communication of digital filters-ieee Transaction ICCSP,Oct 2008 [4] Tsutomu, sasao, Yukihiro, lguchi, Takariho, suzuki-distributed Arithmetic FIR Filterv9.0- DS240 April 28, 2005 [5] Ricardo. A, Losada-Practical FIR Filter Design- MA 01760, USA March 31, 2003 [6] Understanding FIR (Finite Impulse Response) Filters - An Intuitive Approach by Dan Lavry, Lavry Engineering [7] S. Haykin and B. Widrow, Least-Mean- Square Adaptive Filters.Hoboken, NJ, USA: Wiley, [8] D. J. Allred, H. Yoo, V. Krishnan, W. Huang, and D. V. Anderson, LMS adaptive filters using distributed arithmetic for high throughput, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 7, pp ,Jul [9] R. Guo and L. S. DeBrunner, Two highperformance adaptive filter implementation schemes using distributed arithmetic, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 58, no. 9, pp , Sep [10] R. Guo and L. S. DeBrunner, A novel adaptive filter implementation scheme using distributed arithmetic, in Proc. Asilomar Conf. Signals,Syst., Comput., Nov. 2011, pp [11] M. D. Meyer and P. Agrawal, A modular pipelined implementation of a delayed LMS transversal adaptive filter, in Proc. IEEE Int. Symp. CircuitsSyst., May 1990, pp

9 BIOGRAPHIES Science,Kodad. Science,Kodad. D.Venkatarami Reddy. He received Masters Degree in M. Tech Embedded Systems from JNTU. He is working as Associate Professor in Madhira Institute Of Technology & M.Venkata Krishna. He received Masters Degree in M. Tech, VLSI System Design from JNTU. He is working as Assistant Professor in Madhira Institute Of Technology & R.Surendar is currently a PG scholar of VLSI Design in ECE Department. He received B.TECH degree from JNTU. His current research interest includes Analysis & Design of VLSI System Design.