An Efficient VLSI Architecture for Adaptive Rank Order Filter for Image Noise Removal

Transcription

1 International Journal of Information and Electronics Engineering, Vol. 1, No. 1, July 011 An Efficient VLSI Architecture for Adative Rank Order Filter for Image Noise Removal M. C Hanumantharaju, M. Ravishankar, D. R Rameshbabu and S. B Satish Abstract In this aer, an Efficient Very Large Scale Integration (VLSI) Architecture and Field Programmable Gate Array (FPGA) imlementation of Adative Rank Order Filter () is roosed. is a owerful techniue for denoising an image corruted by salt and eer noise. The roosed method rovides better filtering roerties then it is ossible with Adative Median Filter (). The exansion of the window size in an is based on whether the median is noisy or not. However, this criterion is not an aroriate when the noise density is moderate or high. Further the ixels rocessed by the are reused in the filtering rocess. The restored image using this scheme generally degrades the visual uality. The roosed method imlements in order to filter images with higher noise densities. The uses median ixel or median comuted from noise free ixels in order to relace noisy center ixel. The adats the window size itself when all ixels within the current window are noisy or when median itself is noisy. The VLSI architectures develoed is imlemented on Xilinx Virtex XCVP50-7ff115 FPGA device. The ielining and arallel rocessing techniues have been adated in order to seed u the filtering rocess. The exerimental results show that the roosed FPGA imlementation of has better erformance then the, when the noise density is moderate or high. The erformance of the roosed algorithm is verified by alying Peak Signal to Noise Ratio (PSNR) and Image Enhance Factor (IEF). Index Terms Adative Median Filter, Adative Rank Order Filter, FPGA, Image Noise, Pieline. I. INTRODUCTION Nowadays, digital images are usually transmitted through satellites, wired and wireless networks. However, it is uit often to introduce imulse noise in digital images during image acuisition and transmission. During transmission, images are corruted due to interference in the channel such as atmosheric disturbance. In order to rocess images for better visual uality or for further use in digital image rocessing system, the noise has to be removed. The noise reduction algorithms remove noise without degrading image Manuscrit received Aril 16, 011; revised June, 011. M. C Hanumantharaju is with the Deartment of Information Science and Pin (corresonding author hone: ; fax: ; mchanumantharaju@gmail.com). M. Ravishankar, is with the Deartment of Information Science and Pin ( ravishankarmcn@gmail.com). D. R Rameshbabu, is with the Deartment of Comuter Science and Pin ( bobrammysore@gmail.com). S. B Satish, is with the Deartment of Electronics and Communication Pin ( satishbhairannawar@gmail.com). information. One aroach to remove an imulsive noise is linear filters. But, linear filters tend to blur an image; hence they are not commonly used. Non-linear filters [1] such as median filter, order statistics filter cause little blurring and rovide more satisfactory results in comarison to linear filters. A rominent scheme to deal with salt and eer noise is the median filter and its derivatives such as Weighted Median (WM) filter, Switched Median (SM) filter, Iterative Median (IM) filter and Center Weighted Median (CWM) filter. Median filter based aroaches have low comutational comlexity, edge reserving caability and rovide good results for low noise density. However, median filter removes very fine details and sometime changes the visual uality of an image. The main reason is that the median filter uses the rank order information of the image within the filter window and discards its original temoral-order information. In addition, filter erformance deteriorates as the noise density increases. The hardware imlementation of median filter is straightforward and reuires few resources such as sliding window unit, sorting network and median comutation unit. In order to overcome the drawbacks of median filter, Hwang et al. [] roosed an. The median filter algorithm uses fixed window of 3 3, 5 5 ixels etc. However, in the window size adats according to noise density. starts with an initial window size of 3 3 ixels with the following stes: (1) check if the center ixel within the window is noisy or not. If the center ixel is noisy than sort ixels within window. Otherwise slide the window to next ixel and reeat this ste. () Check if the median is noisy or not. If the median is noisy then exand the window size and sort ixels within the window. This rocess is reeated until non-noisy median is found. (3) Relace the center ixel with the median value comuted in ste (). As the noise density increases, emloys a larger window to clean u the noise. However the uality of the restored image degrades when larger window is emloyed. The maximum allowed window size deends on the alication, but a reasonable starting value can be estimated by exerimenting with various sizes of the standard median filter first. This will establish a visual baseline regarding exectations on the erformance of the. The hardware imlementation of with filtering window 7 7 exhibits a very good erformance/cost in comarison to standard median filters. However, this filter occuies aroximately 30% of the chi area and is able to remove noise level u to 60% Yan Lu et al. [3] roosed an otimization of sorting algorithm for median filter and its FPGA imlementation. In this aer, real time median filtering using ielining technology was resented. This method otimizes only 94

2 International Journal of Information and Electronics Engineering, Vol. 1, No. 1, July 011 sorting module with less concern towards noisy ixels. Also this method may not be efficient for highly corruted images. Zdenek Vasicek et al. [4] roosed a new FPGA imlementation for. In this method, was otimized for better throughut allowing 300M ixels filtered er second at the cost of hardware comlexity. An Efficient hardware imlementation of median and weighted median filter [5] uses cumulative histogram to comute median. This scheme is indeendent of window size and the area is being determined by bit width. The architecture resented was efficient in terms of area for larger window size; however the system is slow for smaller window size due to hardware comlexity comared to other methods. Ioannis et al. [6][7] roosed a new intelligent hardware module suitable for the comutation of. The filter rocess avoids image blurring and integrity of edge is reserved along with detailed information. The digital hardware rocesses image with an 8-bit resolution, fully ielined and rocessed arallel to reduce comutation time. However, the window size of the system adatively exands as noise density increases. This rocess increases hardware comlexity and slows down the system for highly corruted images. In this work, an efficient VLSI architecture and an FPGA imlementation of is roosed. This filter removes salt and eer noise resent in images. The rovides better filtering roerties then it is ossible with. The roosed method not only removes salt and eer noise but also imroves the visual uality of an image even at higher noise densities. The imroved erformance of the roosed is measured by Peak Signal to Noise Ratio (PSNR) and Image Enhancement Factor (IEF). This aer is organized as follows: Section describes the roosed. Section 3 gives brief details of hardware imlementation. Section 4 rovides results and discussions. Finally conclusion is resented in Section 5. II. PROPOSED METHOD This aer rooses an efficient VLSI architecture and an FPGA imlementation of for image noise removal. The roosed scheme overcomes the drawback of the. The reconstructed images using are generally not satisfactory for higher noise densities. For a fixed window size, there may be some ixels which are not noisy, when the median is noisy. In such case, if the center ixel is relaced by some non-median ixel. The filter becomes a kind of adative rank orders. The reconstructed image using this method rovides better visual uality than that ossible with. In this work, window adats itself for two cases: (i) if all ixels within the current window are noisy. (ii) In order to relace center ixel with non-median ixel if the median is noisy. The roosed algorithm for adative rank order filter is as follows: 1. Read the image.. Select a window of size 3 3 at to left corner of the image. 3. Check if the center ixel within the window is noisy. If yes, then go to ste 4. Otherwise, slide the window to next ixel and reeat ste. 4. Sort all ixels within the window in an ascending order and find the minimum min, median med and maximum max. 5. Determine if med is noisy by min < med < max. If it holds, med is not a noisy ixel and go to ste 6. Otherwise, med is noisy ixel and go to ste Relace the corresonding center ixel in outut image with med and go to ste By min < med < max, check if all other ixels are noisy. If yes, then exand window and go back to ste 4. Otherwise, go to ste Relace corresonding center ixel in outut image with the noise free ixel which is the closest one to the median. 9. Reset window size and center of window to next ixel. 10. Reeat the stes until all ixels are rocessed. In order to aly for color image, the image is searated into red (R), green (G) and blue (B) color comonents. The above algorithm is reeated for each of R, G and B color comonents. III. HARDWARE IMPLEMENTATION The roosed hardware architecture is based on ieline stages in order to reduce comutation time. In addition, arallel rocessing has been emloyed to accelerate the rocess. In this work, a maximum window size is chosen as 9 9 from comutation oint of view. The to level hardware structure of the is as shown in Fig. 1. It comrises of five basic functional units, the sliding window, noise detection, sorting network, median comutation and the outut selection unit. The image inut data is laced in Random Access Memory (RAM). For every clock cycle, a ixel is read from RAM and laced into the sliding window module. Fig. 1. To level Module of A. Sliding Window Architecture The ixel values of the inut image Pixel_in of width 8-bits are imorted serially into the sliding window module. The Fig. shows the hardware architecture of 3 3 sliding window function that uses row buffers. In this work, one image ixel is read from memory in one clock cycle. The ixels are read row by row in a raster scan order. For a 3 3 sliding window, two First-In-First-Out (FIFO) buffers are used. The FIFO buffers are used to reduce the memory access to one ixel er clock cycle. The deth of the FIFO buffer is chosen as (W-3), where w is the width of the image. In order to access all values of the window for every clock cycle, the two FIFO buffers must be full. The contents of the window 95

3 International Journal of Information and Electronics Engineering, Vol. 1, No. 1, July 011 are shifted right, with the right most ixels being added to the tail of the FIFO. The to right ixel Pixel_out is disosed after the comutation on the ixel is comleted, since it is not used further. In addition, 3 3 sliding window reuires 9 registers to store ixels before it is laced into the noise detection unit. In this work, hardware design of sliding window has taken the advantage of certain features of FPGA. In order to achieve, read and write oerations of the RAM in the same clock cycle the block RAM feature of the Xilinx Vertex FPGA have been used. However, the same effect is also achieved using Look-U Table based (LUT) RAM imlementation on FPGA. But the use of block RAM is more efficient then that ossible with LUT-FPGA imlementation, since logic associated with read and write oeration is less. Similarly for 5 5 sliding window imlementation, four FIFO buffers are used. The deth of FIFO is (W-5), where w reresents width of the image. In this work, 7 7 and 9 9 sliding window are used for hardware imlementation of. generates a sorted seuence of numbers as outut. A 0-1 is called as a bitonic seuence if it contains at most two changes between 0 and 1. In bitonic sorting network an inut seuence is recursively divided into several arts. In each art bitonic seuences are created and merged in order to create another larger bitonic or sorted seuence. There is a roblem with bitonic sorting, however, resulting in it failing to be a sorting network. The outut of each smaller bitonic sorter is sorted, and two sorted seuences concatenated will not always be bitonic. In order to overcome this roblem, the bitonic sorter [11] can be modified to fli (or reverse) the second half of the inut seuence. Since both halves of the inut seuence are sorted, the inut seuence is not bitonic, but the effect of fliing the second half of the inut seuence will result in the inut seuence becoming a bitonic seuence A Batcher s odd-even merge sorting network is based on sorting two halves of the inut seuence. This is followed by merging two sorted seuence into one larger sorted seuence. The Fig. 3 shows the otimal hardware structure sorting 9 elements. Each vertical line reresents one comare and swa oeration. Fig.. Hardware Architecture for 3 3 Sliding Window B. Noise Detection Unit The ixels from the sliding window are laced into the noise detection unit. The noise detection unit checks for noisy ixels within window. If the ixels within the window are 0 or 55, then it is considered as salt and eer noise. The noise detection unit generates outut as zero for noisy ixel inut. The outut of the noise detection unit is fed into the sorting network. C. The Sorting Network A sorting network [8] is defined as a network of elementary oerations (comare and swa) that sorts all inut seuences. The fundamental building block of the sorting network is the comare and swa (sometimes called comarator). In sorting network, seuence of comarisons are fixed hence it is suitable for arallel rocessing and ielined hardware imlementation [9]. The comlexity of a sorting network is measured in two ways: cost and deth. Cost reresents the total number of comarators reuired to imlement the sorting network, while deth reresents the number of arallel oerations reuired to sort all inuts. Chosen sorting algorithm influences the number of reuired comarators. The sorting network includes additional registers for ielined rocessing. There are many ways to construct a sorting network. Batcher [10] describes two methods for constructing sorting networks: bitonic sorter and odd-even merge method. A bitonic sorter is a sorting network that accets a bitonic seuence of numbers as inut and Fig. 3. Otimal Sorting Network D. Median Comutation Unit The task of the median comutation unit is to comute the median value from noise free ixels. The noise detection unit discussed above converts all noisy ixels into 0 if its value is eual to 55. However the ixels with 0 value remains as zero. The median comutation unit oerates after the sorting unit, therefore the noisy ixels or ixels with 0 values are ignored by this module and comutes median from the noise free ixels. E. The Outut Selection Unit The outut selection unit works on riority basis. The comarator outut of the first row is checked for noisy. If the first row comarator outut is noisy then control jums to second row comarator outut. This rocess is followed u to fourth row. Aart from the above described hardware structures, also uses additional logic. IV. RESULTS AND DISCUSSIONS The hardware imlementation of were described in Verilog, simulated using ModelSim Version SE 6.4 and synthesized using Xilinx ISE tools Version 9.i to Vertex XCVP50-7ff115 FPGA device. Fig. 4 shows the results for Lena, House, and Tiger images with different 96

4 International Journal of Information and Electronics Engineering, Vol. 1, No. 1, July 011 noise levels. In order to evaluate the erformance of the roosed method, PSNR [1] and IEF [13] is used: Ens. (1) & (3) 55 PSNR = 10 log 10 MSE The imlementation costs are exressed in terms of number of slices. Table I rovides synthesis results of various sorting network architectures. The sorting network imlemented using odd-even merge sort reuires fewer slices then the bitonic sorting network. However, are imlemented as ieline circuits with the maximal degree of arallelism. (1) The Mean Suare Error (MSE) is given by En. () MSE = ( E ( x, y ) I ( x, y ) ) TABLE I: SYNTHESIS RESULTS OF SORTING NETWORKS () Target device : XCVP50-7ff115 Available Slices : 3616 where E(x, y) is the enhanced gray ixel at osition (x, y), I(x, y) is the original gray ixel at osition (x, y) and, and denote the size of the gray image. No. of inuts Bubble sort Number of slices used Bitonic Batcher s Otimal sort odd-even sorting merge sort Max. fre. (MHz) V. CONCLUSIONS In this aer, FPGA imlementation of for salt and eer noise removal is resented. Adative rank order filter rovides better filtering roerties than. The uses median value in order to relace noisy center ixel. However the uses median ixel or median comuted from noise free ixels for the relacement of noisy center ixel. In, window exansion is based on the criterion of whether the median is noisy or not while the checks if all ixels within the window are noisy. The reuses the ixels which are relaced by median while the avoids it. The exerimental results show that the restored images with higher noise densities based on are better in visual uality than that is achieved using. The erformance of the roosed method is verified by alying eak signal to noise ratio and image enhancement factor. Currently research work is under rogress for filtering aerial images and medical images. The detailed architecture of the roosed is shown in Fig. 5. Fig. 6 shows the Modelsim simulation results for 5 5 window. Finally, the routed FPGA design is shown in Fig. 7. First column: Noisy and Restored images with 50% noise density; Second column: Noisy and Restored images with 70% noise density; Third column: Noisy and Restored images with 90% noise density. Fig. 4. Results of Grey images Lena, House and Tiger The Image Enhancement Factor (IEF) is exressed as: IEF = ( n( x, y) I ( x, y) ) ( f ( x, y) I ( x, y) ) (3) n(x, y) is the noisy image, I(x, y) is the original image and f(x, y) is the filtered image. Fig. 5. Detailed Architecture of Proosed 97

5 International Journal of Information and Electronics Engineering, Vol. 1, No. 1, July 011 REFERENCES [1] [] [3] [4] [5] Fig. 6. ModelSim (Ver. SE 6.4) Simulation Results for 5 5 Window [6] [7] [8] [9] [10] Fig. 7. Imlementation on Xilinx FPGA XCVP50-7ff115 Device [11] TABLE II: PSNR FOR AND WITH VARIOUS NOISE DENSITIES [1] Peak Signal to Noise Ratio (PSNR) Lena House Tiger Noise Density 10% % % % % % % % % [13] [14] TABLE III: IEF FOR AND WITH VARIOUS NOISE DENSITIES Image Enhancement Factor (IEF) Lena House Tiger Noise Densit y 10% % % % % % % % % J Astola and P. Kuosmanen,Fundamentals of Nonlinear Digital Filtering, CRC Press, Boca Raton, H. Hwang and R. A. Haddad, New algorithms for adative median filters, Proceedings of Visual Communication and Image Processing, Vol. 1606, , Nov Lu, Yan Dai, Ming Jiang and Shi, Sort otimization algorithm of median filtering based on FPGA, International Conference Machine Vision and Human-Machine Interface (MVHI), , 4-5 Aril, 010. Zdenek Vasicek and Lukas Sekanina, Novel Hardware Imlementation of Adative Median Filters, in roceedings of 11th IEEE worksho on Design and Diagnostics of Electronic Circuits and Systems,. 1-6, Aril, 008. S. A Fahmy, P.Y.K. Cheung and W. Luk, Novel FPGA-based imlementation of median and weighted median filters for image rocessing, International Conference on Field Programmable Logic and Alications, , 005. Ioannis Andreadis and Gerasimos Louverdis, Real-Time Adative Image Imulse Noise Suression, IEEE transactions on Instrumentation and Measurement, Vol. 53, No. 3, , June 004. G. Louverdis,I. Andreadis and N. Paamarkos, An intelligent hardware structure for imulse noise suression, Proceedings of the 3rd International symosium on image and signal rocessing and Analysis Meena S. M and Linganagouda K, Rank based merge sorting network architecture for D median and morhological filters, IEEE International Conference on Advance Comuting, , 6-7 March, 009. C. Chakrabarti, Novel sorting based architectures for Rank order median filters, IEEE Transactions on Very Large Scale Integration Systems, Vol., No. 4, , Z. Vasicek and L. Sekanina, An evolvable hardware system in Xilinx Virtex II Pro FPGA, International Journal Innovative Comuting and Alications, Vol. 1, , 007. R. Maheshwari, S.S.S.P. Rao and E. G. Poonach, FPGA imlementation of median filter, VLSI Design, IEEE Comuter Society, , Kazimierz Wiatr, Median and Morhological Secialized rocessors for a Real Time Image Data Processing, EURASIP Journal on alied signal rocessing, 00. L. Breveglieri and V. Piuri, Digital median filters, Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, Vol. 31, No. 3, , 00. D. Richards, VLSI median filters, IEEE Transactions on Acoustics, Seech and Signal rocessing, Vol. 38, No. 1, , 1990.