CASCH - a Scheduling Algorithm for "High Level"-Synthesis

Transcription

1 CASCH a Scheduling Algorithm for "High Level"Synthesis P. Gutberlet H. Krämer W. Rosenstiel Comuter Science Research Center at the University of Karlsruhe (FZI) HaidundNeuStr. 1014, 7500 Karlsruhe, F.R.G. Phone no.: ++49/71/ , Fax no.: ++49/71/ Abstract It is the goal of the recently develoed and herewith resented scheduling algorithm to otimize the timing behaviour within automated circuit synthesis. The algorithm is a art of the CADDYSynthesisSystem (CAddy SCHeduling). Basis is a list scheduling algorithm which is controlled by a heuristic rating function. The allocated resources can be modelled in a flexible and detailed manner in order to secify comonent tyes for several different oerations as well as different comonent tyes for the same oeration. It is a secial feature of this scheduling algorithm that the assignment of oerations to comonent tyes is decided during the scheduling. Keywords: High level synthesis, Automatic scheduling, Allocation, Tye selection 1. Introduction To reduce the develoment costs of integrated circuits it is necessary to use owerful CADtools. With "High Level" synthesis the circuits behaviour can be secified at an abstract level by imerative or functional rogramming language like descritions. The data ath as well as the control are synthesized from this behavioural secification. Essential for the generation of the control is esecially the detailed time lanning for the single oerations. This lanning is a scheduling roblem. The result of the scheduling determines the timing behaviour of the circuit which is essential for the erformance.. The CADDY synthesis system An overview of the CADDY synthesis system is given in [CaKR84], [RoCa85], [CaRo89], [KrRo89], [DKNP89], [KoGD90]. The integration of scheduling into the design rocess is shown in figure 1. In the first ste the behavioural secification is translated into the intermediate format (flow grah, FG). Such an intermediate format allows different languages as inut interfaces to the synthesis system CADDY. The next ste generates the dataflow and the control flow grahs from this intermediate format. During this ste behavioural transformations like loo exansion or elimination of common subexressions are erformed. The control and the dataflow grahs are the basis for the data ath synthesis. The scheduling algorithm has to otimize the number of cycles on the basis of reviously selected resources. Based on the results of the scheduling the detailed comonent assignment together with register and bus assignment takes lace [KNRW88]. In this hase also the number of registers and busses is otimized. Finally the control can be generated. data flow grah secification language intermediate format data flow / control flow extraction data ath synthesis resource allocation scheduling comonent assignment control synthesis control flow grah to logic synthesis and layout tools Figure 1 The CADDY synthesis system. The allocation task Figure shows a dataflow grah consisting of additions and subtractions and the corresonding data deendencies. The labels to indicate mutual exclusive oerations and are extracted from the ifthenelse structure of the high level secification. erations with label are always executed and oerations with label and are mutual exclusive.

2 The oerations have to be maed onto comonents in the final circuit. Comonents are adders or ALUs etc. During the allocation task the number and the tyes of comonents are selected which determines the maximum degree of arallelism. Because scheduling otimizes the execution time on the basis of given resources, the allocation controls the area/time tradeoff between sequential or arallel designs. Figure Dataflow grah examle.1. Comonent library A comonent library has been imlemented to handle the necessary resource allocation. This library allows a detailed modelling of the roerties which are essential for the scheduling. This is on one hand the secification of comonent tyes with different seed for the same oeration and on the other hand the secification of universal comonents like ALUs which can be used for different oeration tyes. The scheduling algorithm is also able to deal with chaining, multi cycle comonents and comonents with an internal ieline. Some examles from the library are given on the following: * An examle library Comonent ultl Bit * cycles, no ieline eration UL 1 latency ut 1 Comonent ultlp Bit * cycles, ielined eration UL 1 latency 1 ut 1 Comonent adder 4 Bit * 150 ns eration ADD 14 ut Comonent ALU +/ Bit * 00/0 ns eration ADD 1 ut 1 00 eration SUB 1 ut 1 0 This flexible comonent secification allows different comonent tyes for the same kind of oeration. Since different comonent tyes can have different execution times the assignment to comonent tyes highly influences the scheduling. n the other hand an otimized tye selection deends on the number and the tye of the oerations lanned in each clock cycle and this is a result of the scheduling. It is one of the most imortant features of the here resented scheduling algorithm to resolve these mutual deendencies during the scheduling. It also should be stressed that only the assignment to comonent tyes has to be done during the scheduling. The detailed assignment of oerations to single comonents is otimized in a later hase of the CADDY synthesis system. 4. The scheduling algorithm The basic algorithm is a list scheduling algorithm. An outline is given below: PRC CASCH(V) V: erations in the data flow grah BEGIN act_cycle := 1 WHILE V Ø D V r := oerations which can be started in the actual clock cycle (ready oerations) generate_and_evaluate_all_assignments(v r ) V d := the assignment with the best rating Schedule[act_cycle] := V d V := V \ V d act_cycle := act_cycle + 1 ENDWHILE END The roblem of the basic list scheduling algorithm is that not all ready oerations V r can be executed in arallel due to limited resources. In this case a subset V d of V r has to be selected. Also a comonent tye has to be assigned to every selected oeration. The following recursive algorithm generates all subsets and all ossible assignments to comonent tyes. PRC generate_and_evaluate_all_assignments(b) B: ready oerations in the actual clock cycle BEGIN WHILE B Ø D b := elem (B) B := B \ {b} K := set of all comonent tyes where 1. the tye can execute oeration b and. one comonent of the tye is free FR ALL k K D reserve one comonent of tye k lan oeration b into actual clock cycle on tye k call ratingfunction for the actual assignment generate_and_evaluate_all_assignments(b) take oeration b from actual clock cycle release one comonent of tye k ENDFR ENDWHILE END

3 The otimal scheduling roblem can be reduced to the roblem of the otimal selection of one generated subset and assignment. This selection is controlled by the here called ratingfunction. Since the rating function determines the result of the scheduling the rest of this aer concentrates on it. The scheduling algorithm is also able to deal with loos and ielining including latency otimization. These additional features are described in more detail in [Gutb89]. 5. Rating function 5.1. verview The rating function determines during the scheduling how the total delay will "robably" be influenced by a secific assignment. This forecast includes otential latency in case of ieline rocessing which is not exlained here. To determine these delays exactly would of course allow otimal scheduling. But since the roblem of otimal scheduling under given comonent constraints is NPcomlete [GaJo79] no efficient rating algorithm roviding exact results (yet) exists. In the following an efficient and accurate heuristic rating function for estimating the total delay is resented. The estimation is done for the oerations, which are not yet scheduled. The result of the rating function is the minimal delay of the otimal schedule without resource constraints lus the delay caused by resource constraints. Resource constraints are not only a limited number of comonents but also a limited number of internal and external connections. To clarify how this estimation function works, in the following the dataflow grah from figure is treated as an examle for estimating the total delay. To make the examle simle the only resource constraint is a comonent limitation. nly one adder and one ALU are allocated, where each comonent requires one clock cycle. Additions can be erformed by the adder or the ALU. The subtractions can only be erformed by using the ALU. 5.. Distribution of oerations to clock cycles In a first ste an "as soon as ossible (ASAP)" and an "as late as ossible (ALAP)" schedule without resource constraints are calculated. As a result for each oeration the earliest as well as the latest execution time is obtained. Figure shows the time frames for the oerations based on the ASAP and the ALAP schedules. That means, that in the following we are only dealing with robabilities of assigning an oeration to a secific clock cycle. Table 1 contains for each oeration, each clock cycle and each branch label the robability for the oerations assuming an equirobable distribution of the oerations over their time frames. This table is the basis for the delay estimation due to limited resources. T Figure Time frames of the oerations Table 1 Evaluation table T In the examle we use the oeration tyes addition and subtraction. Within this abstraction level we consider the oerations as units cometing for comonents. ne oeration can therefore be characterized by the comonent tyes able to execute this oeration. That means that the oeration tyes therefore define a subset of all comonent tyes in our examle. This results in (1). = K 1 = ALU { } { } (1) + =K = Add,ALU 5.. Distribution of oerations to comonent tyes In the next ste all the resource limitations are introduced. Starting from an already statistical oeration distribution to clock cycles we will calculate a statistical distribution of oerations to comonents. This distribution is exressed by the matrix multilication given in (). Based on these conditions the distribution factors have to be determined next. The determination of this distribution works as follows. Limited comonent tyes should only be used for such oerations where no other tyes exist. For oerations with a large number of comonent tyes tyes with a small load have to be selected. A criteria to get a good distribution is to equalize the load of all comonent tyes as much as ossible. The load is given by ().

4 b k1 v 11 v 1 L v 1 o K1 b k v = 1 v L v o K b km v m1 v m L v m o K v ij [ 0,1] v ij = 0, if k i K j m v ij = 1 i=1 K j o Kj m k i b ki v ij number of oeration tyes oeration tyes tableentryfor oeration tye K j number of comonent tyes comonent tyes necessarynumber of comonentsof tye k i distribution factor for K j on k i () a ki = b k i r ki () a ki b ki r ki load of comonent tye k i necessarynumber of comonentsof tye k i existing number of comonentsof tye k i An otimal assignment of oerations to comonent tyes requires a distribution with a global view, i.e. assignment of an oeration to a comonent tye influences the assignment of other oerations. To eliminate these mutual deendencies an additional heuristic is used. The oeration tyes are sorted in increasing order with resect to the number of different comonent tyes able to execute this oeration. The oerations are now within this order assigned to comonent tyes, i.e. it is assumed that condition (4) holds: "mistakes". In our examle this means that in the first ste the subtractions are distributed (no mistakes ossible) and in the next ste the additions are distributed. The second ste is done by equalizing the load of the ALU and the adder as much as ossible utual exclusive oerations By using the branch labels it is ossible for the scheduling algorithm to assign several oerations within the same clock cycle to the same comonent. For oerations which are mutual exclusive the maximum of the required comonents within each branch is sufficient for all branches. This is taken into account by the following algorithm. The algorithm starts with the evaluation table given in table 1. Beginning with the main branch, all oerations with this label are added to the oerations in all direct sub branches. With nested sub branches this is done recursively until the innermost sub branch is reached. Table shows the result roduced by this algorithm for our examle. ( is the main branch, and are mutual exclusive.) For each branch and each clock cycle now the oerations are distributed by an heuristic algorithm which equally minimizes the load of all comonent tyes. As a result we obtain table. In the next ste we calculate the maximum for the mutual exclusive branches and this results in table 4. The now calculated number of comonents is the estimate for the total number of comonents of each tye, i.e. the necessary comonents required for each ossible branch. From table 4 now the delay due to resource constraints can be estimated as a comonent load larger than one (5). The result is an estimated delay of 0. clock cycles. v k,t = max(a k,t 1,0) a k,t v k,t load of tye k in clock cycle t delayof tye k in clock cycle t (5) K 1 K L K (4) The distribution factors are now columnwise determined from left to right. The heuristic means that at the beginning only few ossibilities exist and therefore only small "mistakes" are ossible. In a later stage the revious decisions can be taken into account in order to correct these Table Sum in branches,, T Table Comonent distribution,, T Add ALU Add ALU Examles and results The filter examle [DeDN85] is a benchmark for the highlevel synthesis worksho series. It contains 6 additions and 8 multilications. The control flow consists of one single loo without mutual exclusive oerations. Table 4 aximum between branches,, T Add ALU Table 5 shows some results which have been calculated by the here resented algorithm. The results are based on different resource allocations using the comonent tyes given in table 6. The uer art of the table is obtained

5 without using the integrated comonent tye assignment. Similar results have already been obtained by other already resented scheduling algorithms [PaPa86], [PaKn87] and [PaKn89]. The lower art of the table shows the imrovements which are ossible by using different ALU tyes. The comonent tye selection integrated in the scheduling algorithm allows a much better design sace exloration and rovides these very encouraging results. Comarable results from other systems are not known to the authors u to now. The CPU time column is given with resect to a HP/Aollo DN 4500 (7IPS) workstation. Table 5 Results for filter examle Resources Results Add Add* ul ulp ALU ALUP CPU(s) Cycles Add Add* ul Table 6 Comonent tyes Adder, delay 1 clock cycle Adder, delay 0.5 clock cycles ultilier, delay clock cycles ulp ul with internal ieline, latency 1 clock cycle ALU ALU (add, mul), delay for add 1 clock cycle, delay for mul clock cycles ALUP ALU with internal ieline, latency 1 clock cycle 7. Summary A new scheduling algorithm has been resented. An essential feature of this new algorithm is the integrated comonent tye assignment within this scheduling algorithm. By using this algorithm it is ossible to otimize the timing behaviour of a circuit by taking advantage as much as ossible of limited available or esecially owerful comonents. This contribution concentrates on the detailed descrition and exlanation of the rating function. The encouraging results esecially the low CPU times of the rating function allow the use of the rating function indeendent from the scheduling algorithm. ne ossible alication of the rating function could be the automation of an otimal resource allocation. 8. References [CaKR84] R. Camosano, A. Kunzmann, W. Rosenstiel, "Automatic Data Path Synthesis from DSL Secifications", International Conference on Comuter Design, ICCD 1984 [CaRo89] R. Camosano, W. Rosenstiel, "Synthesizing Circuits from Behavioral Descritions", IEEE Transactions on CAD, Vol. 8, 1989 [DeDN85] P. Dewilde, E. Derettere, R. Nouta, "Parallel and Pielined VLSI Imlementations of Signal Processing Algorithms" in S. Y. Kung, H. J. Whitehouse, T. Kailath, "VLSI and odern Signal Processing", Prentice Hall, 1985 [DKNP89] P. Duzy, H. Krämer,. Neher,. Pilsl, W. Rosenstiel, T. Wecker, "CALLAS Conversion of Algorithms to Library Adatable Structures", VLSI 89 [GaJo79]. R. Garey, D. S. Johnson, "Comuters and Intractability", Bell Labaratories, urray Hill, New Jersey, 1979 [Gutb89] P. Gutberlet, "Design of a Scheduling Algorithm for the CADDY Synthesis System", (in german) Diloma Thesis, University of Karlsruhe, 1989 [KNRW88] H. Krämer,. Neher, G. Rietsche, W. Rosenstiel, "Data Path and Control Synthesis in the CADDY System", International Worksho on Logic and Architecture Synthesis for Silicon Comilers, 1988 [KoGD90]. Koster,. Geiger, P. Duzy, "ASIC Design Using the HighLevel Synthesis System CALLAS: A Case Study", ICCD 90 [KrRo90] H. Krämer, W. Rosenstiel, "System Synthesis using Behavioural Descritions", Proceedings at 1 st EDAC, 1990 [PaKn87] P. G. Paulin, J. P. Knight, "ForceDirected Scheduling in Automatic Data Path Synthesis", Proceedings of the 4th Design Automation Conference, 1987 [PaKn89] P. G. Paulin, J. P. Knight, "Scheduling and Binding Algorithms for HighLevel Synthesis", Proceedings of the 6th Design Automation Conference, (Extended Version), 1989 [PaPa86] N. Park, A. C. Parker, "SEHWA: A Program for Synthesis of Pielines", Proceedings of the rd Design Automation Conference, 1986 [RoCa85] W. Rosenstiel, R. Camosano, "Synthesizing Circuits from Behavioral Level Secifications", 7th International Symosium on Comuter Hardware Descrition Languages and their Alications, CHDL 85, Tokio, 1985