D.A.S.T. Defragmentation And Scheduling of Tasks University of Twente Computer Science

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1 D.A.S.T. Defragmentation And Scheduling of Tasks University of Twente Computer Science Frank Vlaardingerbroek Joost van der Linden Stefan ten Heggeler Ruud Groen 14th November 2003 Abstract When mapping tasks on a Heterogeneous Tile Processor (HTP) situations arise that communicating tasks will be mapped on a processor surface in an inefficient way. Inefficiency may be caused when a process cannot be mapped on the tile that would give optimal performance. Moreover, the distance between two communicating processes might become too large when mapping processes on the tile of choice. Choices for less-than ideal situations might be forced when the processor surface has a high degree of occupation. Ways to prevent or reduce this inefficiency can be found on beforehand while scheduling tasks or mapping the processes of the task onto the processor. The best way of inefficiency reduction will be an optimal combination of these three factors. An intelligent scheduler, cooperating with the mapper to determine which process will be running when and where. At the same time defragmenter will keep a close watch, working to local optima when possible, and only interrupting the system and executing a major defragmentation when the gain will be high enough to compensate for the large extra cost and time. It is expected, however, that this will rarely be the case. 1 Introduction The abilities for mobile devices will become more demanding in the near future. Ideas to combine the cell-phone, PDA, photo and film camera and maybe even the wallet into one handheld device, might seem attractive and technologically possible. However, because the evolution of battery technology is not keeping up to solve these demands with traditional techniques like the inefficient General Purpose Processors (GPP), other solutions are sought. Investigations in Application Specific Integrated Circuits (ASIC) technology might yield a good performance in both speed and energy efficiency, but because of the high development time and costs, it might not be a good solution in this area of rapid changing technology. In the recent years, reconfigurable hardware, like the Field Programmable Gate Array (FPGA), proved a promising field of research. The 1

2 FPGA is more flexible than the ASIC, and has better performance than the GPP. But because the FPGA requires bit-level reconfiguration, the overhead for using this technology increases dramatically. The solution addressed in this article, is one using different kinds of processors in parallel. The Heterogeneous Tile Processor (HTP) is a chip containing a matrix of tiles, each being potentially a different kind of processor. When mapping a set of communicating tasks on such a structure, it might be possible that a single process can be mapped on different tiles. The choice of tile might than depend on how efficient the mapping on such a kind of tile is, but the distance to other tiles might be of importance when a process has to communicate with the processes on those tiles. Finding the optimal solution in this mapping problem, is an NP-hard problem. This paper introduces the problem as a graph theory problem. A solution to this problem is formally given in [1], and will be described here shortly. Next to intelligent mapping, intelligent scheduling might be of importance as well. There might be a choice between mapping a high priority task quite inefficient now, and mapping a task with some lower priority more efficient on the same processor space. Ways of scheduling that may improve efficiency in relation to a FIFO queue will be described with some advantages and disadvantages. Despite these preventive methods, the situation will probable arise that the degree of fragmentation of communicating processes will rise above acceptable values. In that case, defragmentation might be necessary. In this paper several approaches to defragmentation are discussed. This will include a view on the approach when the defragmentation is distributed between the three named stages. 2 Process Mapping on HTP The mapping of applications on a HTP might seem quite simple at first, but this proves not to be the case. An application is usually described by a task-graph, which shows the relation between the different processes of the application, with their communication. In the most simplistic point of view, each process might be mapped onto exactly one tile of a HTP. The problem that arises is that for the optimal mapping, the tile chosen for each process is not just one of the kind that might have the best speed and power consumption properties, but the chosen processors also have to be at close distance to minimize the communication cost. For a single task graph with only few processes, and only few choices for the processor tiles, the total amount of possibilities might already be quite large. For example, a linear task graph of three processes, with each three different choices for tiles, already has 3 3 = 27 possibilities, and task graphs are potentially larger and more complex. Modeling of this problem can be done using graph-theory. The construction of the problem graph is done in three steps: The first step is to inflate the base graph. For each vertex in the base graph representing a process, a collection of vertices is made, where each new vertex represents a specific tile where the process might be mapped onto. Step two consists of making the edges into the base graph. Where an edge 2

3 Figure 1: Base graph existed between two vertices of the base graph, the collections of vertices in the new graph are connected complete bipartite. In step three, each vertex and edge is weighted. The weight of vertices is constructed according to energy efficiency and speed of the mapping on that tile, the weight of the edges represents the energy cost of the transportation of the data. The problem can now be described as Finding a new graph by taking exactly one vertex from each collection, so that the total weight of vertices and edges together is as small as possible. This problem proves to be NP-hard[1]. However, when the base graph is not too complex, the problem can be solved by using graph reduction according to some simple paradigms[1]: Vertices in the base graph with degree 1 (end points), can be removed. The costs of the cheapest vertex - connecting edge combination can be added to the vertex where it was connected to. This vertex now represents 2 vertices and 1 edge. Vertices in the base graph with degree 2, can be removed as well. By using an algorithm like Dijkstra s [2], the shortest path in the problem graph can be found between each vertex in the collection before, to each vertex in the collection after the vertex with the original degree of 2. The weight of the vertex in the collection before the removed vertex, has to be increased with the weight of the removed vertex. The weight of the connection has to be increased with the weight of the connections of the shortest path. It is expected that task-graphs only contain few vertices with a degree of 3, and that higher degrees will seldom appear. In that case, the graph reduction Figure 2: Inflated graph, after step one 3

4 Figure 3: Connected graph, after step two as described above, will solve the problem in most cases. 3 Scheduling Scheduling is the process of allocating the CPU to a given task. In our research with a heterogeneous reconfigurable tile processor we will be scheduling one or more tasks on the chip (CPU). There are mainly two ways to schedule tasks on a processor: preemptive and non-preemptive. The disadvantage with preemptive scheduling on a reconfigurable tile-processor is that the overhead generated by the reconfiguration of the processor increases. Also the there is a possibility that the fragmentation of the processor increases, several tasks will be preempted and replaced by less fitting tasks. Those problems are of less importance when nonpreemptive scheduling is used. Disadvantage of non-preemptive scheduling is that the average waiting time of the tasks increases during time [3] [4]. Algorithms using deadlines are ignored because the future model doesn t generate tasks with deadlines. Because of the difficulties with preemption we have decided to choose for non-preemptive scheduling. Only for the defragmentation of the chip it is needed that the running tasks or processes can be preempted. Only for the use of defragmentation the tasks can be preempted. For non-preemptive scheduling there are several different algorithms: 3.1 First-Come First-Served This is by far the simplest CPU-scheduling algorithm. With this scheme the task that requests the CPU first is allocated the CPU first. The implementation of the FCFS policy is easily managed with a FIFO queue. When a task enters the ready queue it is linked onto the tail of the queue. When the CPU becomes free it is allocated to the task at the head of the queue. The problem with this algorithm is that the average waiting time can be quit long because new tasks have to wait for the preceding tasks to complete [4]. 3.2 SJF Shortest Job First This algorithm associates with each task the execution time of the task. when the CPU is available it is assigned to the task that has the smallest execution [4]. If two tasks have the same length (execution time), FCFS is used to break the tie. The advantage of this algorithm is the short waiting time for short tasks. 4

5 3.3 SGF Smallest Graph First A variation on shortest job first only adapted for the HTP. A small graph is given priority above a larger, which has the advantage that a short graph is easier to map and keep probably the fragmentation of the graph smaller. The difference between the previous algorithm and this one is that the shortest job not always has the smallest graph. Another advantage is the fixed priority of the different tasks. Without knowing the layout of the HTP it is possible to reduce the possible fragmentation by sending easy to map tasks. 3.4 On-line scheduling The last option is online scheduling [5] [6]. This is a dynamic way of scheduling, the layout of the processor at a certain moment decides the order of the tasks. This allows the next pending task to be processed sooner. This could prevent further fragmentation of the chip by using the mapping and defragmentation algorithms proposed in the paper. The given task will fit better on the chip. Disadvantage of the use of dynamic scheduling is the increase of the complexity of the algorithm. Another disadvantage of this way of dynamic scheduling is that the more complex tasks can end up waiting, despite there be sufficient resources to serve them, so without a good defragmentation algorithm the utilization of the chip is less. On-line scheduling increases the problem of fragmentation, but by using the right mapping and defragmentation algorithms this problem can be solved [6]. The waiting time of the tasks can be reduced, and when defragmented the utilization can also be improved. The delay time of the task is reduced. 4 Fragmentation problem Fragmentation is the process, or result, of dividing a contiguous area into smaller non-contiguous parts through allocating parts of the area, and leaving the rest to be allocated. Apart from Tile Processor allocation, this is also a known problem in certain memory allocation schemes, and file systems. Fragmentation is expected to cause efficiency problems in the long run. After allocating and deallocating many processes to/from tiles of the Tile Processor, idle (unallocated) tiles will be scattered. In this situation newly allocated processes that are mapped to these tiles suffer from poor efficiency (concerning speed as well as power consumption) as the distance between tiles is much larger than necessary. We believe that efficiency gain by defragmentation will be worth the effort compared waiting for contiguous allocation space, when a process finishes its task. 4.1 Defragmentation The main difficulty of HTP defragmentation is that it deals with a heterogeneous structure of many different tiles. Existing fragmentation problems are found with mappings on homogeneous structures. This means that defragmentation methods used in these areas can not be applied simply. Points that need to be considered: 5

6 Complete or partial defragmentation. It cannot be stated that one is better than the other, as both have their advantages and disadvantages. Complete defragmentation may result in a better overall efficiency compared to partial defragmentation, because the allocation improvements are near a global optimum, however the costs of time and energy will increase severely. Complete defragmentation consists of making a plan of what tasks are to run on what tiles, and carrying out this plan. The use of this defragmentation will be lost, when some tasks are finished, and others are ready to be scheduled. Partial defragmentation has the benefit that it is less of a burden to the currently mapped tasks, but may also have less spectacular results. Any may be more appropriate in one situation or the other. A method for determining the amount of defragmentation is required. This amount is closely related to the distance of an ideal mapping and the distance between tiles of the current mapping. Existing mathematical theories may be used for this purpose. Performing a large defragmentation may be more cost-effective, when doing this with a few processes at a time, while the other processes continue running. The consideration is that we wish to make as few processes idle as possible, but it may be inefficient to place a process on the right spot in many steps. Strategies for defragmentation is a subject for discussion. Performing defragmentation in constant intervals has the advantage that scheduling of the process is kept simpler, and the situation of a completely fragmented mapping is avoided. The disadvantage is that scheduling a defragmentation when it is not necessary will impose an inefficiency, and there may be a situation possible that a mapping is fragmented and a defragmentation is not scheduled before a long while. The alternative is scheduling defragmentation based on properties of the current mapping. Monitoring of the mapping efficiency will give a ground to decide when to schedule a defragmentation. The former strategy will schedule a defragmentation when the mapping is less fragmented, what makes it faster to achieve, while the latter schedules a defragmentation when it is strictly necessary, what makes it worth the effort of the interruption of tasks, and the energy consumption of reconfiguration. 4.2 Proposed solution Currently, simulation results are not available to justify our decision on what method and strategy to employ. At the moment, the following process can be proposed as a part of the solution. Identify a process that suffers from poor efficiency due to large distances between tiles or less suitable tiles for specific tasks. Calculate layout improvements for any possible replacement tile, and select the replacement tile that will result in the highest increase in performance. Configure the selected replacement tile for its task. 6

7 Interrupt the task, transfer the state information to the replacement tile, and reconfigure the routing of the other tiles. Although performance characteristics are not available it can be estimated that this method will prove efficient. The following reasoning preceded this conclusion: The time that a process is interrupted is kept at a minimum. In order to meet a certain ratio of efficiency gain versus time and energy cost, a minimum efficiency gain can be set as a requirement. Modeling and simulation of mapping, scheduling and defragmentation methods is required to compare efficiency costs and benefits of this method of defragmentation and others. 5 Discussion Our research has indicated that the most frequently used method for mapping processes on a processor surface is online scheduling with a FIFO queue. Though this method might normally increase fragmentation, when used in close collaboration with an intelligent mapping algorithm we expect a resulting method that is both fast and efficient. The proposed solution of slack tile defragmentation is merely a partial solution that is expected to be most efficient. Conclusions about the use of complete defragmentation can not be made, as performance improvements cannot be estimated without simulation. Simulation of the different possibilities will be necessary to verify the efficiency of the separate parts, and the most efficient combination. References [1] Broersma H., Paulusma D., Smit G.J.M., Vlaardingerbroek F., Woeginger G.J. The computational complexity of the minimum weight processor assignment problem.working Article University of Twente, Enschede, The Netherlands, 2004 [2] Dijkstra E.W. A note on two problems in connexion with graphs Numerische Mathematik, 1: , 1959 [3] Butazzo G.C. Hard real-time computing systems Kluwer Acadamic Publisher Group, Dordrecht, 2002 [4] Silberschatz, Galvin, Gugne Operating system concepts sixth edition John Wiley & sons, inc., New York, 2003 [5] Walder H., Platzner M. Online scheduling for block-partitioned reconfigurable devices Computer engineering and networks lab Swiss federal institute of technology Zurich, Switzerland 7

8 [6] Diessel O.F., Math B., Hons B.E. On scheduling dynamic FPGA reconfigurations The department of computer science and software engineering, The university of Newcastle, Newcastle, Austalia,