Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs

Transcription

1 Talor Epansion Diagrams: anonical Representation for Verification of Data Flow Designs Maciej iesielski, Priank Kalla, Serkan skar Department of Electrical and omputer Engineering Universit of Massachusetts, mherst, M- Department of Electrical and omputer Engineering Universit of Utah, Salt Lake it, UT 8 ccepted for publication in IEEE Transactions on omputers T-8- pril 8, This work has been supported b a grant from the National Science Foundation, R-, and in part b the international NSF/NRS/DD supplement grant, INT-. bstract Talor Epansion Diagram (TED) is a compact, wordlevel, canonical representation for data flow computations that can be epressed as multi-variate polnomials. TEDs are based on a decomposition scheme using Talor series epansion that allows to model word-level signals as algebraic smbols. This power of abstraction, combined with canonicit and compactness of TED, makes it applicable to equivalence verification of dataflow designs. The paper describes the theor of TEDs and proves their canonicit. It shows how to construct a TED from a HDL design specification and discusses application of TEDs in proving equivalence of such designs. Eperiments were performed with a variet of designs to observe the potential and limitations of TEDs for dataflow design verification. pplication of TEDs to algorithmic and behavioral verification is demonstrated. I. Introduction Design verification is the process of ensuring the correctness of designs described at different levels of abstraction during various stages of the design process. ontinuous increase in the size and compleit of digital sstems has made it essential to address verification issues at earl stages of the design ccle. Identification of errors earl in the design process can significantl epedite time-to-market and make the design and verification process more efficient. To address this problem, robust, automated verification tools that can handle designs at higher levels of abstraction, such as at behavioral and algorithmic levels, need to be developed. Having matured over the ears, formal design verification methods, such as theorem proving, propert and model checking, equivalence checking, etc., have found increasing application in industr. anonic graph-based representations, such as inar Decision Diagrams (DDs) [], inar Moment Diagrams (MDs) [] and their variants (PHDDs [], K*MDs [], etc.) pla an important role in the development of computer-aided verification tools. In particular, these representations have been be used to model RTL designs and prove their equivalence at the bit level. However, these representations are limited in their abilit to represent algebraic computations in abstract, higher-level, smbolic forms. This motivated us to derive a new representation for high-level design descriptions, termed Talor Epansion Diagrams (TEDs). This representation is particularl suited for modeling and supporting equivalence verification of designs specified at the behavioral level [5] []. Similar to DDs and MDs, TED is a canonical, graph-based representation. In contrast to DDs and MDs, TED is based on a non-binar decomposition principle, modeled along the Talor s series epansion [7], [8]. With this new data structure, word-level signals are represented as algebraic smbols, raising the level of abstraction of the design to higher levels. The power of abstraction of TEDs allows one to represent behavioral dataflow designs efficientl, with memor requirements several orders of magnitude smaller than those of other known representations. TEDs are applicable to modeling, smbolic simulation and equivalence verification of dataflow and algorithm-dominant designs, such as digital signal processing for audio, video and multimedia applications and embedded sstems. omputations performed b those designs can often be modeled as polnomials and readil be represented with TEDs. The test for functional equivalence is then performed b checking isomorphism of the resulting graphs. While application of TEDs is limited to those designs whose computations can be epressed as multi-variate polnomials, their use for algorithmic verification is particularl appealing. Eperimental results confirm the potential of TEDs for equivalence verification of dataflow oriented designs at behavioral and algorithmic levels. The paper is organized as follows. Section II reviews contemporar canonic representations and discusses their limitations. complete theor of TED is described in Section III. The composition operations and analsis of their compleit are presented in Section IV, while Section V describes the construction of TEDs for RTL designs and discusses their limitations. Section VI describes the implementation of the TED package along with some eperimental results. Finall, Section VII concludes the paper with comments and directions for future work. II. Review of Previous Work In the realm of high-level design verification, the issue of abstraction of smbolic, word-level computations have received a lot of attention. This is visible in theorem-proving techniques, automated decision procedures for Presburger arithmetic [9] [], techniques using algebraic manipulation [], smbolic simulation [], or in the decision procedures that use a combination of theories [] [], etc. Term re-writing sstems, particularl those used for hardware verification [5] [] [7], etc., also represent computations in high-level smbolic forms. The above representations and verification techniques, however, do not rel on canonical forms. For eample, verification techniques using term rewriting are based on rewrite rules that lead to normal forms. Such forms ma produce false negatives, which ma be difficult to analze and resolve. In contrast, the TED representation proposed in this paper not onl abstracts bit-vector arithmetic computations as polnomials, but also represents them canonicall. Various forms of high-level logics have been used to represent and verif high-level design specifications. Such representations are mostl based on quantifier free fragments of first order logic. The works that deserve particular mention include: the logic of equalit with uninterpreted functions (EUF) [8] and with memories (PEUFM) [9] [], and the logic of counter arithmetic with lambda epressions and uninterpreted functions (LU) []. To avoid eponential eplosion of DDs, equivalence verification is generall performed b transforming high-level logic description of the design into propositional logic formulas [] [] [9] and emploing satisfiabil-

2 it tools [] [] for testing the validit of the formulas. While these techniques have been successful in the verification of control logic and pipelined microprocessors, the have found limited application in the verification of large data-path designs. Word-Level TPG techniques [] [5] [] [7] [8] have also been used for RTL and behavioral verification. However, their applications are generall geared toward simulation, functional vector generation or assertion propert checking, but not so much toward high-level equivalence verification of arithmetic datapaths.. Decision Diagram ased Representations Reduced Ordered inar Decision Diagrams (RODDs, or DDs for short) [], along with their efficient implementation as software packages [9], are credited with significantl increasing the efficienc of equivalence checking for logic designs. DD represents a set of binar valued decisions in a rooted directed acclic graph (DG), based on a recursive Shannon decomposition. This decomposition, combined with a set of reduction rules, makes the resulting diagram minimal and canonical for a given ordering of variables []. DDs have found wide application in a number of verification problems, including combinational equivalence checking [], implicit state enumeration [], smbolic model checking [] [], etc. However, as the designs have grown in size and compleit, the size-eplosion problems of DDs have limited their scope. Most DD-based verification sstems, such as SMV [] and VIS [], have been successful in verifing control-dominated applications. However, for designs containing large arithmetic data-path units, DDs have not been ver successful due to prohibitive memor requirements, especiall for large multipliers. Numerous attempts have been made to etend the capabilities of verification engines to target arithmetic units. Majorit of these methods are based on generic Word Level Decision Diagrams (WLDDs), graph-based representations for functions with a oolean domain and an integer range. Most of the WLDD representations are based on a point-wise, or binar decomposition principle. Different flavors of oolean decomposition (Shannon, Davio, Reed-Muller, etc.) are used to decompose functions w.r.t. their bit-level variables, leading to different Decision Diagrams. In addition to DDs [] and Partitioned DDs [5], the include edge-valued DDs (EVDDs) [], and functional decision diagrams (FDDs, KFDDs) [7] [8]. etending DDs to allow numeric leaf values point-wise decomposition leads to different Multi-terminal DDs, or MTDDs [9], and lgebraic Decision Diagrams (DDs) []. However, the decomposition at each variable is still binar. s a result, a linear increase in the size of input variables results, in the worst case, in an eponential increase in the size of decision diagrams. thorough review of WLDDs can be found in [].. Moment Diagram ased Representations inar Moment Diagrams, MDs, *MDs [], and their derivatives (PHDDs [], K*MD [], etc.), depart from a point-wise decomposition and perform a decomposition of a linear function based on its first two moments. MD uses a modified Shannon s epansion, in which a binar variable is treated as a (,) integer: f() = f + f = f + ( ) f = f + (f f ) where, + and - denote algebraic multiplication, addition and subtraction, respectivel. The above decomposition is termed as moment decomposition, where (f f ) is the linear moment and f the constant moment. In this form, f can be viewed as a linear function in its variables, and (f f ) as the partial derivative of f with respect to. inar moment diagrams provide a concise representation of integer-valued functions defined over bit vectors (words), X = i i i, where each i is a binar variable. The binar moment decomposition is recursivel applied to each variable i. In such defined MD, multiplicative constants reside in the terminal nodes. The constants can also be represented as multiplicative terms and assigned to the edges of the graph, giving a rise to Multiplicative inar Moment Diagram, or *MD []. n eample of such a diagram is depicted in the left part of Fig.. Several rules for manipulating edge weights are imposed on the graph to allow the graph to be canonical. For linear and multi-linear epressions *MD representation is linear in the number of variables. However, the size of *MD for X k, where X is an n-bit vector, is O(n k ). Thus, for high-degree polnomials defined over words with large bit-width, as commonl encountered in man DSP applications, *MD remains an epensive representation. K*MD [] attempts to make the MD decomposition more efficient in terms of the graph size. This is done b admitting multiple decomposition tpes, such as Davio, Shannon, etc., to be used in a single graph, and allowing both the multiplicative and additive weights assigned to the graph edges. However, a set of restrictions imposed on the edge weights to make it canonical makes such a graph difficult to construct.. Smbolic lgebra Methods Man computations encountered in behavioral design specifications, can be represented in terms of polnomials. This includes digital signal and image processing designs, digital filter designs, and man designs that emplo comple transformations, such as DT, DFT, FFT, etc. Polnomial representations of discrete functions have been eplored in literature long before the advent of contemporar canonical graph-based representations. Particularl, Talor s epansion of oolean functions has been studied in [] []. However, these works mostl targeted classical switching theor problems: logic minimization, functional decomposition, fault detection, etc. The issue of abstraction of bit-vectors and smbolic representation of computations for high-level snthesis and formal verification was not their focus. Polnomial models of high-level design specifications have been used recentl in the contet of behavioral snthesis for the purpose of component mapping [5], [], [7]. polnomial representation is created for each component (operator) from the librar and the polnomials are matched b comparing their coefficients. However, storing and comparing large matrices of such coefficients is inefficient for large multi-variate polnomials. The TED representation described in this paper can provide a more robust data structure for performing these tasks efficientl, due to its compact and canonical structure. Several commercial smbolic algebra tools, such as Maple [8], Mathematica [9], and MatLab [5], use advanced smbolic algebra methods to perform efficient manipulation of mathematical epressions. These tools have also been used for the purpose of polnomial mapping, namel to perform simplification modulo polnomial [7]. However, despite the unquestionable effectiveness and robustness of these methods for classical mathematical applications, the are less effective in modeling of large scale digital circuits and sstems. We believe that these methods can benefit from canonical representations such as TED, in particular for component matching and equivalence checking. It is interesting to note that smbolic algebra tools offered b Mathematica and alike cannot unequivocall determine the equivalence of two polnomials. The equivalence is checked b subjecting each polnomial to a series of epand operations and comparing the coefficients of the two polnomials ordered leicographicall. s stated in the manual of Mathematica 5, Section.., there is no general wa to find out whether an arbitrar pair of mathematical epressions are equal [9]. Furthermore, Mathematica cannot guarantee that an finite sequence of transformations will take an two arbitraril chosen epressions to a standard form. (Mathematica 5, Section.). In contrast, the TED data structure described in the sequel provides an important support for equivalence verification b offering a canonical representation for multi-variate polnomials. III. Talor Epansion Diagrams known limitation of all decision and moment diagram representations is that word-level computations, such as +, require the decomposition of the function with respect to bit-level variables [k], [k]. Such an epansion creates a large number of variables in the respective diagram framework and requires ecessive memor and time to operate upon them. In order to efficientl represent and process the HDL description of a large design, it is desirable to treat the word-level variables as algebraic smbols, epanding them into their bit-level components onl when necessar. onsider the *MD for, shown in Fig. (a), which depicts the decomposition with respect to the bits of and. It would be desirable to group the nodes corresponding to the individual bits of these variables to abstract the integer variables the represent, and use the abstracted variables directl in the design. Fig. depicts the

3 b a b b + b + b => [:] b a a + a + a => [:] a *MD: * [:] TED: * [:] f v... f "()/! f() f () f"()/ Fig.. decomposition node in a TED. Fig.. bstraction of bit-level variables into algebraic smbols for F =. idea of such a smbolic abstraction of variables from their bit-level components. In order to achieve the tpe of abstracted representation depicted above, one can rewrite the moment decomposition f = f + (f f ) as f = f( = ) + (f). This equation resembles a truncated Talor series epansion of the linear function f with respect to. allowing to take integer values, the binar moment decomposition can be generalized to a Talor s series epansion. This wa one can represent integer variables without epanding them into bits.. The Talor Series Epansion Let f() be a continuous, differentiable function defined over the domain R of real variables. The Talor series epansion of f w.r.t. variable at an initial point, =, is represented as follows [8]: f() = k= k! ( ) k f k ( ) = f()+f ()+ f ()+... () where f ( ), f ( ), etc., are first, second, and higher order derivatives of f with respect to, evaluated at =. The Talor series epansion can be suitabl adapted to represent computations over integer and oolean variables, as commonl encountered in HDL descriptions. rithmetic functions and dataflow portions of those designs, can be epressed as multi-variate polnomials of finite degree for which Talor series is finite. Let f(,,...) be a real differentiable function in variables {,,...}. ssume an algebra (R,, +) over real numbers R. Using the Talor series epansion with respect to a variable, function f can be represented as: f(,,...) = f( =,, ) + f ( =,, ) + f ( =,, ) +... The derivatives of f evaluated at = are independent of variable, and can be further decomposed w.r.t. the remaining variables, one variable at a time. The resulting recursive decomposition can be represented b a decomposition diagram, called the Talor Epansion Diagram, or TED. Definition III.: The Talor Epansion Diagram, or TED, is a directed acclic graph (Φ, V, E, T ), representing a multi-variate polnomial epression Φ. V is the set of nodes, E is the set of directed edges, and T is the set of terminal nodes in the graph. Ever node v V has an inde var(v) which identifies the decomposing variable. The function at node v is determined b the Talor series epansion at = var(v) =, according to equation. The number of edges emanating from node v is equal to the number of nonempt derivatives of f (including f()) w.r.t. variable var(v). Each edge points to a subgraph whose function evaluates to the respective derivative of the function with respect to var(v). Each subgraph is recursivel defined as TED w.r.t. the remaining variables. Terminal nodes evaluate to constants. Starting from the root, the decomposition is applied recursivel to the subsequent children nodes. The internal nodes are in oneto-one correspondence with the successive derivatives of function f w.r.t. variable evaluated at =. Figure depicts one-level decomposition of function f at variable. The k-th derivative of a function rooted at node v with var(v) = is referred to as a k-child of v; f(=) is a -child, f (=) is a -child,! f (=) is a -child, etc. We shall also refer to the corresponding arcs as -edge (dotted), -edge (solid), -edge (double), etc. Eample: Figure shows the construction of a TED for the algebraic epression F = (+)(+) = + (+ + ). Let the ordering of variables be,,. The decomposition is performed first with respect to variable. The constant term of the Talor epansion F ( = ) =. The linear term of the epansion gives F ( = ) = + ; the quadratic term is F ( = ) = =. This decomposition is depicted in Fig. (a). Now the Talor series epansion is applied recursivel to the resulting terms with respect to variable, as shown in Fig. (b), and subsequentl with respect to variable. The resulting diagram is depicted in Fig. (c), and its final reduced and normalized version (to be eplained in Section III-) is shown in Fig. (d). The function encoded b the TED can be evaluated b adding all the paths from non-zero terminal nodes to the root, each path being a product of the variables in their respective powers and the edge weights, resulting in F = Using the terminolog of computer algebra [5], TED emplos a sparse recursive representation, where a multivariate polnomial p(,, n) is represented as: p(,, n) = m p i (,, n ) i n () i= The individual polnomials p i (,, n ) can be viewed as coefficients of the leading variable n at the decomposition level corresponding to n. construction, the sparse form stores onl non-zero polnomials as the nodes of the TED.. Reduction and Normalization It is possible to further reduce the size of an ordered TED b a process of TED reduction and normalization. nalogous to DDs and *MDs, Talor Epansion Diagrams can be reduced b removing redundant nodes and merging isomorphic subgraphs. In general, a node is redundant if it can be removed from the graph, and its incoming edges can be redirected to the nodes pointed to b the outgoing edges of the node, without changing the function represented b the diagram. Definition III.: TED node is redundant if all of its non- edges are connected to terminal. If node v contains onl a constant term (-edge), the function computed at that node does not depend on the variable var(v), associated with the node. Moreover, if all the edges at node v point to the terminal node, the function computed at the node evaluates to zero. In both cases, the parent of node v is reconnected to the -child of v, as depicted in Fig.. Fig.. u v Removal of redundant node with onl a constant term edge. Identification and merging of isomorphic subgraphs in a TED are analogous to that of DDs and *MDs. Two TEDs are considered isomorphic if the match in both their structure and their attributes; i.e. if there is a one-to-one mapping between the verte sets and the edge sets of the two graphs that preserve verte adjacenc, edge labels and terminal leaf values. construction, two isomorphic TEDs represent the same function. u

4 F(=) = F (=) = + / F (=) = (a) (b) (c) (d) Fig.. onstruction of a TED for F = ( + )( + ): (a)-(c) decomposition w.r.t. individual variables; (d) normalized TED In order to make the TED canonical, an redundanc in the graph must be eliminated and the graph must be reduced. The reduction process entails merging the isomorphic sub-graphs and removing redundant nodes. Definition III.: Talor epansion diagram is reduced if it contains no redundant nodes and has no distinct vertices v and v, such that the subgraphs rooted at v and v are isomorphic. In other words, each node of the reduced TED must be unique. It is possible to further reduce the graph b performing a procedure called normalization, similar to the one described for *MDs []. The normalization procedure starts b moving the numeric values from the non-zero terminal nodes to the terminal edges, where the are assigned as edge weights. This is shown in Fig. (d) and Fig. 5(b). doing this, the terminal node holds constant. This operation applies to all terminal edges with terminal nodes holding values different than or. s a result, onl terminal nodes and are needed in the graph. The weights at the terminal edges ma b further propagated to the upper edges of the graph, depending on their relative values. The TED normalization process that accomplishes this is defined as follows. Definition III.: reduced, ordered TED representation is normalized when: The weights assigned to the edges spanning out of a given node are relativel prime. Numeric value appears onl in the terminal nodes. The graph contains no more than two terminal nodes, one each for and. ensuring that the weights assigned to the edges spanning out of a node are relativel prime, the etraction of common subgraphs is enabled. Enforcing the rule that none of the edges be allowed zero weight is required for the canonization of the diagram. When all the edge weights have been propagated up to the edges, onl the value and can reside in the terminal nodes. The normalization of the TED representation is illustrated b an eample in Fig. 5. First, as shown in Fig. 5(b), the constants (, 5) are moved from terminal nodes to terminal edges. These weights are then propagated up along the linear edges to the edges rooted at nodes associated with variable, see Fig. 5(c). t this point the isomorphic subgraphs (+) are identified at the nodes of and the graph is subsequentl reduced b merging the isomorphic subgraphs, as shown in Fig. 5(d). It can be shown that normalization operation can reduce the size of a TED eponentiall. onversel, transforming a normalized TED to a non-normalized TED can, in the worst-case, result in an eponential increase in the graph size. This result follows directl from the concepts of normalization of MDs to *MDs [].. anonicit of Talor Epansion Diagrams It now remains to be shown that an ordered, reduced and normalized Talor Epansion Diagram is canonical; i.e. for a fied ordering of variables, an algebraic epression is represented b a unique reduced, ordered and normalized TED. First, we recall the following Talor s Theorem, proved in [8]. Theorem (Talor s Theorem [8]) Let f() be a polnomial function in the domain R, and let = be an point in R. There eists one and onl one unique Talor s series with center that represents f() according to the equation. The above theorem states the uniqueness of the Talor s series representation of a function, evaluated at a particular point (in our case at = ). This is a direct consequence of the fact that the successive derivatives of a function evaluated at a point are unique. Using the Talor s theorem and the properties of reduced and normalized TEDs, it can be shown that an ordered, reduced and normalized TED is canonical. Theorem : For an multivariate polnomial f with integer coefficients, there is a unique (up to isomorphism) ordered, reduced and normalized Talor Epansion Diagram denoting f, and an other Talor Epansion Diagram for f contains more vertices. In other words, an ordered, reduced and normalized TED is minimal and canonical. Proof: The proof of this theorem follows directl the arguments used to prove the canonicit and minimalit of DDs [] and *MDs []. Uniqueness. First, a reduced TED has no trivial redundancies; the redundant nodes are eliminated b the reduce operation. Similarl, a reduced TED does not contain an isomorphic subgraphs. Moreover, after the normalization step, all common subepressions are shared b further application of the reduce operation. virtue of the Talor s Theorem all the nodes in an ordered, reduced and normalized TED are unique and distinguished. anonicit. We now show that the individual Talor epansion terms, evaluated recursivel, are uniquel represented b the internal nodes of the TED. First, for polnomial functions the Talor series epansion at a given point is finite and, according to the Talor s Theorem, the series is unique. Moreover, each term in the Talor s series corresponds to the successive derivatives of the function evaluated at that point. definition, the derivative of a differentiable function evaluated at a particular point is also unique. Since the nodes in the TED correspond to the recursivel computed derivatives, ever node in the diagram uniquel represents the function computed at that node. Since ever node in an ordered, reduced and normalized TED is distinguished and it uniquel represents a function, the Talor Epansion Diagram is canonical. Minimalit. We now show that a reduced, ordered and normalized TED is also minimal. This can be proved b contradiction. Let G be a graph corresponding to a reduced, normalized and hence canonical TED representation of a function f. ssume there eists another graph G, with the same variable order as in G, representing f that is smaller in size than G. This would impl that graph G could be reduced to G b the application of reduce and normalize operations. However, this is not possible as G is a reduced and normalized representation and contains no redundancies. The sharing of identical terms across different decomposition levels in the graph G has been captured b the reduction operation. Thus G cannot have a representation for f with fewer nodes than G. Hence G is a minimal and canonical representation for f. D. ompleit of Talor Epansion Diagrams Let us now analze the worst-case size compleit of an ordered and reduced Talor Epansion Diagram. For a polnomial function of degree k, decomposition with respect to a variable can produce k+ distinct Talor epansion terms in the worst-case. Theorem : Let f be a polnomial in n variables and maimum degree k. In the worst case, the ordered, reduced, normalized Talor Epansion Diagram for f requires O(k n ) nodes and O(k n ) edges. Proof: The top-level contains onl one node, corresponding to the first variable. Since its maimum degree is k, the number of distinct children nodes at the second level is bounded b k+. Similarl, each of the nodes at this level produces up to k + children nodes at the net level, giving a rise to (k+) nodes, and so on. In the worst case the number of children increases in geometric progression, with the level i containing up to (k + ) i nodes. For an n-variable function,

5 5 (+)+5(+)+(+) 5 ( +5+)(+) (a) (b) (c) (d) Fig. 5. Normalization of the TED for F = ( )( + ) there will be n- such levels, with the n-th level containing just two terminal nodes, and. Hence the total number of internal nodes in n the graph is N = i= (k+)i = (k+)n. The number of edges E k n can be similarl computed as E = i= (k + )i = (k+)n+, k since there ma be up to (k + ) n terminal edges leading to the and nodes. Thus, in the worst-case, the total number of internal nodes required to represent an n-variable polnomial with degree k is O(k n ) and the number of edges is O(k n ). One should keep in mind, however, that the TED variables represent smbolic, word-level signals, and the number of such signals in the design is significantl smaller than the number of bits in the bit-level representation. Subsequentl, even an eponential size of the polnomial with a relativel small number of such variables ma be acceptable. Moreover, for man practical designs the compleit is not eponential. Finall, let us consider the TED representation for functions with n variables encoded as n-bit vectors, X = i= i i. For linear epressions, the space compleit of TED is linear in the number of bits n, the same as *MD. For polnomials of degree k, such as X, etc., the size of *MD representation grows polnomiall with the number of bits, as O(n k ). For K*MD the representation also becomes nonlinear, with compleit O(n k ), for polnomials of degree k. However, for ordered, reduced and normalized TEDs, the graph remains linear in the number of bits, namel O(n k), for an degree k, as stated in the following theorem. Theorem : onsider variable X encoded as an n-bit vector, X = n i= i i. The number of internal TED nodes required to represent X k in terms of bits i, is k(n ) +. Proof: We shall first illustrate it for the quadratic case k =. n Let W n be an n-bit representation of X: X = W n = i= i i = (n ) n n + W n where W n = i= i i is the part of X containing the lower (n-) bits. With that, Wn = (n n + W n ) = (n ) n + n n W n + Wn. Furthermore, let W n = ( n n + W n ), and W n = ((n ) n + n n W n + W n ). Notice that the constant term (-edge) of W n w.r.to variable n contains the term W n, while the linear term (-edge) of Wn contains n W n. This means that the term W n can be shared at this decomposition level b two different parents.s a result, there are eactl two non-constant terms, W n and Wn at this level. (n ) W n W n Fig.. n W n n n (n ) W n (n ) W n W n W n n n W n n n onstruction of TED for X with n bits n n In general, at an level l, associated with variable n l, the epansion of terms W n l and W n l will create eactl two different non-constant terms, one representing W n l and the other W n l ; plus a constant term n l. The term W n l l will be shared, with different multiplicative constants, b Wn l and W n l. This reasoning can be readil generalized to arbitrar integer degree k; at each level there will alwas be eactl k different nonconstant terms. Since on the top variable ( n ) level there is onl one node (the root), and there are eactl k non-constant nodes at each of the remaining (n ) levels, the total number of nodes is equal to k(n ) +. E. Limitations of Talor Epansion Diagram Representation It should be obvious from the definition of TED that it can onl represent those functions that have finite Talor epansion, and in particular multi-variate polnomials with finite integer degrees. For polnomials of finite integer degree k, successive differentiation of the function ultimatel leads to zero, resulting in a finite number of terms. However, those functions that have infinite Talor series (such as a, where a is a constant) cannot be represented with a finite TED graph. nother natural limitation of TEDs is that the cannot represent relational operators (such as comparators,, ==, etc.) in smbolic form. This is because Talor series epansion is defined for functions and not for relations. Relations are characterized b discontinuities over their domain and are not differentiable. In order to use TEDs to represent relational operators, often encountered in RTL descriptions, the epansion of word-level variables and bit vectors into their bit-level components is required. Finall, TEDs cannot represent modular arithmetic. This issue will be discussed in Section V- in the contet of RTL verification. IV. omposition Operations for Talor Epansion Diagrams Talor Epansion Diagrams can be composed to compute comple epressions from simpler ones. This section describes general composition rules to compute a new TED as an algebraic sum (+) or product ( ) of two TEDs. The general composition process for TEDs is similar to that of the appl operator for DD s [], in the sense that the operations are recursivel applied on respective graphs. However, the composition rules for TEDs are specific to the rules of the algebra (R,, +). Starting from the roots of the two TEDs, the TED of the result is constructed b recursivel constructing all the non-zero terms from the two functions, and combining them, according to a given operation, to form the diagram for the new function. To ensure that the newl generated nodes are unique and minimal, the reduce operator is applied to remove an redundancies in the graph. Let u and v be two nodes to be composed, resulting in a new node q. Let var(u) = and var(v) = denote the decomposing variables associated with the two nodes. The top node q of the resulting TED is associated with the variable with the higher order, i.e., var(q) =, if, and var(q) = otherwise. Let f, g be two functions rooted at nodes u, v, respectivel, and h be a function rooted at the new node q. For the purpose of illustration, we describe the operations on linear epressions, but the analsis is equall applicable to polnomials

6 of arbitrar degree. In constructing these basic operators, we must consider several cases:. oth nodes u, v are terminal nodes. In this case a new terminal node q is created as val(q) = val(u) + val(v) for the add operation, and as val(q) = val(u) val(v) for the mult operation.. t least one of the nodes is non-terminal. In this case the TED construction proceeds according to the variable order. Two cases need to be considered here: (a) when the top nodes u, v have the same inde, and (b) when the have different indices. The detailed analsis of both cases is given in []. Here we show the multiplication of two diagrams rooted at variables u and v with the same inde. h() = f() g() = (f() + f ()) (g() + g ()) () = [f()g()] + [f()g () + f ()g()] + [f ()g ()]. In this case, the -child of q is obtained b pairing the -children of u, v. Its -child is created as a sum of two cross products of - and -children, thus requiring an additional add operation. lso, an additional -child (representing the quadratic term) is created b pairing the -children of u, v. u Fig. 7. u u * v v v = u*v u*v u*v+u*v u*v Multiplicative composition for nodes with same variables. Figure 8 illustrates the application of the add and mult procedures to two TEDs. s shown in the figure, the root nodes of the two TEDs have the same variable inde. The mult operation requires the following steps: (i) performing the multiplication of their respective constant (-) and linear (-) children nodes; and (ii) generating the sum of the cross-products of their - and -children. On the other hand, the two TEDs corresponding to the resulting cross-product, as highlighted in the figure, have different variable indices for their root nodes. In this case, the node with the lower inde corresponding to variable is added to the -child of the node corresponding to variable. + * 5 (+)(+) + =,,5, 7,5,, +,5 8,,5,, = +,,,,7, 8,7,, to the children proceeds until the weights reach the terminal nodes. The numeric values are updated onl in the terminal nodes. Ever time a new node is created, the reduce and normalize operations are required to be performed in order to remove an redundancies from the graph and generate a minimal and canonical representation. We now analze the computational compleit of the basic TED operations described above. Let f and g be the size, epressed in the number of nodes, of the two TEDs, f and g, respectivel. The number of recursive calls made to add is bounded b ( f g ). The mult operation has higher compleit than add. The worst case for the multipl operation would occur when each node in f is multiplied b each node in g, resulting in ( f g ) recursive mult calls. However, each multipl operation further relies on ( f g ) recursive calls to the add operation, in the worst case (see Fig. 8). In order to derive an absolute worst-case upper bound for the composition operations, we have to consider the case where edge-weights have to be propagated all the wa down to terminal nodes. In such cases, non-normalized TEDs are dnamicall created from their normalized counterparts. s discussed in Section III-, non-normalized TEDs can be eponentiall more comple than normalized TEDs. This ma result in an eponential worst-case compleit of the composition operations. However, it should be noted that the number of calls to the mult operation can be efficientl reduced b using a computed table to store the results, as is done in the recent implementation. detailed analsis of the compleit of basic TED operations is presented in [5]. It should be noted that the multiplication of two multi-variate polnomials has been shown to be eponential. For instance, time compleit of Karatsuba algorithm for multipling two n-variate polnomials with maimum degree d is O((d + ) n log ) [5]. t the first glance, time compleit for TED construction appears to be prohibitive. However, we observed that for dataflow computations specified at sufficientl high level (see Section VI) the composition operations do not ehibit eponential compleit. The number of smbolic variables is orders of magnitude smaller than that of oolean variables present in the *MD and DD representations. Eponential compleit can be observed in cases when the oolean variables start dominating in the design, in which case the behavior of TED starts approaching that of a *MD. V. Design Modeling and Verification with TEDs Using the operations described in the previous section, Talor Epansion Diagrams can be constructed to represent various computations over smbolic variables in a compact, canonical form. The compositional operators add and mult can be used to compute an combination of arithmetic functions b operating directl on their TEDs. However, the representation of oolean logic, often present in the RTL designs, requires special attention since the output of a logic block must evaluate to oolean rather than to an integer value.. Representing oolean Logic We now define TED operators for oolean logic, or, and, and or, where both the range and domain are oolean. Figure 9 shows TED representations for these basic oolean operators. In the diagrams, and are oolean variables represented b binar variables, and + and represent algebraic operators of add and mult, respectivel. The resulting functions are, integer functions. These diagrams are structurall identical to their *MD counterparts [5] []. Fig. 8. Eample of mult composition: (+)(+). It should be noted that the add and mult procedures described above will initiall produce non-normalized TEDs, with numeric values residing onl in the terminal nodes, requiring further normalization. When these operations are performed on normalized TEDs, with weights assigned to the edges, then the following modification is required: when the variable indices of the root nodes of f and g are different, the edge weights have to be propagated down to the children nodes recursivel. Downward propagation of edge weights results in the dnamic update of the edge weights of the children nodes. In each recursion step, this propagation of edge weights down NOT ND OR XOR Fig. 9. TED representation for oolean operators: a) not: = ( ); b) and: = ; c) or: = + ; d) or: = +. Similarl one can derive other operators which rel on oolean variables as one of their inputs, with other inputs being word-level.

7 7 One such eample is the multipleer, mu(c, X, Y ) = c X +( c) Y, where c is a binar control signal, and X and Y are word-level inputs. In general, TED, which represents an integer-valued function, will also correctl model designs with arithmetic and oolean functions. Note that the add (+) function will alwas create correct integer result over oolean and integer domains, because oolean variables are treated as binar (,), a special case of integer. However the mult ( ) function ma create powers of oolean variables, k, which should be reduced to. minor modification of TED is done to account for this effect so that the oolean nature of variable can be maintained in the representation. Such modified Talor Epansion Diagrams are also canonical.. Verification of RTL and ehavioral Designs TED construction for an RTL design starts with building trivial TEDs for primar inputs. Partial epansion of the word-level input signals is often necessar when one or more bits from an of the input signals fan out to other parts of the design. This is the case in the designs shown in Fig. (a) and (b), where bits a k = [k] and b k = [k] are derived from word-level variables and. In this case, the word-level variables must be decomposed into several word-level variables with shorter bit-widths. In our case, = (k+) hi + k a k + lo and = (k+) hi + k b k + lo, where hi = [n :k+], a k = [k], and lo = [k-:]; and similarl for variable. Variables hi, a k, lo, hi, b k, lo form the abstracted primar inputs of the sstem. The basic TEDs are readil generated for these abstracted inputs from their respective bases ( hi, a k, lo ), and ( hi, b k, lo ). Once all the abstracted primar inputs are represented b their TEDs, Talor Epansion Diagrams can be constructed for all the components of the design. TEDs for the primar outputs are then generated b sstematicall composing the constituent TEDs in the topological order, from the primar inputs to the primar outputs. For eample, to compute + in Fig. (a) and (b), the add operator is applied to functions and (each represented in terms of their abstracted components). The subtract operation,, is computed b first multipling with a constant and adding the result to the TED of. The multipliers are constructed from their respective inputs using the mult operator, and so on. To generate a TED for the output of the multipleers, the oolean functions s and s first need to be constructed as TEDs. Function s is computed b transforming the single-bit comparator a k > b k into a oolean function and epressed as an algebraic equation, s = a k b k = a k ( b k ), as described in Section V-. Similarl, s = a k b k is computed as s = a k ( b k ) and represented as a TED. Finall, the TEDs for the primar outputs are generated using the mu operator with the respective inputs. s a result of such a series of composition operations, the outputs of the TED represent multivariate polnomials of the primar inputs of the design. fter having constructed the respective ordered, reduced, and normalized Talor Epansion Diagram for each design, the test for functional equivalence is performed b checking for isomorphism of the resulting graphs. If the corresponding diagrams are isomorphic, the represent equivalent functions. Fig. (c) shows the isomorphic TED for the two designs, demonstrating that the are indeed equivalent. In fact, the generation of the TEDs for the two designs under verification takes place in the same TED manager; when the two functions are equivalent, both top functions point to the same root of the common TED.. Limitations of TEDs in RTL Verification The proposed TED representation naturall applies to functions that can be modeled as finite polnomials. However, the efficienc of TED relies on its abilit to encode the design in terms of its word-level smbolic inputs, rather than bit-level signals. This is the case with the simple RTL designs shown in Figure, where all input variables and internal signals have simple, low-degree polnomial representation. The abstracted word-level inputs of these designs are created b partial bit selection (a k, b k ) at the primar inputs, and a polnomial function can be constructed for its outputs. However, if an of the internal or output signals is partitioned into sub-vectors, such sub-vectors cannot be represented as polnomials in terms of the smbolic, word-level input variables, but depend on the individual bits of the inputs. The presence of such signal splits creates a fundamental problem for the polnomial representations, and TEDs cannot be used efficientl in those cases. For similar reasons TED cannot represent modular arithmetic. n attempt to fi this problem was proposed in [5], b modeling the discrete functions as finite, wordlevel polnomials in Galois Field (GF). The resulting polnomials, however, tend to be of much higher degree than the original function, with the degree depending on the signal bit-width, making the representation less efficient for practical applications. This is the case where TEDs can ehibit space eplosion similar to that encountered in DDs and MDs. Despite these limitation, TEDs can be successfull used for verifing equivalence of high-level, behavioral and algorithmic descriptions. Such algorithmic descriptions tpicall do not ehibit signal splits, hence resulting in polnomial functions over word-level input signals. VI. Implementation and Eperimental Results We have implemented a prototpe version of TED software for behavioral HDL designs using as a front end a popular high-level snthesis sstem GUT [55]. This sstem was selected due to its commercial qualit, robustness, and its open architecture. The input to the sstem is behavioral VHDL or description of the design. The design is parsed and the etracted data flow is automaticall transformed into canonical TED representation. The core computational platform of the TED package consists of a manager that performs the construction and manipulation of the graph. It provides routines to uniquel store and manipulate the nodes, edges and terminal values, in order to keep the diagrams canonical. To support canonicit, the nodes are stored in a hash table, implemented as unique table, similar to that of the UDD package [9],[5]. The table contains a ke for each verte of the TED, computed from the node inde and the attributes of its children and the edge weights. s a result, equivalence test between two TEDs reduces to a simple scalar test between the identifiers of the corresponding vertices. Variable ordering. s shown in this paper, TEDs are a canonical representation subject to the imposition of a total ordering on the variables. Therefore it is desirable to search for a variable order that would minimize the size of TEDs. We have recentl developed a dnamic variable ordering for TEDs based on local swapping of adjacent variables in the diagram, similar to those emploed in DD ordering [57], [58]. It has been shown that, similarl to DDs, local swapping of adjacent variables does not affect the structure of the diagram outside of the swapping area. We are currentl eperimenting with different static ordering heuristics, including the ordering of variables that correspond to constant coefficients. Due to initial nature of these heuristics, in our initial eperiments we have used the default (topological) order in which the signals appear in the design specification.. Eperimental Setup Several eperiments were performed using our prototpe software on a number of dataflow designs described in behavioral VHDL. The designs range from simple algebraic (polnomial) computations to those encountered in signal and image processing algorithms. Simple RTL designs with oolean-algebraic interface were also tested. We wish to emphasize that the goal of these eperiments was to demonstrate, as a proof of concept, the application of TED to highlevel dataflow design representation and verification, and in particular to functional equivalence checking of behavioral HDL specifications, rather than to develop a complete equivalence verification sstem. Our eperimental setup is as follows. The design described in behavioral VHDL or is parsed b a high-level snthesis sstem GUT [55]. The etracted data flow is then automaticall translated into a canonical TED representation using our software. Statistics related to graph size and composition time are reported. We have compared TEDs against *MDs to demonstrate the power of abstraction of TED representation. For this purpose, each design was snthesized into a structural netlist from which *MDs were constructed. In most cases DDs could not be constructed due to their prohibitive size, and the are not reported. Eperiments confirm that word-size abstraction b TEDs results in much smaller graph size and computation times as compared to *MDs.. Verification of High-level Transformations During the process of architectural snthesis, the initial HDL description often proceeds through a series of high-level transformations.

8 8 + * D s F F D - ak. ak. D ak a k b k a k > bk (a) bk. - hi bk. bk hi * * a k D s F lo. - lo. - - hi 5 lo. 5 lo. 8 - hi lo lo b k (b) - T (c) Fig.. RTL verification using canonical TED representation: (a), (b) Functionall equivalent RTL modules; (c) The isomorphic TED for the two designs. For eample, computation + can be transformed into an equivalent one, ( + ), which better utilizes the hardware resources. TEDs are ideall suited to verif the correctness of such transformations b proving equivalence of the two epressions, regardless of the word size of the input/output signals. We performed numerous eperiments to verif the equivalence of such algebraic epressions. Results indicate that both time and memor usage required b TEDs is orders of magnitude smaller as compared to *MDs. For eample, the epression ( + )( + D), where,,, D are n-bit vectors, has a TED representation containing just internal nodes, regardless of the word size. The size of *MD for this epression varies from 8 nodes for the 8-bit vectors, to,88 nodes for -bit variables. DD graphs could not be constructed for more than 5 bits.. RTL Verification s mentioned earlier, TEDs offer the fleibilit of representing designs containing both arithmetic operators and oolean logic. We used the generic designs of Figure and performed a set of eperiments to observe the efficienc of TED representation under varing size of oolean logic. The size of the algebraic signals, was kept constant at bits, while the word size of the comparator (or the equivalent oolean logic) was varied from to. s the size of oolean logic present in the design increases, the number of bits etracted from, also increases (the figure shows it for single bits). Table I gives the results obtained with TED and compares them to those of *MDs. Note that, as the size of oolean logic increases, TED size converges to that of *MD. This is to be epected as *MDs can be considered as a special (oolean) case of TEDs. TLE I Size of TED vs. oolean logic bits *MD TED (k) Size PU time Size PU 7 s 9 s 8 5K 87 s s 9K 9 s s.9k 9 s 5 s 8 timeout > hrs.8k 9 min timeout > hrs timeout > hrs D. rra Processing n eperiment was also performed to analze the capabilit of TEDs to represent computations performed b an arra of processors. The design that was analzed is an n n arra of configurable Processing Elements (PE), which is a part of a low power motion estimation architecture [59]. Each processing element can perform two tpes of computations on a pair of 8-bit vectors, i, i, namel ( i j ) or ( i j ), and the final result of all PEs is then added together. The size of the arra was varied from to, and the TED for the final result was constructed for each configuration. When the PEs are configured to perform subtraction ( i j ), both TEDs and *MDs can be constructed for the design. However, when the PEs are configured to compute i j, the size of *MDs grows quadraticall. s a result, we were unable to construct *MDs for the arra of 8-bit processors. In contrast, the TEDs were constructed easil for all the cases. The results are shown in Table II. Note that we were unable to construct the DDs for an size n of the arra for the quadratic computation. TLE II PE computation: ( i j ). rra size *MD TED (n n) Size PU time Size PU time s. s 98. s.5 s s 8. s out of mem s E. DSP omputations One of the most suitable applications for TED representation are algorithmic descriptions of dataflow computations, such as digital signal and image processing algorithms. For this reason, we have eperimented with the designs that implement various DSP algorithms. Table III presents some data related to the compleit of the TEDs constructed for these designs. The first column in the Table describes the computation implemented b the design. These include: F IR and IIR filters, fast Fourier transform (F F T ), elliptical wave filter (Elliptic), least mean square computation (LMS8), discrete cosine transform (DT ), matri product computation (P rodmat), Kalman filter (Kalman), etc. Most of these designs perform algebraic computations b operating on vectors of data, which can be of arbitrar size. The net column gives the number of inputs for each design. While each input is a -bit vector, TED represents them as word-level smbolic variable. Similarl, the net column depicts the number of -bit outputs. The remaining columns of the table show: MD size (number of nodes), PU time required to construct the MD for the -bit output words, TED size (number of nodes) required to represent the entire design; PU times required to generate TED diagrams does not account for the parsing time of the GUT front end.