Topic C Memory Models

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1 Memory Memory Non- Topic C Memory CPEG852 Spring 2014 Guang R. Gao CPEG 852 Memory Advance 1 / 29

2 Memory 1 Memory Memory Non- 2 Non- CPEG 852 Memory Advance 2 / 29

3 Memory Memory Memory Non- Introduction: What is a Memory Model Part II: Some Open Problems on Memory CPEG 852 Memory Advance 3 / 29

4 Memory Memory What is a Memory Model? Non- CPEG 852 Memory Advance 4 / 29

5 Memory Memory Non- CPEG 852 Memory Advance 5 / 29

6 Memory Memory Non- CPEG 852 Memory Advance 6 / 29

7 Memory Memory Non- CPEG 852 Memory Part I: Basics on Stéphane ZUCKERMAN University of Delaware Computer Architecture and Parallel Laboratory (CAPSL) April 17, 2014 CPEG 852 Memory Advance 7 / 29

8 Memory 1 Memory Memory Non- 2 Non- CPEG 852 Memory Advance 8 / 29

9 Memory A Motivating Example (1) Memory Non- a 1 if (b = 0) then critical section; a 0 else something else CPEG 852 Memory Advance 9 / 29

10 Memory A Motivating Example (1) Memory Non- b 1 if (a = 0) then critical section; b 0 else something else CPEG 852 Memory Advance 9 / 29

11 Memory Memory Non- A Motivating Example (1) Thread 0 Thread 1 a 1 b 1 if (b = 0) then if (a = 0) then critical section; critical section; a 0 b 0 else something else else something else Table: Initially, a = b = 0. Is mutual exclusion guaranteed? CPEG 852 Memory Advance 9 / 29

12 Memory A Motivating Example (2) Memory x 1 r1 y Non- CPEG 852 Memory 10 Advance / 29

13 Memory A Motivating Example (2) Memory y 1 r2 x Non- CPEG 852 Memory 10 Advance / 29

14 Memory A Motivating Example (2) Memory Non- Thread 0 Thread 1 x 1 y 1 r1 y r2 x Table: Initially, x = y = 0. Is it possible to have r1 = r2 = 0? CPEG 852 Memory 10 Advance / 29

15 Memory What Memory is All About Memory Q What happens when at least two concurrent memory operations arrive at the same memory location x? Non- CPEG 852 Memory 11 Advance / 29

16 Memory What Memory is All About Memory Non- Q What happens when at least two concurrent memory operations arrive at the same memory location x? What happens when a data-race (i.e. at least one of the two memory operations is a write) occurs at some memory location x? CPEG 852 Memory 11 Advance / 29

17 Memory What Memory is All About Memory Non- Q What happens when at least two concurrent memory operations arrive at the same memory location x? What happens when a data-race (i.e. at least one of the two memory operations is a write) occurs at some memory location x? Memory try to answer that question. CPEG 852 Memory 11 Advance / 29

18 Memory Memory Non- The Answer of the Message Passing Crowd It can never happen: data is explicitly sent and received. This answer is fine, but... We do not live in a pure message-passing world Memory is shared on most super-computers, e.g.: Efficient MPI runtime systems make the distinction between intra-node and inter-node communications Inter-node communications work as advertised, but... CPEG 852 Memory 12 Advance / 29

19 Memory Memory Non- The Answer of the Message Passing Crowd It can never happen: data is explicitly sent and received. This answer is fine, but... We do not live in a pure message-passing world Memory is shared on most super-computers, e.g.: Efficient MPI runtime systems make the distinction between intra-node and inter-node communications Inter-node communications work as advertised, but... Efficient intra-node communications make the use of shared-memory segments, i.e. shared memory CPEG 852 Memory 12 Advance / 29

20 Memory 1 Memory Memory Non- 2 Non- CPEG 852 Memory 13 Advance / 29

21 Memory Atomic [Lamport(1986)] Memory Non- A system is AC if All memory operations are issued and performed in some total order Real time constraint: time slots are allocated, and mem ops must be performed according to them. Memory operations must follow program order CPEG 852 Memory 14 Advance / 29

22 Memory Atomic [Lamport(1986)] Memory Non- A system is AC if All memory operations are issued and performed in some total order Real time constraint: time slots are allocated, and mem ops must be performed according to them. Memory operations must follow program order Strongest MCM that was conceived Never implemented CPEG 852 Memory 14 Advance / 29

23 Memory Memory Non- A system is SC if Sequential [Lamport(1978)] All memory operations appear to follow some total order Memory operations (appear to) follow program order Definition: Sequential A system is sequentially consistent if... the result of any execution is the same as if the operations of all the processors were executed in some sequential order, and the operations of each individual processor appear in this sequence in the order specified by its program. CPEG 852 Memory 15 Advance / 29

24 Memory Back to our Example Memory Non- Thread 0 Thread 1 x 1 y 1 r1 y r2 x Table: Initially, x = y = 0. CPEG 852 Memory 16 Advance / 29

25 Memory Back to our Example Memory Non- Thread 0 Thread 1 x 1 y 1 r1 y r2 x Table: Initially, x = y = 0. Homework: Is it possible to have r1 = r2 = 0? CPEG 852 Memory 16 Advance / 29

26 Memory Sequential and its Popularity Memory Non- It behaves pretty much as one would expect in the context of a uniprocessor-multithread execution It is considered very intuitive It offers strong guarantees: a modification to memory must be seen by all other threads in a given program CPEG 852 Memory 17 Advance / 29

27 Memory Memory Non- The Drawbacks of Sequential It offers strong guarantees: a modification to memory must be seen by all other threads in a given program How complicated is it to implement such a system in hardware? What about caches? Write buffers? etc. How scalable is it? How expensive is it to implement that kind of consistency model? CPEG 852 Memory 18 Advance / 29

28 Memory The Difference with Previous Memory Non- Previous models tried to define an order for memory operations, regardless of their role in a program whatsoever Non-uniform make a difference between synchronizing memory operations and ordinary ones CPEG 852 Memory 19 Advance / 29

29 Memory Release [Gharachorloo et al.(1990)gharachorloo Memory Non- RC refines synchronizing accesses into two types: acquire and release. They are used to label instructions (Gharachorloo speaks about properly labeled programs). A system is RC if: acquire accesses must have performed before any ordinary operation is performed all ordinary memory operations have performed before an release operation is performed Synchronizing accesses (acquire or release) are SC CPEG 852 Memory 20 Advance / 29

30 Memory Memory Non- More Examples (See [Adve et al.(1999)adve, Pai, and Ranga Thread 0 Thread 1 Data1 = 64 while(flag!= 1) ; Data2 = 55 reg1 = Data1 Flag = 1 reg2 = Data2 Table: Ex1: What are the legal values in SC? RC? CPEG 852 Memory 21 Advance / 29

31 Memory Memory Non- Solution More Examples (See [Adve et al.(1999)adve, Pai, and Ranga Thread 0 Thread 1 Data1 = 64 while(flag!= 1) ; Data2 = 55 reg1 = Data1 Flag = 1 reg2 = Data2 Table: Ex1: What are the legal values in SC? RC? SC reg1 = 64 ; reg2 = 55 RC reg1 = 64 or 0 ; reg2 = 55 or 0 CPEG 852 Memory 21 Advance / 29

32 Memory More Examples Memory Non- Thread 0 Thread 1 Flag1 = 1 Flag2 = 1 reg1 = Flag2 reg2 = Flag1 if reg1 == 0 if reg2 == 0 critical section critical section Table: Homework Ex2: What are the legal values in SC? RC? CPEG 852 Memory 22 Advance / 29

33 Memory Memory Non- Very easy to understand: The C++ Memory Model Synchronizing accesses (through the atomic keyword) are SC any incorrectly synchronized behavior implies an undefined behavior, CPEG 852 Memory 23 Advance / 29

34 Memory Memory Non- Very easy to understand: The C++ Memory Model Synchronizing accesses (through the atomic keyword) are SC any incorrectly synchronized behavior implies an undefined behavior,... which really means by issuing a data-race you can have initiated a new TCP connection in order to order 20 elephants to be delivered by next Saturday CPEG 852 Memory 23 Advance / 29

35 Memory A Brief Recap Memory Non- CPEG 852 Memory 24 Advance / 29

36 Memory What to take home Memory Non- A memory consistency model defines which memory operations are allowed, in which order It concerns both hardware and software points of view The weaker the MCM, the more optimizations can be performed the more scalable it is the heavier it is on a programmer s shoulders CPEG 852 Memory 25 Advance / 29

37 Memory The I Did Not Talk About Memory Non- SPARC processors memory consistency models: Total Store Order (TSO) Partial Store Order (PSO) Location [Gao and Sarkar(2000)] (will be explained in Part II) Others (Local consistency,... ) CPEG 852 Memory 26 Advance / 29

38 Memory If You Want to Know More... Memory Non- S.Adve, K.Gharachorloo: Shared Memory : a Tutorial [Adve and Gharachorloo(1996)] D.Mosberger: Memory [Mosberger(1993)] J.Hennessy and D.Patterson: Computer Architecture: A Quantitative Approach CPEG 852 Memory 27 Advance / 29

39 Memory Memory Non- S. Adve and K. Gharachorloo. Shared memory consistency models: a tutorial. Computer, 29(12):66 76, Dec ISSN doi: / I S. Adve, V. Pai, and P. Ranganathan. Recent advances in memory consistency models for hardware shared memory systems. Proceedings of the IEEE, 87(3): , Mar ISSN doi: / G. R. Gao and V. Sarkar. Location consistency-a new memory model and cache consistency protocol. IEEE Trans. Comput., 49: , August ISSN doi: / URL CPEG 852 Memory 28 Advance / 29

40 Memory Memory Non- II K. Gharachorloo, D. Lenoski, J. Laudon, P. Gibbons, A. Gupta, and J. Hennessy. Memory consistency and event ordering in scalable shared-memory multiprocessors. In Proceedings of the 17th Annual International Symposium on Computer Architecture, pages 15 26, Seattle, Washington, May L. Lamport. Time, clocks, and the ordering of events in a distributed system. Communications of the ACM, 21(7): , July L. Lamport. On interprocess communication. Distributed Computing, 1:77 101, D. Mosberger. Memory consistency models. SIGOPS Oper. Syst. Rev., 27:18 26, January ISSN doi: URL CPEG 852 Memory 29 Advance / 29

Shared Memory Systems

Shared Memory Systems Haitao Wei (Most of the slides are from Dr. Stephane Zuckerman) University of Delaware hep://www.udel.edu Computer Architecture and Parallel Systems Laboratory hep://www.capsl.udel.edu