Proposal for Parallel SCSI: Increase Transfer Rate and Improve Error Detection

Transcription

1 Proposal for Parallel SCSI: Increase Transfer Rate and Improve Error Detection To: T10 Technical committee From: Jim McGrath Quantum Corporation 500 McCarthy Boulevard Milpitas, CA USA Phone: Fax: Date: September 11 August 17, Overview Rev 5 This revision incorporates changes suggested during the conference call to review revision 4, held on August 27, Representatives from Adaptec, Compaq, IBM, QLogic, Quantum, Seagate, Symbios, and WD attended. an error was made in the revision note for revision 4, and that change has been made in section , a (obvious) error was made, caught, and corrected. The transfer period times were made TDB they will be speified in the Fast-80 proposal instead. Otherwise all changes are insertions/deletions of appropriate wording to support decision(s) taken several issues. The issues surrounding these decisions are document in another proposal ( Outstanding Issues in Document , Proposal for Parallel SCSI: Increase Transfer Rate and Improve Error Detection ), and modifying/approving that proposal will make the corresponding changes in this proposal. This issues, and their identifying Letter, are: A. Degree of support for 8 bit transfers B. Degree of support for single ended C. Use of the P1 signal D. Value of the Pad bytes For each issue there are a number of options. For issues A and B the options are very similar: A1) 16 bit only, 8 bit forbidden A2) 16 bit only, silence on 8 bit A3) 16 bit recommended but and 8 bit allowed A4) 16 bit and 8 bit allowed

2 T10/98-177r54 and B1) LVD only, single ended and HVD forbidden B2) LVD only, silence on single ended, and HVD forbidden B3) LVD recommended but, single ended allowed, and HVD forbidden B4) LVD and single ended allowed, and HVD forbidden For issues C and D the options are fewer: and C1) the current wording indicating that P1 is 16 bit parity C2) new wording indicating that the P1 line shall not be driven by the device receiving data, and shall be released or driven at a rate no higher than the negotiated data transfer rate for the device sending the data. It is intended to reclaim this line for future use. D1) pad bytes are 00 D2) pad bytes are anything The text that is inserted/deleted is delimiated with a letter and number combination, e.g. A3, which would refer to issue A, option 3 ( 16 bit recommended but and 8 bit allowed ). This information is noted by being enclosed in double square brackets ([[ ]]), making the changes easy to search for and subsequently edit (e.g. [[A3]]). Rev 4 This revision incorporates changes suggested at the T1110 standards meeting in Portland, Maine on AugustJuly 14, A general consensus emerged at that meeting that this document is close to being recommended for inclusion in the next revision of SPI-3. Towards that end, this revision is intended for review at a teleconference call before the next T10 meeting in September. At that time a final revision will be presented and (hopefully) meet full committee approval. A reminder that notes included between square brackets are explanatory information for the committee, and will not be incorporated into SPI-3. If someone feels that some of that material (or material like that) is needed in the standard, then please advise me ASAP so I can draft appropriate wording. All changes in this document are highlighted from revision 3. These include: An explanation of how the CRC protocol works in both 16 and 8 bit modes Inclusion of a diagram on how CRC is calculated approved at the earlier Orange Country meeting Removal in section 24 of the exception for BUS FREE phase (since it is covered elsewhere in SPI), but an enumeration of the other phases to insure there is no misunderstanding. Elimination in section 27 of timings other than those related to CRC_Valid in the Timing budget table Rev 3 This revision notes the changes made in response to feedback at the special working group in Orange County June 19. At various points table, figure, and clause numbers are identified by xxx. The SPI-3 editor will insert the appropriate numbers when the document is incorporated into SPI-3. Some figures may also have to be Page 2 of 31 Increase Transfer Rate and Improve Error Detection Proposal

3 modified for incorporation into the SPI-3 document. The SPI-3 editor may make the appropriate nonsubstantive changes required. The note on using DT/CRC only with wide buses has been deleted. Although raised as an issue in the committee, the working groups opinion is to continue to allow narrow buses to be used with the new protocols. This issue may be raised again at a later date. Given its controversy and lack of solid support in the committee, I suggest that any attempt to restrict the new protocol to wide buses be offered as a separate proposal to the committee. The section on CRC testing was modified with new tests included. The sections on information transfer phases and DT transfer phase was clarified to require that the REQx/ACKx signals be deasserted before leaving the DT phase, even on error conditions. Rev 2 This revision notes the changes made in response to the phone conference call reviewing the rev 1 document that took place on June 5. Individuals from Adaptec, Compaq, IBM, Qlogic, Quantum, Seagate, and Symbios Logic particiapated. Rev 1 This revision notes the changes from revision 0. It is an outgrowth of the discussions at the T10 working group meeting on May 22, 1998 in Chicago. It will be reviewed on a conference call on June 5, with one or more subsequent revisions generated for the next working group meeting on June 19 in Irvine. Name changes: DEC to DT, double-edged to double transition, SEC to ST, single-edged to single transition, IUTR to PPR, frame to group, and frame check sequence to group check sequence. Section 5: reword to make asynchronous data transfers in DT data phase explicitly illegal. Section 7: eliminate the enumeration of the phase lines, since they do not have simple meanings as individual lines. Section 8: keep parity in SELECTION phase (it was accidentally dropped in the rev 0 of SPI-3). Note that DB(P) and DB(P2) are used for parity only in the ST DATA IN and ST DATA OUT phases. Eliminated the error rate information for the CRC algorithm. Restructured the description of a data group, and moved the pad bytes to be between the data bytes and the CRC bytes. CRC now covers the data field and the pad field. The CRC calculation section needs more work, and will be revised in the next revision. Section 22: a note was added that SECTION still uses parity, and is assumed that will be fixed in SPI-3, rev 1. Section 27: extensive rewording of how CRC errors are detected was made for clarity. The additional setup time for CRC_AVAILABLE assertion was changed from 12.5 to 10 ns in Fast-40:DT and Fast- 80:DT. A couple of sections were eliminated, although they may just need rewording. Another 10 ns setup time for the subsequent deassertion is proposed for these speeds. Rev 0 What follows beginning with Clause 1 is our first pass at a proposal for including double-edge clocked clocking and CRC into SPI. Increase Transfer Rate and Improve Error Detection Proposal Page 3 of 31

4 T10/98-177r54 General themes: This proposal references the SPI-3 r0 draft. I have tried to note references to (SPI-2) rev 20a or the packetized SCSI proposal (T10/97-230r6) when possible, but the SPI-3 draft is a fairly simple merge of the two documents, so it should be straightforward for people to follow. I avoided changes to sections 6 and 7, since they are the analog sections affected T10/98-153r1. Comments on that proposal are included, since there is some degree of content overlap. Specifically, other sections in the document do require Fast-80:DT timing information, and 153r1 does not define Fast-10:DT, Fast-20:DT, and Fast-40:DT. These items have been provided, but it should be noted that some change in terminology may be required for double edge clocking, and the exact timing values are subject to further discussion. A whole bunch of new definitions were added. Note that DT (double-edge clocked) synchronous data transfer must be defined. I was surprised to note that there are no synchronous data transfer timing diagrams in SPI (there are sections in the clauses that specify measurement points, but no overall timing diagram). I have supplied such a timing diagram (I am sure that some changes will be necessary to put it in proper form). Parity has been replaced by Protection in all areas of SPI where the clause could deal with either Parity or CRC. In the clause where Parity was defined, I have added a clause defining CRC, as well as the 16-bit P1 parity (and an analogous 16-bit P3 parity for the secondary bus). DATA phase now consists of ST DATA IN, ST DATA OUT, DT DATA IN, and DT DATA OUT (ST is Single-Edge Clocked, and DT is Double-Edge Clocked). DATA IN generically now refers to ST DATA IN and DT DATA IN; DATA OUT to ST DATA OUT and DT DATA OUT. ST DATA generically refers to ST DATA IN and ST DATA OUT; DT DATA to DT DATA IN and DT DATA OUT. I made corresponding changes throughout SPI. This change gives us terminology to be precise in direction and protocol for data transfer when that is needed, but to retain the existing data phase terminology throughout our standards where that level of detail is irrelevant. Packetized SCSI was actually pretty easy to accommodate basically all references to INFORMATION UNIT IN (or OUT) phases were replaced by information units or data phases, whichever was appropriate (sometimes both, as in data phases that can only contain information units). At this time I have kept the initial restriction that information units only be transferred in the DT data phase, but that could be changed rather easily if people wanted to allow information units during the traditional ST data phase. I did not change the PPR message section (George Penokie was going to work on that). It is important to note that this is the negotiation that established asynchronous, ST synchronous, or DT synchronous/crc transfer protocols; whether the information unit protocol is used or not; whether Domain Validation is to be attempted; and the resource requirements for Domain Validation. The Domain Validation proposal is T10/ Various tables have to be altered rather than produce them, I listed instructions on changing them for the editor (since any change I make he has to redo in FRAMEMAKER anyway). The only exception is in the timing tables, since there is a lot of information in them. I have identified high priority issues for us to focus on by [??????]. These issues have been identified through discussions with a variety of people, and signify important areas where I do not believe there is a consensus. This proposal marches sequentially through the SPI document. The technical meat of this proposal in sections 8 (on CRC) and 27 (double-edge clocking data transfers). I suggest that people focus primarily on these areas in their review. Page 4 of 31 Increase Transfer Rate and Improve Error Detection Proposal

5 I am looking into a couple of issues people raised privately to me recently, and will make whatever (minor) updates are needed for the meeting of March 22. Hardcopy markups for information purposes will be available at the working group meeting. I strongly suggest that people have available some form of SPI-2 and the packetized SCSI proposal, or the SPI-3 draft, since I have made little attempt to duplicate the text surrounding the proposed modifications. 1 Introduction This document describes a proposal for the SCSI parallel interface to: 1) define double transition clocking to reduce the frequency of the REQx/ACKx signals at a given transfer rate and to increase the maximum data rate to 80 megatransfers per second; and, 2) Improve error detection through the use of CRC. The methods defined in this proposal allow initiators and targets to be backward compatible with fast-40, fast-20, fast-10 and fast-5 initiators and targets. This proposal requires no change in maximum cable lengths or number of devices from fast-20. In addition, there are no changes required for connectors, cables or terminators. This proposal references clauses in SCSI Parallel Interface 3 (SPI-3) rev 0. Where text should be modified I have tried to produce the original text and the new text with strikeouts and underscores to reflect the modifications. Changes in tables are much harder, and there I have been reduced to specifying the changes in English. [For discussion purposes I have included comments in several sections. These comments are in brackets and can be deleted from the final proposal document.] Special thanks to Mark Evans for his diligent review and tireless editing of this document. Without his outstanding help this document would barely have been possible, and certainly not in as good shape. 2 T10/98-153r1 comments Elimination of HVD from SPI-3: I support this, but desire committee input before assuming we can eliminate it in our documentation. Page 2 (clause 9) change looks OK. Page 3 (clause 9.1) the Fast-80:DT timings are documented in this proposal in section 27, and there are some differences. A discussion based on the model for the timings would be helpful in clarifying some of the differences. Page 11 - In addition, I have provided timings for Fast-10:DT Fast-20:DT, and Fast-40:DT, which hopefully will prove to be less controversial than Fast-80:DT timings for obvious reasons. I believe that Board skew can be significantly reduced for most devices (such as disk drives) if some way can be found to allow a few devices on the bus (e.g. motherboard mounted SCSI chips) a looser specification due to their greater board layout challenges. One technique would be to allow these devices to have twice as much skew, under the assumption that they are also supplying termination (which limits the number of such devices to 2). Another is to create two classes of devices Class 1 devices are help to the tighter specification, Class 2 to a looser one, and then restrict the number of Class 2 devices in configurations (afterall, there are not many systems with 16 hosts with motherboard Increase Transfer Rate and Improve Error Detection Proposal Page 5 of 31

6 T10/98-177r54 mounted SCSI chips). Note that Domain Validation can assist in insuring that very badly configured systems are detected and appropriate transfers rates used. Page 19 for the LVD capacitance loads, we support the 15 pf. This is an area where we agree, and can even suggest a lower value for difference between C1 and C2 (1 pf rather than 1.5 pf). Even more than board skew, reductions in this area should help overall margin. Once again, while I believe that the capacitance can be significantly reduced for most devices (such as disk drives) if some way can be found to allow a few devices on the bus (e.g. motherboard mounted SCSI chips) a looser specification due to their greater board layout challenges. The same techniques discussed for board skew could be applied in this instance. As far as I can see, all other portions of the proposal are identical with SPI-3, and so don t present any problems with this proposal. 3 Definitions The following definitions should be added in clause 3.1 of SPI-3 (or SPI-2). 3.1 Cyclic Redundancy Check (CRC): An error detecting code used to detect the validity of data that has been transferred during the current data phase. 3.2 double transition clocking (DT): The method for transferring data into a register or latch on both polarity edges of the clock signal. Double-edged clocking is used in the DT data phases to perform data transfers on both edges of the REQ or ACK. 3.3 fast-10:dt: Negotiated to receive synchronous data at a transfer rate less than or equal to a transfer rate of 10 megatransfers per second using double transition clocking. 3.4 fast-20:dt: Negotiated to receive synchronous data at a transfer rate greater than 10 megatransfers per second and less than or equal to 20 megatransfers per second using double transition clocking. 3.5 fast-40:dt: Negotiated to receive synchronous data at a transfer rate greater than 20 megatransfers per second and less than or equal to 40 megatransfers per second using double transition clocking. 3.6 fast-80:dt: Negotiated to receive synchronous data at a transfer rate greater than 40 megatransfers per second and less than or equal to 80 megatransfers per second using double transition clocking. 3.7 Data Group: The complete sequence of data bytes, any pad bytes, and the four CRC bytes during a DT phase. 3.8 Intersymbol interference (ISI): The effect of adjacent symbols on the symbol currently being received. 3.9 Protection: Signal used to transfer parity information or control the transfer of CRC information. Both allow error detection for signals on the DATA BUS, and so provide protection for those signals Single-edged clocking (ST): The method for transferring data into a register or latch on one polarity edge of the clock signal. Single-edged clocking is used in the ST data phases to perform data transfers when REQ or ACK transition from negated to asserted. The following definitions should be modified in clause 3.1 of SPI-3. Page 6 of 31 Increase Transfer Rate and Improve Error Detection Proposal

7 3.11 Make the following modification: odd parity: Odd logical parity, where the parity bit is driven and verified to be that value that makes the number of assertions on the associated DATA BUS plus the parity bit equal to an odd number (1, 3, 5, 7,or 9). See xxx, parity bit Make the following modification : parity bit: A bit associated with a transfer on the DATA BUS that is used to detect the presence of single-bit errors within the transfer. The parity bit is driven such that the number of logical ones in the transfer plus the parity bit is odd. 4 Abbreviations The following abbreviations should be added in clause 3.2 of SPI-2. CRC DT ISI MTps ST Cyclic Redundancy Check double transition clocked Intersymbol Interference Megatransfers per second single transition clocked 5 Clause Data Transfer Modes This clause should be modified as follows: SCSI parallel interface devices default to 8-bit transfer. The 8-bit information transfer mode is always used for all information transfers except the DATA phases. DATA phases may use the 8-bit, 16-bit or 32-bit wide, if a wide transfer agreement is in effect. SCSI parallel interface devices default to asynchronous transfer. The asynchronous information transfer mode is always used for all information transfers except the DATA phases. ST DATA phases may use either asynchronous or synchronous, if a synchronous transfer agreement is in effect. DT DATA phases shall use synchronous and a synchronous transfer agreement shall be effect if that phase is used. 6 Clause Cables, Connectors, Signals, Transceivers [This modification introduces the concepts of the fast-80 transfer rate and DT (double-edge clocked) LVD transfers. It restricts fast-80 to DT LVD and notes that fast-10:dt, fast-20:dt, and fast-40:dt are also allowed (note that asynchronous DT is not allowed).] Modify Table 1 (Transceiver/speed support map) in the following manner: 1) Insert a row between LVD and HVD labeled DT LVD 2) In this row make the respective values (from left to right) No, No, Yes, Yes, and Yes 3) Then insert a column after Fast-40 labeled Fast-80 4) In this column make the respective values (from top to bottom) No, No, No, Yes, No Increase Transfer Rate and Improve Error Detection Proposal Page 7 of 31

8 T10/98-177r54 7 Clause 8.1 Signal Descriptions [The following two modifications simply note that the MSG signal is used to distinguish the DT data phases as well as the MESSAGE phase. The signal will still be known as the MSG signal.] Eliminate the Control and Message line sections and put in a note to refer to the information phase definition in table xxx in SPI-3. [The following modifications change parity to protection and remove the definition of parity for the DB(P, P1, P2, P3) signals (they are defined later).] 1) DB(7-0,P) (8-bit DATA BUS). Eight data-bit signals, plus a protection signal that forms the 8-bit DATA BUS. Bit significance and priority during arbitration are shown in table 39. 2) DB(15-0,P,P1) (16-bit DATA BUS). Sixteen data-bit signals, plus two protection signals that form the 16-bit DATA BUS. Bit significance and priority during arbitration are shown in table 39. 3) DB(31-0,P,P1,P2,P3) (32-bit DATA BUS). Thirty-two data-bit signals, plus four protection signals that form the 32-bit DATA BUS. Bit significance and priority during arbitration are shown in table Clause 8.2 Parity checking rules [This is a major modification to the document. The parity nomenclature is replaced by the protection nomenclature -- this ripples throughout the document. This clause should specify two types of protection: parity and CRC. It should both define them and indicate how and when they are used.] Valid parity is determined by rules in table 40. Should be replaced by the following clauses [there are no change indications in the following as this is essentially an entire new 8.2 clause]: 8.2 Data Bus Protection The data bus protection signals are used to generate parity or control the transfer of CRC information Parity For an 8-bit data bus: DB(P) shall contain odd parity for DB(7-0) when in the SELECTION, RESELECTION, COMMAND, STATUS, MESSAGE IN, MESSAGE OUT, ST DATA IN, or ST DATA OUT phases. [[A3]][[A4]]DB(P) shall be used as the CRC_Available signal in DT DATA IN and DT DATA OUT phases.[[a3]][[a4]] For a 16-bit data bus: DB(P,P1) shall contain odd parity for DB(7-0) and DB(15-8), respectively, when in the SELECTION, RESELECTION, COMMAND, STATUS, MESSAGE IN, MESSAGE OUT, ST DATA IN, or ST DATA OUT phases. In the DT DATA IN and DT DATA OUT phases DB(P) shall be used as the CRC_Available signal [[C1]] and DB(P1) shall contain odd parity for DB(15-0).[[C1]][[C2]]. In the DT DATA IN phase the initiator shall not drive P1, and the target shall either release it or drive it no faster than the negotiated data transfer rate. In the DT DATA OUT phase the target shall not drive P1, and the initiator may either release it or drive it no faster than the negotiated data transfer rate. In either case the initiator shall ignore the value of this signal[[c2]] Page 8 of 31 Increase Transfer Rate and Improve Error Detection Proposal

9 For a 32-bit data bus: DB(P,P1,P2,P3) shall contain odd parity for DB(7-0), DB(15-8), DB(23-16), and DB(31-24), respectively, when in the SELECTION, RESELECTION, COMMAND, STATUS, MESSAGE IN, MESSAGE OUT, ST DATA IN, or ST DATA OUT phases. In the DT DATA IN and DT DATA OUT phases DB(P,P2) shall be used as CRC_Available signals[[c2]] and DB(P1,P3) shall contain odd parity for DB(15-0) and DB(31-16) respectively.[[c1]][[c2]]. In the DT DATA IN phase the initiator shall not drive DB(P1,P3), and the target shall either release them or drive them no faster than the negotiated data transfer rate. In the DT DATA OUT phase the target shall not drive DB(P1,P3), and the initiator may either release them or drive them no faster than the negotiated data transfer rate. In either case the initiator shall ignore the value of this signal. [[C2]] Parity Checking Rules Valid parity is determined by rules in table 40. [Insert table 40 here] CRC The primary bus and secondary bus generate, transfer, and check CRC independently. This section describes the operation for the primary bus, which is [[A3]][[A4]]either 8-bit or [[A3]][[A4]]16 bits wide. The operation for the secondary bus is identical except that the secondary bus signals are used instead of the primary bus signals (DB(P2) for DB(P), DB(P3) for DB(P1), DB(31-16) for DB(15-0), REQQ for REQ, ACKQ for ACK)[[A3]][[A4]], and the secondary bus is always 16 bits wide.[[a3]][[a4]] Error Detection Capabilities The error detecting code is a 32 bit Cyclic Redundancy Check (CRC), referred to as CRC-32. It is also used by Fibre Channel, FDDI, and Ethernet. Four CRC bytes are transferred with data to increase the reliability of data transfers. The CRC can detect all single bit errors, all double bit errors, all odd numbers of errors, and all burst errors up to 32 bits long Application CRC is used in the DT DATA IN and DT DATA OUT phases only. CRC protects a group of information transferred during these phases. Each phase consists of a transfer of one or more of these data groups. A data group consists of a data field, followed by a pad field, and then followed by a CRC field. The initiator or target transmitting data sends the pad and CRC fields at a point in time determined by the target. The target shall not change phases except at data group boundaries. Any phase change within a data group indicated either an error in logic or a data transmission error that can be alleviated in no other manner. In either event, all of the data transferred for that data group shall be considered to have been transferred incorrectly, and appropriate error reporting/recovery actions taken. [Note: in the case of logic errors (changing phases out of the blue ) the error is usually a fatal hardware error. Of more interest are errors due to data transmission errors that generate REQ/ACK offset mismatches or an incorrect number of pad/crc bytes (due to a problem with CRC_Available). Increase Transfer Rate and Improve Error Detection Proposal Page 9 of 31

10 T10/98-177r54 In the former case there the SCSI bus would hang today (since the REQ/ACK offset would never get to zero), forcing a BUS RESET to clear the condition. While it may be possible to improve on this for both ST and DT data phases, this problem is not unique to DT data phase and so is not solved as part of this proposal. In the latter case the detection/recovery is straightforward if the rules on pad/crc bytes are not followed, then an error is declared. Note that hardware can, for the sake of efficiency, assume that the rules are always followed (this simplifies the pipelining of data into the CRC generator/checker) and note the failure to follow the rules in parallel. As long as error is detected in real time, so that the device would act in the same manner as if the CRC checker detected an error, then the implementation is acceptable.] DATA Group Format A data group consists of a data field followed by a pad field and a CRC field. A group shall always have an even number of transfers, and shall be a multiple of four bytes (32 bits). REQ and ACK are negated both before and after the transmission of a data group. This is the result of a group always being an even number of transfers. The combined data and pad fields shall always have an even number of transfers (since the CRC field always consists of an even ([[A3]][[A4]]two four for an 8-bit bus, or [[A3]][[A4]]four two for a 16 bit bus) number of transfers). The combined data and pad fields shall also always be a multiple of four bytes (since the CRC field always consists of a multiple (of one) of four bytes). The pad field shall consist of 0 [[A3]][[A4]]to 3 [[A3]][[A4]][[A1]][[A2]]or 2 [[A1]][[A2]]bytes as follows: [[A3]][[A4]]8-bit bus: 0 bytes if the data field is a multiple of four bytes in length 1 byte if the data field is a multiple of four bytes plus three extra bytes in length 2 bytes if the data field is a multiple of four bytes plus two extra bytes in length 3 bytes if the data field is a multiple of four bytes plus one extra byte in length[[a3]][[a4]] 16-bit bus: 0 bytes if the data field is a multiple of four bytes in length 2 bytes if the data field is a multiple of four bytes plus two extra bytes in length [If there are 0 pad bytes, then no pad bytes are sent, pad bytes may be non-zero] If there are no 0 pad bytes, then no pad bytes are sent. If there are [[A3]][[A4]]1, 2, or 3[[A3]][[A4]][[A1]][[A2]]2[[A1]][[A2]] pad bytes, then that number of pad bytes are sent. [[D2]]Pad bytes may be of any value.[[d2]] [[D1]]Pad bytes shall have the value of zero. The receiving device is not required to check the value of the pad bytes.[[d1]] The data field shall consist of any number of transfers (including zero), as determined by the target. Data Field Pad Field CRC Field Associated with REQ sent with CRC_Available Negated Associated with REQ sent with CRC_Available Asserted 0 to N bytes 0 to 3 bytes 4 bytes Even R/A Transitions Four Byte Multiple Even R/A Transitions Four Byte Multiple Page 10 of 31 Increase Transfer Rate and Improve Error Detection Proposal

11 Figure xxx: Fields within a Data Group Only one set of REQxs associated with CRC_Available for the pad field and the CRC field of a single data group shall be outstanding at any time. [Note that these rules allow for a straightforward implementation of CRC. Since the data and pad field bytes are checked by the CRC, all of the data is put into the CRC checker as usual. Since all calculations are done using 32 bit (4 byte) data word, these words are sent to the CRC checker and are considered as a unit. For any word, if the first byte received by the device is associated with an asserted state of CRC_Available, then the entire word must be the CRC field (since pads of 4 bytes are illegal). For sending user data onto the device, the rule is simplier yet: after CRC checking, the bytes not associated with the asserted state of CRC_Available are the data field the others are pad/crc field bytes. Note that one implementation is to record the value of CRC-available associated with each 8 or 16 bit piece of data transferred on the bus until these determinations are made (similar to storing the parity bit for each word today). Other implementations are possible and legal as long as the observable behaviourbehavior is as documented in the standard.] CRC_Available Signal The CRC_Available signal is asserted by the target to indicate a REQ associated with byte(s) in a pad or CRC field of a data group.. The CRC_Available signal is negated to indicate a REQ associated with byte(s) in a data field of a data group. CRC_Available is transmitted on DB(P) for [[A3]][[A4]]an 8-bit or [[A3]][[A4]]16-bit DATA BUS; DB(P) and DB(P2) for a 32-bit DATA BUS Order of Bytes in the CRC Field [[A1]][[A2]] [Note to the editor: that the following tables will be modififed to remove 8 bit.][[a1]][[a2]] The data is transmitted, used to calculate the CRC, and the CRC is transmitted in the following manner: CRC GENERATION DATA TRANSMISSION TIME Value Value Value Value 1 NARROW Value 1 Value 0 Value 3 Value 2 WIDE BUS Increase Transfer Rate and Improve Error Detection Proposal Page 11 of 31

12 T10/98-177r54 CALCULATION 31 0 Value 0 Value 1 Value 2 Value Value 0 Value 1 Value 2 Value CRC GENERATOR Invert bits 31 0 CRC 0 CRC 1 CRC 2 CRC CRC 0 CRC 1 CRC 2 CRC TIME CRC 0 CRC 1 CRC 2 CRC 3 2 NARROW CRC 1 CRC 0 CRC 3 CRC 2 WIDE BUS Page 12 of 31 Increase Transfer Rate and Improve Error Detection Proposal

13 CRC Generation and Checking The 32 bit generator polynomial used is: x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 This equals 0x104C11DB7 in hexadecimal. The remainder is generated by dividing the bytes in the data and pad fields (which are a multiple of four bytes) by the generator polynomial, modulo two. The remainder is generated 32 bits at a time. The remainder is initialized to all ones (0xFFFFFFFF). This is the seed value. It is reloaded at the beginning of each DT DATA phase and after each CRC is generated/checked. Bytes are bit reversed prior to generating the remainder and the bytes of the remainder are bit reversed prior to forming the CRC field. The CRC Field is the ones complement of the bit reversed remainder. A unique remainder is generated by an error free group. The unique remainder polynomial of an error free group is: x 31 + x 30 + x 26 + x 25 + x 24 + x 18 + x 15 + x 14 + x 12 + x 11 + x 10 + x 8 + x 6 + x 5 + x 4 + x 3 + x + 1 This equals 0xC704DD7B in hexadecimal Test Cases For a 32 byte transfer of all 0's, the CRC transferred across the SCSI bus: Narrow: Wide: 0xad, 0x55, 0x0a, 0x19 0x55ad, 0x190a For a 32 byte transfer of all 1's: Narrow: Wide: 0x0b, 0xab, 0x6c, 0xff 0xab0b, 0xff6c For a 32 byte transfer of an incrementing patter from 0x00 to 0x1F: (Note that the last test case used to be 0x01 to 0x20, I didn't have any reason for changing it, I just didn't check before running the simulation) Narrow: Wide: 0x8a, 0x7e, 0x26, 0x91 0x7e8a, 0x Clause 8.4 OR-Tied Signals Modify the third sentence in the second paragraph as follows: Protection bits shall not be driven false during the ARBITRATION phase but may be driven false in other phases. Increase Transfer Rate and Improve Error Detection Proposal Page 13 of 31

14 T10/98-177r54 10 Clause 8.5 Signal Sources [The packetized SCSI proposal (T10/97-230r6) added two rows to table 41 (Signal Sources).] 1) In the first column: replace INFORMATION UNIT IN with DT DATA IN, and INFORMATION UNIT OUT with DT DATA OUT. 2) Split column 6 (headed by DB7-0, DB(P) ) into two columns (headed by DB7-0 and DB(P) respectively). The contents of the two columns shall be the same as the original column, except for the row marked DT DATA OUT. In that row, the value in the DB(P) column shall be Targ, not Init. 3) Split column 10 (headed by DB31-16, DB(P2), DB(P3) ) into two columns (headed by DB31-16, DB(P3) and DB(P2) respectively). The contents of the two columns shall be the same as the original column, except for the row marked DT DATA OUT. In that row the value in the DB(P2) column shall be Targ, not Init. 4) In the footnotes for Table 41, modify the following: S ID: A unique data bit (the SCSI ID) shall be driven by each SCSI device that is actively arbitrating; the other data bits shall be released (i.e., not driven) by this SCSI device. The protection bit(s) may be released or driven to the true state, but shall not be driven to the false state during this phase. [Note: the SPI editor may make whatever formatting changes in Table 41 that make the text more usable without loss of the content specified above.] 11 Clause 9 SCSI parallel bus timing [This modification provides the timing tables for Fast-10:DT, Fast-20:DT, Fast-40:DT, and Fast-80:DT. The actual times are TBD, and will be filled in by the Fast-80:DT proposal.] 1) Table 42 (SCSI Bus Timing Values) needs to add columns for Fast-10:DT, Fast-20:DT, Fast-40:DT, and Fast-80:DT. 2) The timing values for these new entries are TBD, and will be supplied in the Fast-80:DT proposal. 3) A footnote should be added to remind people that the CRC_Available signal must obey the same constraints as any other signal on the data bus (since it is mapped to DB(P) and BD(P2)). [Note: the SPI editor may make whatever formatting changes in Table 42 that make the text more usable without loss of the content specified above.] 12 Clause 9.2 Measurement Points Modify as follows: The measurements points for ST and differential ACK, REQ, DATA, and PROTECTION signals are defined in this clause. 13 Clause ST fast-10 data transfer rates Modify the second sentence in the first paragraph as follows: The rise and fall times for the ST REQ/ACK signals shall be nominally the same as for the ST DATA/PROTECTION signals. 14 Clause ST fast-20 data transfer rates Page 14 of 31 Increase Transfer Rate and Improve Error Detection Proposal

15 Modify the second sentence in the first paragraph as follows: The rise and fall times for the ST REQ/ACK signals shall be nominally the same as for the ST DATA/PROTECTION signals. 15 Clause LVD 1) Modify the second sentence in the first paragraph as follows: The rise and fall times for the LVD REQ/ACK signals shall be nominally the same as for the LVD DATA/ PROTECTION signals. 2) In Figure LVD timing measurement points, replace PARITY with PROTECTION 16 Clause Section HVD [Until the committee officially removes HVD from SPI-3, I felt it prudent to continue to include it in the modifications.] 1) Modify the second sentence in the first paragraph as follows: The rise and fall times for the HVD REQ/ACK signals shall be nominally the same as for the HVD DATA/ PROTECTION signals. 2) In Figure HVD timing measurement points, replace PARITY with PROTECTION 17 Clause Fast-10 data transfer rates 1) Modify the second paragraph as follows: The receiver skew is the maximum difference in propagation time between any two receivers on the REQ, REQQ, ACK, ACKQ, DATA BUS or protection signals of the same SCSI bus when external receivers are used. 2) Modify the third paragraph as follows: The transmitter skew is the maximum difference in propagation time between any two transmitters on the REQ, REQQ, ACK, ACKQ, DATA BUS or protection signals of the same SCSI bus when external transmitters are used. 18 Clause Fast-20 data transfer rates 1) Modify the third paragraph as follows: The receiver skew is the maximum difference in propagation time between any two receivers on the REQ, REQQ, ACK, ACKQ, DATA BUS or protection signals of the same SCSI bus when external receivers are used. 2) Modify the fourth paragraph as follows: The transmitter skew is the maximum difference in propagation time between any two transmitters on the REQ, REQQ, ACK, ACKQ, DATA BUS or protection signals of the same SCSI bus when external transmitters are used. 19 Clause DT data transfer rates [This modification provides the system level timing budget for Fast-10:DT, Fast-20:DT, Fast-40:DT, and Fast-80:DT. The actual times for Fast-80:DT are actually TBD, and are subject to change by the Fast- 80:DT proposal.] [This new section should be added to compliment the previous sections. I suggest using the same format as section 9.3.3, but limited to only Integrated Transmitters and Receivers, and, for completeness, specifying the budget for the various defined DT speeds (Fast-10:DT, Fast-20:DT, Fast- 40:DT, and Fast-80:DT. The actual times for Fast-80:DT are actually TBD, and are subject to change by the Fast-80:DT proposal.] Increase Transfer Rate and Improve Error Detection Proposal Page 15 of 31

16 T10/98-177r54 20 Clause 11.1 SCSI Bus Phases [These modifications are to SPI-3, which is identical in wording to that in the packetized SCSI proposal, T10/97-230r6.] 20.1 Delete: g) INFORMATION UNIT phase 20.2 Modify the second paragraph as follows: The COMMAND phase, DATA phase,, STATUS phase, and MESSAGE phase are collectively termed the information transfer phases. 21 Clause ARBITRATION phase Modify the last paragraph as follows: Protection is not valid during the ARBITRATION phase. During the ARBITRATION phase, DB(P), DB(P1) (if present), DB(P2) (if present), and DB(P3) (if present), may be released or asserted, but shall not be actively driven false. 22 Clause SELECTION phase [This modification is extensive since the packetized SCSI proposal, T10/97-230r6 restructured this clause in SPI-2. This wording is a modification of the wording for the section in SPI-3, which is identical to that in the packetized SCSI proposal. The intent is to make the information unit phases into references to information unit protocol.] [Note that parity during SELECTION was deleted in the packetized SCSI proposal, but will be reinstated. The text below is still the original text from the packetized SCSI and SPI-3 rev (the SPI-3 editor has agreed to fix the wording in the next revision of SPI-3).] The following are modifications that should be made to SPI-3 (or the corresponding sections documented in T10/97-230r6): Selection with ATN The initiator shall set the DATA BUS to a value that is the OR of its SCSI ID bit and the target's SCSI ID bit and assert the ATN signal (indicating that a MESSAGE OUT phase is to follow the SELECTION phase). The initiator shall then wait at least two system deskew delays and release the BSY signal. The initiator shall then wait at least a bus settle delay before looking for an assertion of the BSY signal from the target. If the information protocol is disabled for the connecting initiator the target shall follow the phase sequences defined in clause If the information protocol is enabled for the connecting initiator the target shall indicate a protocol error by performing an unexpected bus free Selection without ATN The initiator shall set the DATA BUS to a value that is the combination of its SCSI ID bit and the target's SCSI ID bit and negate the ATN signal (indicating that a DT DATA OUT phase is to Page 16 of 31 Increase Transfer Rate and Improve Error Detection Proposal

17 follow the SELECTION phase). The initiator shall then wait at least two deskew delays and release the BSY signal. The initiator shall then wait at least a bus settle delay before looking for an assertion of the BSY signal from the target. If the information protocol is disabled for the connecting initiator the target shall follow the phase sequences defined in clause If the information protocol is enabled for the connecting initiator the target shall follow the phase sequences defined in clause If an initiator, when selecting without ATN, detects an unexpected COMMAND phase it should invalidate any prior IUTR with the selected target. In this case, the initiator shall assert the ATN signal and on the corresponding MESSAGE OUT phase shall issue an ABORT TASK message. On the next selection with the invalidated target the initiator should do a selection with ATN and negotiate to enable the information protocol. 23 Clause RESELECTION 23.1 Modify the third sentence of the first paragraph as follows: The winning SCSI device shall also set the DATA BUS to a value that is the logical OR of its SCSI ID bit and the initiator's SCSI ID bit and the appropriate protection bit Modify the fourth sentence of the second paragraph as follows: The initiator shall not respond to a RESELECTION phase if there is a data protection error (see 8.2). 24 Clause Information transfer phases Modify the first paragraph as follows: [new sentence was added since it is the current SPI-3 wording] Information transfer phases The COMMAND, DATA, STATUS, and MESSAGE phases are all grouped together as the information transfer phases because they are all used to transfer data or control information via the DATA BUS. The actual content of the information is beyond the scope of this section. [The following was added to complement the changes made in section 24, clause please see that section for details.] Insert this paragraph at the end of the section: The target shall not transition into an information transfer phase unless the REQx/ACKx signals are in their deasserted state. The target shall not transition from an information transfer phase into another information transfer phase unless the REQx/ACKx signals are in their deasserted state. 25 Clause Information transfer phases Increase Transfer Rate and Improve Error Detection Proposal Page 17 of 31

18 T10/98-177r54 [This wording is a modification of the wording for the section in SPI-3, which is identical to that in the packetized SCSI proposal. The intent is to remove the INFORMATION UNIT phases and replace them with the DT DATA phases.] 1) In Table 43 (Information Transfer Phases), in the 1 st and 2nd row replace the phrase Data phase in the Comment column with the phrase Single-edge clocked Data phase. 2) In Table 43 (Information Transfer Phases), in the 5 th row (with the first three entries 1, 0, 0), replace the phrase INFORMATION UNIT OUT in the Phase column with the phrase DT DATA OUT. 3) In Table 43 (Information Transfer Phases), in the 6 th row (with the first three entries 1, 0, 1), replace the phrase INFORMATION UNIT IN in the Phase column with the phrase DT DATA IN. 4) In Table 43 (Information Transfer Phases), in the 5 th and 6 th row replace the phrase Information unit phase in the Comment column with the phrase Double-edge clocked Data phase. 26 Clause Information transfer phases [This modification is extensive since the packetized SCSI proposal, T10/97-230r6 restructured this clause in SPI-2. This wording is a modification of the wording for the section in SPI-3, which is identical to that in the packetized SCSI proposal. The intent is to make the information unit phases into references to information unit protocol.] The following are modifications that should be made to the document T10/97-230r6 (all references are to the clause numbers in that document): Information unit protocol The information unit protocol is optional and is only used in DT DATA IN and DT DATA OUT phases. It shall be used in a data phase if an information unit has been established (see xxx) INFORMATION UNIT IN protocol exception condition handling The initiator shall not assert the ACK for the last byte of the CRC of any information unit until the CRC has been verified to be correct. If the initiator detects a parity error on any byte or a CRC error in any information unit it receives, the initiator shall create an attention condition by asserting the ATN signal before the ACK signal is released for the last byte of CRC. When the target switches to a MESSAGE OUT phase the initiator shall send an INITIATOR DETECTED ERROR message (see xxx) to the target. This message notifies the target that data in that information unit was invalid. If the target does not retry transmitting that information unit, or it exhausts its retry limit, it shall send a SPI L_Q/Status information unit pair to the initiator with a CHECK CONDITION status and a sense key set to ABORTED COMMAND and an additional sense code set to INITIATOR DETECTED ERROR MESSAGE RECEIVED for the task associated with the received INITIATOR DETECTED ERROR message. (48/00) INFORMATION UNIT OUT protocol exception condition handling The target shall only respond to a parity error or CRC error after all the data in an information unit has been received. If the nexus has been fully identified (i.e., an I_T_L_Q nexus has been established) and the target detects a parity error on any byte or a CRC error in any information Page 18 of 31 Increase Transfer Rate and Improve Error Detection Proposal

19 unit it receives, and the target does not retry transmitting that information unit, or it exhausts its retry limit, the target shall send a SPI L_Q/SPI status information unit pair to the initiator with a CHECK CONDITION status and a sense key set to ABORTED COMMAND and the additional sense code set to SCSI PARITY ERROR for the task associated with the parity error or CRC error. (47/00) If the target is receiving a SPI L_Q information unit and the target detects a parity error (i.e., the nexus identification fails) on any byte or a CRC error the target shall cause an unexpected bus free by generating a BUS FREE phase (see xxx). 27 Clause Synchronous data transfer Replace clause Synchronous data transfer with the following clause with four sub-clauses. The first subclause defines single transition clocked synchronous data transfer; the second defines doubleedge clocked synchronous data transfer; the third defines transfer of CRC; and, the fourth defines timings: [changes are noted in , since it is a rewrite of the existing , but the latter sections are all new and so have no changes explicitly noted.] Synchronous data transfer Single-edge [transition] clocked synchronous data transfer [The following modification is to define single transition clocked synchronous data transfer. What was clause has been demoted and slightly modified for single transition clocked. The changes from the original clause are underlined. The SPI-3 editor may find an easier way to combine this section with the latter double-edge clocked section, but for the moment this seemed the approach that would insure the greatest degree of clarity.] Single-edge clocked synchronous data transfer is optional and is only used in the ST DATA IN and ST DATA OUT data phases. It shall be used in a data phase if a single transition clocked synchronous data transfer agreement has been established (see xxx ). The agreement specifies the REQx/ACKx offset and the minimum transfer period. The REQx/ACKx offset specifies the maximum number of REQx assertions that shall be sent by the target in advance of the number of ACKx assertions received from the initiator, establishing a pacing mechanism. If the number of REQx assertions exceeds the number of ACKx assertions by the REQx/ACKx offset, the target shall not assert the REQx signal until after the next ACKx assertion is received. For successful completion of the data phase is that the number of ACKx and REQx assertions shall be equal. The target shall assert the REQx signal for a minimum of an assertion period. The target shall then wait at least the greater of a transfer period from the last transition of the REQx signal to true or a minimum of negation period from the last transition of the REQx signal to false before again asserting the REQx signal. The initiator shall assert the ACKx signal for each REQx assertion received. The ACKx signal may be asserted as soon as the corresponding REQx assertion has been received. The initiator shall assert the ACKx signal for a minimum of an assertion period. The initiator shall wait at least the greater of a transfer period from the last transition of the ACKx signal to true or for a minimum of a negation period from the last transition of the ACKx signal to false before asserting the ACKx signal. [Although I left them in, the following two paragraphs are subject to the same concern as the similar sections in the DT section. reword for setup and hold time] Increase Transfer Rate and Improve Error Detection Proposal Page 19 of 31