Administrivia. Caches III. Making memory accesses fast! Associativity. Cache Organization (3) Example Placement

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1 s III CSE Autumn Instructor: Justin Hsia Teaching Assistants: Lucas Wotton Michael Zhang Parker DeWilde Ryan Wong Sam ehman Sam Wolfson Savanna Yee Vinny Palaniappan Administrivia Midterm regrade requests due end of tonight Lab due riday HW is released, due next riday (/) No lecture on riday Veteran s Day! Making memory accesses fast! basics Principle of locality hierarchies organization Direct mapped (sets; index + tag) (ways) Replacement policy Handling writes Program optimizations that consider caches What if we could store data in any place in the cache? More complicated hardware = more power consumed, slower So we combine the two ideas: Each address maps to exactly one set Each set can store block in more than one way -way: 8 sets, block each direct mapped -way: sets, blocks each -way: sets, blocks each 8-way: set, 8 blocks fully associative Organization () (): # of ways for each set Such a cache is called an way set associative cache We now index into cache sets, of which there are // Use lowest log // = bits of block address Direct mapped: =, so = log / as we saw previously ully associative: = /, so = bits Used for tag comparison Decreasing associativity Direct mapped (only one way) Selects the set Increasing associativity Note: The textbook uses b for offset bits Selects the byte from block Tag () Index () Offset () ully associative (only one set) Example Placement Where would data from address x8 be placed? Binary: b bit address: =? Direct mapped = Tag () = log // Index () block size: B capacity: 8 blocks address: bits = log Offset () =? =? way set associative way set associative

2 Block Replacement Peer Instruction Question Any empty block in the correct set may be used to store block If there are no empty blocks, which one should we replace? No choice for direct mapped caches s typically use something close to least recently used (LRU) (hardware usually implements not most recently used ) Direct mapped way set associative way set associative We have a cache of size KiB with block size of 8 B. If our cache has sets, what is its associativity? Vote at A. B. C. 8 D. E. We re lost If addresses are bits wide, how wide is the Tag field? 8 eneral Organization (,, ) Notation Review = # sets = valid bit V = blocks/lines per set Tag K = bytes per block set line (block plus management bits) size: data bytes (doesn t include V or Tag) 9 We just introduced a lot of new variable names! Please be mindful of block size notation when you look at past exam questions or are watching videos Variable This Quarter ormulas Block size in book size Number of s Address space Address width Tag field width Index field width Offset field width in book log log log log // Read = # sets = = blocks/lines per set ) Locate set ) Check if any line in set is valid and has matching tag: hit ) Locate data starting at offset Address of byte in memory: bits bits bits tag set index block offset Example: Direct Mapped ( = ) Block Size = 8 B = sets bits find set data begins at this offset v tag K valid bit = bytes per block

3 Example: Direct Mapped ( = ) Example: Direct Mapped ( = ) Block Size = 8 B Block Size = 8 B valid? + match?: yes = hit bits valid? + match?: yes = hit bits int ( B) is here This is why we want alignment! No match? Then old line gets evicted and replaced Example: Associative ( = ) Example: Associative ( = ) way: Two lines per set Block Size = 8 B bits way: Two lines per set Block Size = 8 B compare both bits valid? + match: yes = hit find set v tag Example: Associative ( = ) Types of Misses: C s! way: Two lines per set Block Size = 8 B valid? + match: yes = hit compare both short int ( B) is here No match? One line in set is selected for eviction and replacement Replacement policies: random, least recently used (LRU), bits Compulsory (cold) miss Occurs on first access to a block Conflict miss Conflict misses occur when the cache is large enough, but multiple data objects all map to the same slot e.g. referencing blocks, 8,, 8,... could miss every time Direct mapped caches have more conflict misses than way set associative (where > ) Capacity miss Occurs when the set of active cache blocks (the working set) is larger than the cache (just won t fit, even if cache was fullyassociative) Note: ully associative only has Compulsory and Capacity misses 8

4 What about writes? Multiple copies of data exist: L, L, possibly L, main memory What to do on a write hit? Write through: write immediately to next level Write back: defer write to next level until line is evicted (replaced) Must track which cache lines have been modified ( ) What to do on a write miss? Write allocate: ( fetch on write ) load into cache, update line in cache ood if more writes or reads to the location follow No write allocate: ( write around ) just write immediately to memory Typical caches: Write back + Write allocate, usually Write through + No write allocate, occasionally 9 Contents of memory stored at address xbee xcae xbee tag (there is only one set in this tiny cache, so the tag is the entire block address!) In this example we are sort of ignoring s. Here a block holds bytes ( bits, hex digits). Normally a block would be much bigger and thus there would be multiple items per block. While only one item in that block would be written at a time, the entire line would be brought into cache. mov xace, mov xace, xbee U xcae xbee Step : Bring into cache xcae xcae xbee xbee mov xace, mov xace, mov xeed, U xace xcae xbee U xace xcae xbee xcae Step : Write xace to cache only and set xcae Write hit! Write xeed to cache only xbee xbee

5 mov xace, mov xeed, mov, %rax mov xace, mov xeed, mov, %rax U xeed xcae xbee xbee xcae xeed. Write back to memory since it is dirty. Bring into the cache so we can copy it into %rax xbee xbee Peer Instruction Question Example Parameters Problem Which of the following cache statements is ALSE? Vote at A. We can reduce compulsory misses by decreasing our block size B. We can reduce conflict misses by increasing associativity C. A write back cache will save time for code with good temporal locality on writes D. A write through cache will always match data with the memory hierarchy level below it E. We re lost MiB address space, cycles to go to memory. ill in the following table: Size KiB Block Size B way Hit Time cycles Miss Rate % Write Policy Write through Replacement Policy LRU Tag Bits Index Bits Offset Bits AMAT 8 Example Code Analysis Problem Assuming the cache starts cold (all blocks invalid), calculate the miss rate for the following loop: = bits, = KiB, = B, = #define AR_SIZE 8 int int_ar[ar_size], sum=; // &int_ar=x8 for (int i=; i<ar_size; i++) sum += int_ar[i]; for (int j=ar_size-; j>=; j--) sum += int_ar[i]; 9