HT48RAx/HT48CAx Software Application

Size: px

Start display at page:

Download "HT48RAx/HT48CAx Software Application"

Benedict Terry
6 years ago
Views:

1 HT48RAx/HT48CAx Software Application Note D/N: HA0076E Introduction CALL and JUMP will load the BP to program counter. Interrupt will store the contents of program counter into stack. RETI/RET will load the contents of stack into program counter. Jump Between Different Banks (a) To locate a code section to a bank (definition) Use ROMBANK directive: ROMBANK n codesec; n= 0~4 (b) Load the bank number of the destination address into BP Use BANK directive: BANK label (c) Jump to the destination address (d) Example ROMBANK 0 codesec0; definition ROMBANK 1 codesec1; definition ROMBANK 2 codesec2; definition codesec0.section at 000h code ; BANK 0 org 0000h clr bp jmp strt 1

2 strt: mov a,bank label1 ; label1 is located in BANK 1 ; load bank number of label1 to BP jmp label1 ; jump to label1 label0: ; label0 is located in BANK 0 codesec1.section at 000h code ; BANK 1 label1: mov a,bank label2 ; label2 is located in BANK 2 ; load bank number of label2 to BP jmp label2 ; jump to label2 codesec2.section at 000h code ; BANK 2 label2: mov a,bank label0 ; label0 is located in BANK 0 ; load bank number of label0 to BP jmp label0 ; jump to label0 end 2

3 Interrupt Service Routines (a) Accumulator backup (b) Move BP to accumulator (c) Clear BP (d) Jump a label located in bank 0 (e) BP backup (f) Other registers backup (g) Example include ht48ca3.inc ; use HT48CA3 MCU body accbuf0 db? statusbuf0 db? bpbuf0 db? accbuf1 db? statusbuf1 db? bpbuf1 db? accbuf2 db? statusbuf2 db? bpbuf2 db? ROMBANK 0 codesec0; definition ROMBANK 1 codesec1; definition ROMBANK 2 codesec2; definition codesec0.section at 000h code ; BANK 0 org 0004h mov accbuf0,a mov a,bp clr bp jmp labelbank00 ; labelbank00 should be located in BANK 0 org 0008h mov accbuf1,a mov a,bp clr bp 3

4 mov labelbank01 ; labelbank01 should be located in BANK 0 org 000ch mov accbuf2,a mov a,bp clr bp jmp labelbank02 ; labelbank02 should be located in BANK 0 labelbank00: ; located in BANK 0 mov bpbuf0,a ; backup BP mov a,status mov statusbuf0,a ; can call/jump to different banks labels ; BP should be managed mov a,statusbuf0 ; restore registers mov status,a mov a,bpbuf0 mov a,accbuf0 reti labelbank01: ; located in BANK 0 mov bpbuf1,a ; backup BP mov a,status mov statusbuf1,a ; can call/jump to different banks labels ; BP should be managed mov a,statusbuf1 ; restore registers mov status,a mov a,bpbuf1 mov a,accbuf1 reti 4

5 labelbank02: ; located in BANK 0 mov bpbuf2,a ; backup BP mov a,status mov statusbuf2,a ; can call/jump to different banks labels ; BP should be managed mov a,statusbuf2 ; restore registers mov status,a mov a,bpbuf2 mov a,accbuf2 reti codesec1.section at 000h code ; BANK 1 labelbank10: codesec2.section at 000h code ; BANK 2 labelbank20: end Call Between Different Banks Subroutines (a) To locate a code section to a bank (definition) Use ROMBANK directive: ROMBANK n codesec ; n= 0~4 (b) Backup BP (c) Load the bank number of the destination address into BP Use BANK directive: BANK label (d) Call the destination address 5

6 (e) Load current bank number to BP (f) (g) Nesting: from (b) to (j) (h) (i) RET (j) Restore BP (k) Example include ht48ca3.inc ; use HT48CA3 MCU body accbuf0 db? statusbuf0 db? bpbuf0 db? accbuf1 db? statusbuf1 db? bpbuf1 db? accbuf2 db? statusbuf2 db? bpbuf2 db? ROMBANK 0 codesec0; definition ROMBANK 1 codesec1; definition ROMBANK 2 codesec2; definition codesec0.section at 000h code ; BANK 0 org 0000h clr bp jmp strt strt: mov a,bp ; backup BP mov bpbuf0,a mov a,bank label1 ; label1 is located in BANK 1 6

7 ; load bank number of label1 to BP call label1 ; jump to label1 mov a,bpbuf0 ; restore BP label0: ; label0 is located in BANK 0 mov a,bank label0 ; new BP ret codesec1.section at 000h code ; BANK 1 label1: mov a,bank label1 ; new BP mov a,bp ; BP backup mov bpbuf1,a mov a,bank label2 ; label2 is located in BANK 2 ; load bank number of label2 to BP call label2 ; jump to label2 mov a,bpbuf1 ret codesec2.section at 000h code ; BANK 2 label2: mov a,bank label2 ; new BP 7

8 mov a,bp ; BP backup mov bpbuf2,a mov a,bank label0 ; label0 is located in BANK 0 ; load bank number of label0 to BP call label0 ; jump to label0 mov a,bpbuf2 ret end Generate PFD/Carrier Signal (Not Synchronized) and Remote Output (a) PB0 selects the PFD output (mask option). (b) Timer/event counter 0 is used to generate PFD/carrier signal (c) Disable timer/event counter 0. (d) Disable timer/event counter 0 overflow interrupt. (e) Load the preload value to TMR0, f PFD =f SYS /(2(n+1) (256-m)), n= prescaler stage (1~8), m= 0~255. (f) Enable timer/event counter 0 counting. (g) Clear PBC.0 to enable the PB.0 output function (h) Set PB.0 (PB.0 = 1) to enable the PFD output. (PB0 = carrier output) (i) Clear PB.0 (PB.0 = 0) to disable the PFD output. (PB0 = 0) (j) (k) Timer/event counter 1 is used to control the timing of bit streams and time interval between successive bit stream frame (l) It is suggested that all programs are located in bank 0 and data can be located in bank 0, 1 and 2. (BP backup/restore can be ignored) 8

9 Example 1: Pulse are Not Synchronized (All Programs are Located in Bank 0) f CARRIER =38kHz, f SYS =4MHz, preload value= /(2 38)=230 Timer/Event Counter 0 prescaler stage n=1, f PFD =38.46kHz Transmission sequence: MSB first lead frame: carrier=2.4ms Bit 1 : low=600 s, carrier=1200 s Bit 0 : low=600 s, carrier=600 s Bit stream frame=50ms Timer/Event Counter 1 overflow period=600 s 50ms/600 s 83 unit (per unit=600 s) 2.4ms/600 s=4 unit (per unit=600 s) include ht48ca3.inc accbuf2 db? statusbuf2 db? bitcount db? bitno db? frame db? leadframe db? bith1 db? byte1 db question byte0 db question txflag dbit org 0000h clr bp jmp strt org 0008h reti org 000ch mov accbuf2,a mov a,status mov statusbuf2,a jmp label2 strt: ; use HT48CA3 MCU body ; Tx data high byte ; Tx data low byte 9

10 ; scan key ; read table to and datah ; decode transmission format clr leadframe clr frame clr bith1 clr tmr0c mov a,17 mov bitno,a ; bit number=16 bits+1(leadframe) mov a,230 ; f PFD =38.46kHz=4000/(4 ( ))kHz mov tmr0,a mov a,098h mov tmr0c,a clr tmr1c mov a,168 ; Timer/Event Counter 1 overflow time unit mov tmr1l,a ; =65536-( ) s=600 s mov a,253 mov tmr1h,a mov a,098h mov tmr1c,a mov a,09h ; disable TMR0 interrupt mov intc,a ; enable TMR1 interrupt mov a,datal ; datal is read from ROM table (TABRDC) mov byte0,a mov a,datah ; datah is read from ROM table (TABRDC) mov byte1,a set txflag ; enable IR data transmission clr bitcount ; reset IR data bit-count label2: mov a,bitcount xor a,bitno sz status.2 clr txflag snz txflag jmp stoptx sz bitcount jmp txing 10

11 txstart: clr pbc.0 set pb.0 inc leadframe snz leadframe.2 jmp endtxbit inc bitcount clr leadframe jmp endtxbit txing: inc bith1 mov a,bithl xor a,01h snz status.2 jmp chk23 clr pbc.0 clr pb.0 jmp endtxbit chk23: mov a,bithl xor a,02h snz status.2 jmp chk3 clr pbc.0 set pb.0 sz byte1.7 jmp endtxbit inc bitcount chk230: rlc byte0 rlc byte1 clr bith1 jmp endtxbit chk3: clr pbc.0 set pb.0 jmp chk230 chk3: clr pbc.0 ; generate leadframe ; leadframe=2.4ms ; clear leadframe timer ; transmit bit data ; first: low pulse=600 s ; second: high pulse=600 s ; third for 0 : high pulse=none ; third for 1 : high pulse=600 s ; all bits are transmitted 11

12 clr pb.0 endtxbit: inc frame mov a,frame sub a,83 snz status.0 jmp endframe set txflag clr bitcount mov a,datal mov byte0,a mov a,datah mov byte1,a clr bith1 clr frame endframe: mov a,statusbuf2 mov status,a mov a,accbuf2 reti ; frame timer ; frame time-out re-send code ; reload data to related registers ; clear frame timer Example 2: Pulses are Synchronized (All Programs are Located in Bank 0) f CARRIER =38kHz, f SYS =4MHz, preload value= /(2 38)=230 Timer/Event Counter 0 prescaler stage n=1, f PFD =38.46kHz Transmission sequence: MSB first lead frame: carrier=2.4ms=88 pulses (counted by INT) bit 1 : low=600 s, carrier=44 pulses (counted by INT) bit 0 : low=600 s, carrier=22 pulses (counted by INT) bit stream frame=50ms Timer/Event Counter 1 overflow period=600 s 50ms/600 s 83 unit (per unit=600 s) 2.4ms/600 s=4 unit (per unit=600 s) 12

13 include ht48ca3.inc ; use HT48CA3 body accbuf1 db? statusbuf1 db? bitcount db? bitno db? frame db? leadframe db? bith1 db? byte1 db? ; data high byte byte0 db? ; data low byte intcntcom db? txflag dbit pulsetxing dbit enpulse dbit bittxing dbit ; bit is transmitting org 0000h clr bp jmp strt org 0004h ; PB0/PFD connected to PF0/INT sdz intcntcom reti clr pb.0 reti org 0008h reti org 000ch mov accbuf2,a mov a,status mov statusbuf2,a jmp label2 strt: ; scan key ; read table to data1 and datah ; decode transmission format 13

14 clr leadframe clr frame clr bith1 clr intcntcom clr tmr0c mov a,17 mov bitno,a mov a,230 mov tmr0,a mov a,088h mov tmr0c,a clr tmr1c mov a,168 mov tmr1l,a mov a,253 mov tmr1h,a mov a,098h mov tmr1c,a mov a,09h mov intc,a mov a,datal mov byte0,a mov a,datah mov byte1,a set txflag clr pulsetxing clr bitcount clr enpulse clr bittxing clr pbc.0 label2: mov a,bitcount xor a,bitno sz status.2 clr txflag snz txflag jmp stoptx sz bitcount ; bit number=16 bits+1 (leadframe) ; Timer/Event Counter 1 overflow time unit ; = ( ) ms=600 s ; enable TMR1 interrupt ; datal is read from ROM table (TABRDC) ; datah is read from ROM table (TABRDC) 14

15 jmp txing txstart: mov a,88 mov intcntcom,a set intc.1 clr intc.4 clr intc.3 set intc.0 clr tmr0c mov a,230 mov tmr0,a mov a,098h mov tmr0c,a set pb.0 clr pbc.0 txstart0: sz pb.0 jmp txstart1 clr.1 txstart1: snz intc.6 jmp txstart2 clr intc.6 inc leadframe inc frame txstart2: snz leadframe.2 jmp txstart0 inc bitcount clr leadframe jmp endtxbit txing: inc bith1 mov a,bithl xor a,01h snz status.2 jmp chk23 clr pbc.0 clr pb.0 jmp endtxbit ; leadframe interrupt number ; enable external interrupt ; clear external interrupt request flag ; disable Timer/Event Counter 1 interrupt ; enable global interrupt ; Timer/Event Counter 0 synchronized ; enable carrier output ; check leadframe pulses transmitted ; leadframe pulses transmitted ; leadframe=2.4ms and 88 pulses ; reset leadframe timer ; transmit bit data ; first: low pulse=600 s 15

16 chk23: mov a,bithl xor a,02h snz status.2 jmp chk3 mov a,22 sz byte1.7 add a,22 mov intcntcom,a set.1 clr.4 clr.3 set.0 clr tmr0c mov a,230 mov tmr0,a mov a,098h mov tmr0c,a set pb.0 clr pbc.0 txbit0: sz Pb.0 jmp txbit1 clr intc.1 txbit1: snz intc.6 jmp txbit0 clr intc.6 inc frame sz pb.0 jmp txbit0 txbit2: inc bitcount rlc byte0 rlc byte1 clr bith1 jmp label2 stoptx: clr pb.0 clr pbc.0 ; bit=0 22 pulses ; bit=1 44 pulses ; enable external interrupt ; clear external interrupt request flag ; disable Timer/Event Counter 1 interrupt ; enable global interrupt ; Timer/Event Counter 0 synchronized ; enable carrier output ; check leadframe pulses transmitted ; leadframe pulses transmitted ; all bits are transmitted 16

17 endtxbit: mov a,frame sub a,83 snz status.0 jmp endframe set txflag clr bitcount mov a,datal mov byte0,a mov a,datah mov byte1,a clr bith1 clr frame endframe: set intc.3 mov a,statusbuf2 mov status,a mov a,accbuf2 reti ; frame time-out re-send code ; reload data to related registers ; clear frame timer Synchronize the PFD Pulse (Generate the Desired Number of Pulses) Method 1: Synchronization by Using Timer/Event Counter 0 Generate PFD by using Timer/Event Counter 0 2 Timer/Event Counter 0 interrupt period will generate a PFD pulse Timer/Event Counter 0 interrupt should be enabled Timer/Event Counter 0 start counting from desired preload value to synchronize with PFD output and then enable Timer/Event Counter 0 counting Count the desired pulse in the Timer/Event Counter 0 interrupt service routine and then disable the PFD output by clearing PB.0 17

18 Method 2: Synchronization by Using External Interrupt Generate PFD by using Timer/Event Counter 0 Connect external PF0/INT pin to PB0 pin 1 PFD pulse will generate an external interrupt Timer/Event Counter 0 counting should be enabled External interrupt should be enabled to detect and count the PFD pulse number Count the desired pulse in the external interrupt service routine and then disable the PFD output by clearing PB.0 and the external interrupt Method 3: Generate Pulses by Using Software Instructions Generate pulses by using software instructions Pulse number can be controlled by using software counting Carrier output period can be controlled by timer/event counters Read Table from Program ROM (a) To locate a code section to a bank (definition) Use ROMBANK directive: ROMBANK n codesec ; n=0~4 (b) Load the bank number of the destination address into BP Use BANK directive: BANK label (c) Load high-order byte (with BANK) of table address in a bank to TBHP MOV A,HIGH table MOV TBHP,A (d) Load the lower-order byte of table address to TBLP MOV A,LOW table MOV TBLP,A (e) Use TABRDC to read table contents (f) 18

19 Example include ht48ca3.inc ; use HT48CA3 MCU body tablowbyte db? ; table low byte buffer ROMBANK 0 codesec0; definition ROMBANK 1 codesec1; definition ROMBANK 2 codesec2; definition codesec0.section at 000h code ; BANK 0 org 0000h clr bp jmp strt strt: mov a,high table0 ; get bank and high byte address mov tbhp,a mov a,low table0 ; get table 0 low byte address mov tblp,a tabrdc tablowbyte ; table read instruction mov a,high table1 ; get bank and high byte address mov tbhp,a mov a,low table1 ; get table 1 low byte address mov tblp,a tabrdc tablowbyte ; table read instruction mov a,high table2 ; get bank and high byte address mov tbhp,a mov a,low table2 ; get table 2 low byte address mov tblp,a tabrdc tablowbyte ; table read instruction talbe0: ; table0 is located in BANK 0 dc 0a55ah, 05aa5h ; bank 0 table 19

20 codesec1.section at 000h code ; BANK 1 table1: ; table 1 is located in BANK 1 dc 09669h, 06996h ; bank 1 table codesec2.section at 000h code ; BANK 2 table2: ; table 2 is located in BANK 2 02dd2h,0d22dh ; bank 2 table end Carrier Frequency (f CARRIER ) Calculation f PFD =f SYS /(2 t TMR0OV )=f CARRIER t TMR0OV =2 (PSC2~PSC0+1) (256-[TMR0]) 20

21 Crystal Oscillator Configuration t INTD : internal delay time and oscillator setting time t WU : crystal/resonator warm-up time (500 s~5ms), dependent on crystal/resonator quality/ capacitor (C1 and C2) t SST : system start-up time, f OSC / f OSC Ceramic Resonator Quartz Crystal C1 C2 C1 C2 393kHz 300pF 300pF 400kHz 300pF 300pF 455kHz 300pF 300pF 480kHz 300pF 300pF 600kHz 300pF 300pF 1MHz 120pF 120pF 0pF 0pF 2MHz 0pF 0pF 0pF 0pF 3.58MHz 0pF 0pF 0pF 0pF 3.82MHz 0pF 0pF 0pF 0pF 4MHz 0pF 0pF 0pF 0pF 4.2MHz 0pF 0pF 0pF 0pF Note Crystal/resonator oscillator bias resistor is built-in OSC1 and OSC2 capacitors (25pF and 30pF) are built-in 21

HT46RU26/HT46CU26 A/D Type 8-Bit MCU with UART

HT46RU26/HT46CU26 A/D Type 8-Bit MCU with UART A/D Type 8-Bit MCU with UART Technical Document Tools Information FAQs Application Note HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM HA0049E Read and Write Control