EE 231 Fall EE 231 Homework 10 Due November 5, 2010

Transcription

1 EE 23 Fall 2 EE 23 Homwork Du Novmbr 5, 2. Dsign a synhronous squntial iruit whih gnrats th following squn. (Th squn should rpat itslf.) (a) Draw a stat transition diagram for th iruit. This is a systm with 4 stats, whih rpats itslf: S S3 8 S 2 S2 S2 S 4 S3 4 S S4 S9 2 S5 8 S8 S7 S6

2 EE 23 Fall 2 (b) Writ a Vrilog program to implmnt th iruit. modul hw_p(input lk, rst, output rg [7:] ount); rg [3:] stat; lk ngdg rst) if (~rst) stat <= 4 h; ls as (stat) 4 d: stat <= 4 d; 4 d: stat <= 4 d2; 4 d2: stat <= 4 d3; 4 d3: stat <= 4 d4; 4 d4: stat <= 4 d5; 4 d5: stat <= 4 d6; 4 d6: stat <= 4 d7; 4 d7: stat <= 4 d8; 4 d8: stat <= 4 d9; 4 d9: stat <= 4 d; 4 d: stat <= 4 d; 4 d: stat <= 4 d2; 4 d2: stat <= 4 d3; 4 d3: stat <= 4 d; dfault: stat <= 4 d; as (stat) 4 d, 4 d2, 4 d4, 4 d6, 4 d8, 4 d, 4 d2: ount = 8 h; 4 d: ount = 8 h2; 4 d3: ount = 8 h4; 4 d5: ount = 8 h8; 4 d7: ount = 8 h; 4 d9: ount = 8 h2; 4 d: ount = 8 h4; 4 d3: ount = 8 h8; ndmodul 2

3 EE 23 Fall 2 2. Dsign a synhronous squntial iruit whih dtts th ourrn of at last thr s arriving at th input. Th s do not nd to arriv in onsutiv lok priods. Th output will go high aftr it ss thr s at th input. Th output will stay high until th systm ss thr onsutiv s at th input. Whn it ss thr onsutiv s, th iruit should rturn to th rst stat and start looking for thr s. Hr is what th output should look lik for typial input: Input Output (a) Draw a stat transition diagram for th iruit. rst no on two thr on two 3

4 EE 23 Fall 2 (b) Writ down a stat transition tabl for th iruit. Currnt Nxt Stat Input Stat Output no no no on on on on two two two two thr thr on thr thr on two on thr two no two thr 4

5 EE 23 Fall 2 () Writ a Vrilog program to implmnt th iruit. modul hw_p2(input lk, rst, x, output rg z); paramtr no = 3 h, on = 3 h, two = 3 h2, thr = 3 h3, on = 3 h4, two = 3 h5; rg [2:] stat, nxt_stat; lk, ngdg rst) if (rst == b) stat <= no; ls stat <= nxt_stat; ///* Dfin nxt stat ombinational blok */ x) as (stat) no : if (x == b) nxt_stat = no; ls nxt_stat = on; on: if (x == b) nxt_stat = on; ls nxt_stat = two; two: if (x == b) nxt_stat = two; ls nxt_stat = thr; thr: if (x == b) nxt_stat = on; ls nxt_stat = thr; on: if (x == b) nxt_stat = two; two: ls nxt_stat = thr; if (x == b) nxt_stat = no; ls nxt_stat = thr; dfault: stat = no; // /* Dfin output ombinational blok */ as (stat) no,on,two: z = b; thr,on,two: z = b; dfault: z = b; ndmodul 5

6 EE 23 Fall 2 3. Dsign a srial 8-bit two s omplmntr. Eight bits ar fd srially into th iruit, last signifiant bit first. Th srial output should b th 8-bit two s omplmnt of th input. Th iruit will transition bak to th rst stat aftr ah ight-bit pakt is prossd. Pag of th txt disusss how you an find th 2 s omplmnt of a numbr by looking at th bits, starting with th last signifiant bit. (a) Draw a stat transition diagram for th iruit. From th dsription in th txt, you an tak a 2 s omplmnt by laving all th last signifiant s and th first alon, thn invrting all subsqunt bits. Th stat mahin should hav th output qual to th input until th first. Aftr that, th output should b in th invrs of th input. You nd to kp trak of th numbr of vnts, and whthr or not you v gottn th first : start / / b_ni b_i / / b2_ni / b2_i / b3_ni b3_i x/x / / b4_ni b4_i / b5_ni b5_i / b6_ni b6_i / b7_ni b7_i You ould also implmnt this with just thr stats and a 3-bit ountr. Hav th ountr kp trak of th numbr of bits. Whn th numbr of bits is svn, go bak to th START stat: rst start ountr==7/x / ountr==7/x / no_invrt invrt x== & ountr<7 / ountr < 7/x x == & ount < 7/ 6

7 EE 23 Fall 2 (b) Writ a Vrilog program to implmnt th iruit. Hr is a vrilog program to implmnt th sond stat diagram: modul hw_p3(input lk, rst, x, output rg z); paramtr START = 2 b, NO_INVERT = 2 b, INVERT = 2 h; rg [:] stat; rg [2:] ount; lok, ngdg rst) if (~rst) bgin stat <= START; ount <= 3 b; nd ls as (stat) START: bgin ount <= 3 h; if (x == b) stat <= NO_INVERT; ls stat <= INVERT; nd NO_INVERT: bgin ount <= ount + ; if (ount == 7) stat <= START; ls if (x == ) stat <= NO_INVERT; ls stat <= INVERT; nd INVERT: bgin ount <= ount + ; if (ount == 7) stat <= START; ls stat <= INVERT; nd dfault: bgin stat <= START; ount <= 3 h; nd as (stat) START: z = x; NO_INVERT: z = x; INVERT: z = x ; dfault: z = bx; ndmodul 7

8 EE 23 Fall 2 4. Dsign a synhronous squntial iruit with two inputs x and x and a singl output z. Th iruit dtts any violation of th rul i bfor xpt aftr. Th lttr i is rprsntd by x =, th lttr is rprsntd by x =, th lttr is rprsntd by x =, and all othr lttrs ar rprsntd by x =. Th output z will go high for on lok yl if th iruit ss ithr an followd by an i whih was not prdd by a, or if th iruit ss i. (a) Draw a stat transition diagram for th iruit. Th rul is violatd if w s i or i. W hav th stats start, s_ (last haratr a ), s_ (last two haratrs ), t. In th stat diagram, mans th input haratr is a, mans th input haratr is an, i mans th input haratr is an i, and o mans th input haratr is anything othr than a, or i. Hr is a start to th stat diagram: rst s_n s_ s_n_ i i s_i s_n_i s_i 8

9 EE 23 Fall 2 Th abov stat diagram shows only on path to gt to th stat s_ (th stat whr th last lttr was ). Howvr, if you ar in any of th othr stats (.g., stat s_n_) and a oms along, you nd to go th stat s_. Similarly, if you ar in any stat xpt s_ and an oms along, you nd to go to th stat s n. This givs a lot mor paths to gt to th stats s_ and s_n_: rst s_n io io s_ o o s_n_ i i s_i s_n_i io io s_i 9

10 EE 23 Fall 2 (b) Writ a Vrilog program to implmnt th iruit. modul hw_p4(input lk, rst, input [:] x, output rg rr); paramtr lo = 2 b, li = 2 b, l = 2 b, l = 2 b; // Lttr othr than,, i // Lttr i // Lttr // Lttr paramtr s_n = 3 h, // Last haratr was not on in squn s_ = 3 h, // Last haratr was a s_i = 3 h2, // Last two hars wr i s_i = 3 h3, // Last thr hars wr i s_n_ = 3 h4, // Last two hars wr o s_n_i = 3 h5; // Last thr hars wr o i rg [2:] stat; lok, ngdg rst) if (~rst) stat <= s_n; ls as (stat) start: if x == l stat <= s_; ls if x == l stat <= s_n_; ls stat <= start; s_: if x == l stat <= s_; ls if x == li stat <= s_i; ls stat <= start; s_i: if x == l stat <= s_; ls if x == l stat <= s_i; ls stat <= start; s_n_: if x == l stat <= s_; ls if x == li stat <= s_n_i; ls if x == l stat <= s_n_; ls stat <= start; s_n_i: if x == l stat <= s_; ls if x == l stat <= s_n_; ls stat <= start; dfault: stat <= start; as (stat) start, s_, s_i, s_n_: z = b; s_i, s_n_i: z = b; ndmodul dfault: z = b;