Example (cont.): Control Flow Graph. 2. Interval analysis (recursive) 3. Structural analysis (recursive)

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1 DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 1 C.Kessler,IDA,Linköpings Universitet, Control Flow Analysis [ASU1e 10.4] [ALSU2e 9.6] [Muchnick 7] necessary to enable global optimizations beyond basic blocks basis for data-flow analysis reconstruction of if-then-else, loops from MIR, from unstructured source code or from target code! loops: candidates for loop transformations, software pipelining! if-then-else: candidates for predication identify basic blocks of a routine construct its flow graph / basic block graph 1. Dominator-based analysis (iterative) 2. Interval analysis (recursive) 3. Structural analysis (recursive) DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 3 C.Kessler,IDA,Linköpings Universitet, Example (cont.): Control Flow Graph // MIR 1 receive m 1 receive m // read arg value 2 f0 = 0 3 f1 = 1 4 if m<=1 goto L3 5 i = 2 6 L1: if i<=m goto L2 8 L2: f2 = f0 + f1 9 f0 = f1 10 f1 = f2 11 i = i goto L1 13 L3: return f2 12 return m f0 = 0 f1 = 1 m <= 1? 5 6 i = 2 i <= m? f2 = f0+f1 f0 = f1 f1 = f2 i = i + 1 DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 2 C.Kessler,IDA,Linköpings Universitet, Control Flow Analysis Running Example // Fibonacci - Iterative alg. unsigned int fib ( unsigned int m ) { unsigned int f0 = 0, f1 = 1, f2, i; if (m <= 1) return m; else { for (i=2; i<=m; i++) { f2 = f0 + f1; f0 = f1; f1 = f2; } return f2; } } // MIR, flattened 1 receive m // read arg value 2 f0 = 0 3 f1 = 1 4 if m<=1 goto L3 5 i = 2 6 L1: if i<=m goto L2 8 L2: f2 = f0 + f1 9 f0 = f1 10 f1 = f2 11 i = i goto L1 13 L3: return f2 DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 4 C.Kessler,IDA,Linköpings Universitet, Detecting basic blocks basic block (BB) = max. sequence of consecutive statements (IR or target level) that can be entered by program control only via the first one and left only via the last one. first instruction ( leader ) of a BB: either + point of a procedure, or + branch target, or + instruction immediately following a branch or return! call instructions need not delimit the basic block (ok for most cases, but not for e.g. instruction scheduling)! exception-based control transfer not considered here

2 successor BB s of a BB b: Succ(b) = fn 2 : (b n) 2 Eg predecessor BB s of a BB b: Pred(b) = fn 2 : (n b) 2 Eg DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 5 C.Kessler,IDA,Linköpings Universitet, Basic-block graph erminology: in [Muchnick 97] called control-flow graph CFG, whereas our CFG (statement level) is there called a flowchart rooted, directed graph = G E) ( nodes = basic blocks + + edges = control flow edges from CFG/flowchart (there connecting BB s to the leaders of their successor BBs) + enter! initial basic block + final basic blocks (no succ.)! DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 7 C.Kessler,IDA,Linköpings Universitet, Example (cont.): CFG + Basic Blocks! Basic Block Graph 1 receive m 2 f0 = 0 12 return m 3 4 f1 = 1 m <= 1? 5 i = 2 6 i <= m? 8 f2 = f0+f1 9 f0 = f1 10 f1 = f2 11 i = i + 1 DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 6 C.Kessler,IDA,Linköpings Universitet, Example (cont.): CFG! Basic Block Leaders 1 receive m 1 receive m 2 f0 = 0 2 f0 = 0 3 f1 = 1 3 f1 = 1 12 return m 4 m <= 1? 5 i = 2 12 return m 4 m <= 1? 5 i = 2 6 i <= m? 6 i <= m? 8 f2 = f0+f1 8 f2 = f0+f1 9 f0 = f1 9 f0 = f1 10 f1 = f2 10 f1 = f2 11 i = i i = i + 1 DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 8 C.Kessler,IDA,Linköpings Universitet, Extended basic blocks, regions Extended basic block (EBB) = max. sequence of instructions beginning with a leader that contains no join nodes other than (maybe) its first node! single, multiple s, tree-like internal control flow! EBB also known as treegion EBB s are useful for some optimizations e.g. instruction scheduling Algorithm for computing the EBB s of a CFG: see e.g. [Muchnick 7.1] Region = strongly connected subgraph (SCC) of the CFG with a single

3 ! Find uniform treatment for program loops DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 9 C.Kessler,IDA,Linköpings Universitet, Example (cont.): Extended Basic Blocks DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 11 C.Kessler,IDA,Linköpings Universitet, Graph-theoretic concepts of control-flow analysis (1) depth-first search (dfs): recursively explore descendants of a node before any of its siblings (as far as not yet visited) dfs-number: order in which dfs enters nodes tree edges: edges followed by dfs via recursive calls dfs-tree: ( nodes, tree edges ) non-tree edges classified as forward edges F back edges B cross edges C not unique! depends on ordering of descendants see also DFS-slides on course homepage DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 10 C.Kessler,IDA,Linköpings Universitet, Finding Loops Programs spend most of the execution time in loops.! Optimizations that exploit the loop structure are important loop unrolling, loop parallelization, software pipelining,... Loops may be expressed in programs by different constructs (while, for, goto,..., compiler-converted tail-recursion) Use a general approach based on graph-theoretic properties of CFG. DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 12 C.Kessler,IDA,Linköpings Universitet, Example: DFS-tree, edge classification B C 3 4 F B 7 3 B C 5 C 7 B 8 5 4

4 DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 13 C.Kessler,IDA,Linköpings Universitet, Graph-theoretic concepts of control-flow analysis (2) preorder traversal of a digraph G = ( E): at each node b 2 process b before its descendants (not unique; in dfsnum-order) postorder traversal at each node b 2 process b after its descendants DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 15 C.Kessler,IDA,Linköpings Universitet, Dominance intuition (1) Imagine a source of light going into the node, nodes are transparent and edges are optical fibers Lamp Place an opaque barrier at node v! nodes dominated by v get dark (Adapted from a nice presentation by J. Amaral 2003) DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 14 C.Kessler,IDA,Linköpings Universitet, Dominance, immediate dominance, strict dominance Given: flow graph G = ( E), nodes d i p b 2 d dominates b (d dom b) if every possible execution path! b includes d dom is reflexive, transitive, antisymmetric! partial order on i immediately dominates b (i idom b) if i dom b and there is no c 2, i 6= c 6= b, withi dom c and c dom b idom(b) is unique for each b 2! (i)dominator tree, rooted at strict dominance d sdom b if d dom b and d 6= b DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 16 C.Kessler,IDA,Linköpings Universitet, Dominance intuition (2) he node dominates all nodes: Lamp

5 Domin(r) frg; Domin(n) 8n 2 ;frg Domin(p) p2pred(n) DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 17 C.Kessler,IDA,Linköpings Universitet, Dominance intuition (3) ode dominates,,, : Lamp DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 19 C.Kessler,IDA,Linköpings Universitet, Postdominance p postdominates b (p pdom b) if every possible execution path b! includes p p pdom b () b dom p in the reversed flow graph DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 18 C.Kessler,IDA,Linköpings Universitet, Dominance intuition (4) ode only dominates itself: Lamp DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 20 C.Kessler,IDA,Linköpings Universitet, Computing the dominators of a node a dom b iff (1) a = b, or 9 (2) unique immediate predecessor of b, namely a, Pred(b) = i.e. fag, or (3) for all 2 Pred(b) c 6= c a and a dom c. Algorithm 1: change true; while ( change ) change false for all n 2 ;frg // in dfsnum order D fng[ if D 6= Domin(n) return Domin c1 c2 Domin(n) D; change true a... b

6 mp(n) Domin(n) ; fng mp(n) mp(n) ;ftg idom(n) the b 2mp(n) time O(elogn) or O(e α(e n)) DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 21 C.Kessler,IDA,Linköpings Universitet, Example: Computing dominators node i Domin(i), init. Domin(i), iter. 1 iter fg fg change=true... f,,,,,, g, g f, change=true... f,,,,,, g, f, g,... f,,,,,, g, f, g,... f,,,,,, g, f,, g,... f,,,,,, g, f,,,g,... f,,,,,, g, f,,,g,... f,,,,,, g, f, g,... DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 23 C.Kessler,IDA,Linköpings Universitet, Example: Computing immediate dominators node i init. mp(i)=domin(i) fig mp(i), iter. 1 fg fg fg fg f, g fg f, g fg f,, g fg f,,, g fg f,,, g fg f, g fg Dominator tree: DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 22 C.Kessler,IDA,Linköpings Universitet, Extension for computing immediate dominators... compute Domin... for each n 2 for each n 2 ;frg // in dfsnum order // if a s in mp(n) has a dominator t 6= s, removet from mp(n) for each s 2 mp(n) for each 2 mp(n) ;fsg t if 2 mp(s) t then for each n 2 ;frg // in dfsnum order otal time: O(n 2 e) if sets are represented by bitvectors DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 24 C.Kessler,IDA,Linköpings Universitet, Computing dominators Algorithm 2 [Lengauer/arjan 79] based on depth first search and path compression (see e.g. [Muchnick pp ])

7 Algorithm: Compute the loop node set for a given loop back edge (m n)! Easier to place new instructions immediately before the loop DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 25 C.Kessler,IDA,Linköpings Universitet, Loops and Strongly Connected Components We call a (backward, B) edge (m n) a loop back edge if n dom m. Remark: ot every B edge is a loop back edge! atural loop of a loop back (m n) edge = subgraph of n and all nodes v from which m can be reached without passing through n n is the loop header. n B v m a w a b b C c v B c d B d e e F c does not dominate d ) not a natural loop (2 points) DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 27 C.Kessler,IDA,Linköpings Universitet, Identifying the natural loop of a loop back edge Start by marking m and n as loop nodes. Backwards from m, (df)search predecessors v, stopping recursive backward search at already found loop nodes. w n? Can t exist because n dom m B v v m DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 26 C.Kessler,IDA,Linköpings Universitet, Example (cont.): atural Loop n m DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 28 C.Kessler,IDA,Linköpings Universitet, Loop header, preheader For technical reasons, add a pre-header (initially empty) if the header has more than 2 predecessors: header pre header B header B

8 DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 29 C.Kessler,IDA,Linköpings Universitet, Properties of atural Loops wo natural loops with different headers are either disjoint or one is nested in the other. Each natural loop is a SCC. Background: Strongly connected component (SCC) = subgraph S = (S E S), S, ES E, where every node in VS is reachable in S from every other node in VS via edges in ES. SCC s can be computed with arjan s algorithm (extension of dfs) in time O(jV j + jej) [arjan 72] Several loops sharing a common header node is a pathological special case that must be treated ad hoc. See e.g. Muchnick 7.4 for more details. DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 31 C.Kessler,IDA,Linköpings Universitet, Reducibility of flow graphs A flow-graph is reducible if all B edges in any DFS tree are loop back edges. Intuitively:... if there are no jumps into the middles of loops (e.g., goto s). b b c d e f c d c e f Reducible flow graphs are well-structured (loops properly nested). Irreducible flow graphs are rare and can be made reducible by replicating nodes. DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 30 C.Kessler,IDA,Linköpings Universitet, Properties of atural Loops (cont.) ASCCS V is maximal if every SCC containing S is just S itself. Example: S1 = f g is a maximal SCC. S2 = fg is a SCC but not a maximal SCC. DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 32 C.Kessler,IDA,Linköpings Universitet, Interval analysis Divide flowgraph into regions (e.g., loops in CFA) Repeatedly collapse a region to an abstract node! abstract flowgraph nested regions (control tree)! Hierarchical folding structure allows for faster / simpler data flow analysis Simplest variant: 1-2 Analysis [Ullman 73] 1: a 2: a ry to fold entire flow graph into a single node Works only for very restricted flow graphs

9 DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 33 C.Kessler,IDA,Linköpings Universitet, Analysis Example 1: a 2: a Example: a a 2: 1: 2: b b a b a b a 1-2 control tree DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 35 C.Kessler,IDA,Linköpings Universitet, Structural analysis Some regions and transformations self loop: a a if then: Bn a if then else: a a... stmt block: while loop: DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 34 C.Kessler,IDA,Linköpings Universitet, Structural Analysis is a special case of interval analysis: CFG folding follows the hierarchical structure of the program! folding transformations for loops, if-then-else, switch, etc. Every region has 1 point Works only for well-structured programs Extensions to handle arbitrary flowgraphs (define a new region / transf. for otherwise irreducible constructs) + Equations etc. for dataflow analysis can be pre-formulated for each construct! faster DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 36 C.Kessler,IDA,Linköpings Universitet, Example (cont.): Structural analysis procedure R9 R9 R8 R7 n m R8 R7 Region Hierarchy ree Remark: If only loop-based regions are of interest, the hierarchy flattens accordingly (R8 and R9 merged with top level).

10 DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 37 C.Kessler,IDA,Linköpings Universitet, Computing a bottom-up order of regions of a reducible flow graph Input: A reducible flow graph G Output: A bottom-up ordered list R of loop-based regions of G 1. R f :::g = all leaf regions, i.e., all single blocks in G, in any order 2. repeat Choose a natural loop L such that, if there are any natural loops L 0 contained within L, then the (body and loop) regions for these L 0 were already added to R. R.add( the region consisting of the body of L ) // body of L = L without the back edges to the header of L R.add ( the loop region for L ) until all natural loops have been considered 3. If the entire flow graph is not itself a natural loop, R.add( the region consisting of the entire flow graph ). DDC86 Compiler Optimizations and Code Generation Control Flow Analysis. Page 38 C.Kessler,IDA,Linköpings Universitet, Summary: Control-Flow Analysis Basic blocks, extended basic blocks Loop detection Dominator-based CFA Interval-based CFA Structural analysis

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