Intel 64 and IA-32 Architectures Software Developer s Manual

Transcription

1 Intel 64 and IA-32 Architectures Software Developer s Manual Volume 3A: System Programming Guide, Part 1 NOTE: The Intel 64 and IA-32 Architectures Software Developer's Manual consists of seven volumes: Basic Architecture, Order Number ; Instruction Set Reference A-M, Order Number ; Instruction Set Reference N-Z, Order Number ; Instruction Set Reference, Order Number ; System Programming Guide, Part 1, Order Number ; System Programming Guide, Part 2, Order Number ; System Programming Guide, Part 3, Order Number Refer to all seven volumes when evaluating your design needs. Order Number: US September 2014

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3 CONTENTS CHAPTER 1 ABOUT THIS MANUAL 1.1 INTEL 64 AND IA-32 PROCESSORS COVERED IN THIS MANUAL OVERVIEW OF THE SYSTEM PROGRAMMING GUIDE NOTATIONAL CONVENTIONS Bit and Byte Order Reserved Bits and Software Compatibility Instruction Operands Hexadecimal and Binary Numbers Segmented Addressing Syntax for CPUID, CR, and MSR Values Exceptions RELATED LITERATURE CHAPTER 2 SYSTEM ARCHITECTURE OVERVIEW 2.1 OVERVIEW OF THE SYSTEM-LEVEL ARCHITECTURE Global and Local Descriptor Tables Global and Local Descriptor Tables in IA-32e Mode System Segments, Segment Descriptors, and Gates Gates in IA-32e Mode Task-State Segments and Task Gates Task-State Segments in IA-32e Mode Interrupt and Exception Handling Interrupt and Exception Handling IA-32e Mode Memory Management Memory Management in IA-32e Mode System Registers System Registers in IA-32e Mode Other System Resources MODES OF OPERATION Extended Feature Enable Register SYSTEM FLAGS AND FIELDS IN THE EFLAGS REGISTER System Flags and Fields in IA-32e Mode MEMORY-MANAGEMENT REGISTERS Global Descriptor Table Register (GDTR) Local Descriptor Table Register (LDTR) IDTR Interrupt Descriptor Table Register Task Register (TR) CONTROL REGISTERS CPUID Qualification of Control Register Flags EXTENDED CONTROL REGISTERS (INCLUDING XCR0) SYSTEM INSTRUCTION SUMMARY Loading and Storing System Registers Verifying of Access Privileges Loading and Storing Debug Registers Invalidating Caches and TLBs Controlling the Processor Reading Performance-Monitoring and Time-Stamp Counters Reading Counters in 64-Bit Mode Reading and Writing Model-Specific Registers Reading and Writing Model-Specific Registers in 64-Bit Mode Enabling Processor Extended States CHAPTER 3 PROTECTED-MODE MEMORY MANAGEMENT 3.1 MEMORY MANAGEMENT OVERVIEW USING SEGMENTS PAGE Vol. 3A iii

4 CONTENTS Basic Flat Model Protected Flat Model Multi-Segment Model Segmentation in IA-32e Mode Paging and Segmentation PHYSICAL ADDRESS SPACE Intel 64 Processors and Physical Address Space LOGICAL AND LINEAR ADDRESSES Logical Address Translation in IA-32e Mode Segment Selectors Segment Registers Segment Loading Instructions in IA-32e Mode Segment Descriptors Code- and Data-Segment Descriptor Types SYSTEM DESCRIPTOR TYPES Segment Descriptor Tables Segment Descriptor Tables in IA-32e Mode CHAPTER 4 PAGING 4.1 PAGING MODES AND CONTROL BITS Three Paging Modes Paging-Mode Enabling Paging-Mode Modifiers Enumeration of Paging Features by CPUID HIERARCHICAL PAGING STRUCTURES: AN OVERVIEW BIT PAGING PAE PAGING PDPTE Registers Linear-Address Translation with PAE Paging IA-32E PAGING ACCESS RIGHTS PAGE-FAULT EXCEPTIONS ACCESSED AND DIRTY FLAGS PAGING AND MEMORY TYPING Paging and Memory Typing When the PAT is Not Supported (Pentium Pro and Pentium II Processors) Paging and Memory Typing When the PAT is Supported (Pentium III and More Recent Processor Families) Caching Paging-Related Information about Memory Typing CACHING TRANSLATION INFORMATION Process-Context Identifiers (PCIDs) Translation Lookaside Buffers (TLBs) Page Numbers, Page Frames, and Page Offsets Caching Translations in TLBs Details of TLB Use Global Pages Paging-Structure Caches Caches for Paging Structures Using the Paging-Structure Caches to Translate Linear Addresses Multiple Cached Entries for a Single Paging-Structure Entry Invalidation of TLBs and Paging-Structure Caches Operations that Invalidate TLBs and Paging-Structure Caches Recommended Invalidation Optional Invalidation Delayed Invalidation Propagation of Paging-Structure Changes to Multiple Processors INTERACTIONS WITH VIRTUAL-MACHINE EXTENSIONS (VMX) VMX Transitions VMX Support for Address Translation USING PAGING FOR VIRTUAL MEMORY MAPPING SEGMENTS TO PAGES PAGE iv Vol. 3A

5 CONTENTS CHAPTER 5 PROTECTION 5.1 ENABLING AND DISABLING SEGMENT AND PAGE PROTECTION FIELDS AND FLAGS USED FOR SEGMENT-LEVEL AND PAGE-LEVEL PROTECTION Code Segment Descriptor in 64-bit Mode LIMIT CHECKING Limit Checking in 64-bit Mode TYPE CHECKING Null Segment Selector Checking NULL Segment Checking in 64-bit Mode PRIVILEGE LEVELS PRIVILEGE LEVEL CHECKING WHEN ACCESSING DATA SEGMENTS Accessing Data in Code Segments PRIVILEGE LEVEL CHECKING WHEN LOADING THE SS REGISTER PRIVILEGE LEVEL CHECKING WHEN TRANSFERRING PROGRAM CONTROL BETWEEN CODE SEGMENTS Direct Calls or Jumps to Code Segments Accessing Nonconforming Code Segments Accessing Conforming Code Segments Gate Descriptors Call Gates IA-32e Mode Call Gates Accessing a Code Segment Through a Call Gate Stack Switching Stack Switching in 64-bit Mode Returning from a Called Procedure Performing Fast Calls to System Procedures with the SYSENTER and SYSEXIT Instructions SYSENTER and SYSEXIT Instructions in IA-32e Mode Fast System Calls in 64-Bit Mode PRIVILEGED INSTRUCTIONS POINTER VALIDATION Checking Access Rights (LAR Instruction) Checking Read/Write Rights (VERR and VERW Instructions) Checking That the Pointer Offset Is Within Limits (LSL Instruction) Checking Caller Access Privileges (ARPL Instruction) Checking Alignment PAGE-LEVEL PROTECTION Page-Protection Flags Restricting Addressable Domain Page Type Combining Protection of Both Levels of Page Tables Overrides to Page Protection COMBINING PAGE AND SEGMENT PROTECTION PAGE-LEVEL PROTECTION AND EXECUTE-DISABLE BIT Detecting and Enabling the Execute-Disable Capability Execute-Disable Page Protection Reserved Bit Checking Exception Handling CHAPTER 6 INTERRUPT AND EXCEPTION HANDLING 6.1 INTERRUPT AND EXCEPTION OVERVIEW EXCEPTION AND INTERRUPT VECTORS SOURCES OF INTERRUPTS External Interrupts Maskable Hardware Interrupts Software-Generated Interrupts SOURCES OF EXCEPTIONS Program-Error Exceptions Software-Generated Exceptions Machine-Check Exceptions EXCEPTION CLASSIFICATIONS PROGRAM OR TASK RESTART PAGE Vol. 3A v

6 CONTENTS 6.7 NONMASKABLE INTERRUPT (NMI) Handling Multiple NMIs ENABLING AND DISABLING INTERRUPTS Masking Maskable Hardware Interrupts Masking Instruction Breakpoints Masking Exceptions and Interrupts When Switching Stacks PRIORITY AMONG SIMULTANEOUS EXCEPTIONS AND INTERRUPTS INTERRUPT DESCRIPTOR TABLE (IDT) IDT DESCRIPTORS EXCEPTION AND INTERRUPT HANDLING Exception- or Interrupt-Handler Procedures Protection of Exception- and Interrupt-Handler Procedures Flag Usage By Exception- or Interrupt-Handler Procedure Interrupt Tasks ERROR CODE EXCEPTION AND INTERRUPT HANDLING IN 64-BIT MODE Bit Mode IDT Bit Mode Stack Frame IRET in IA-32e Mode Stack Switching in IA-32e Mode Interrupt Stack Table EXCEPTION AND INTERRUPT REFERENCE Interrupt 0 Divide Error Exception (#DE) Interrupt 1 Debug Exception (#DB) Interrupt 2 NMI Interrupt Interrupt 3 Breakpoint Exception (#BP) Interrupt 4 Overflow Exception (#OF) Interrupt 5 BOUND Range Exceeded Exception (#BR) Interrupt 6 Invalid Opcode Exception (#UD) Interrupt 7 Device Not Available Exception (#NM) Interrupt 8 Double Fault Exception (#DF) Interrupt 9 Coprocessor Segment Overrun Interrupt 10 Invalid TSS Exception (#TS) Interrupt 11 Segment Not Present (#NP) Interrupt 12 Stack Fault Exception (#SS) Interrupt 13 General Protection Exception (#GP) Interrupt 14 Page-Fault Exception (#PF) Interrupt 16 x87 FPU Floating-Point Error (#MF) Interrupt 17 Alignment Check Exception (#AC) Interrupt 18 Machine-Check Exception (#MC) Interrupt 19 SIMD Floating-Point Exception (#XM) Interrupt 20 Virtualization Exception (#VE) Interrupts 32 to 255 User Defined Interrupts CHAPTER 7 TASK MANAGEMENT 7.1 TASK MANAGEMENT OVERVIEW Task Structure Task State Executing a Task TASK MANAGEMENT DATA STRUCTURES Task-State Segment (TSS) TSS Descriptor TSS Descriptor in 64-bit mode Task Register Task-Gate Descriptor TASK SWITCHING TASK LINKING Use of Busy Flag To Prevent Recursive Task Switching Modifying Task Linkages TASK ADDRESS SPACE PAGE vi Vol. 3A

7 CONTENTS Mapping Tasks to the Linear and Physical Address Spaces Task Logical Address Space BIT TASK-STATE SEGMENT (TSS) TASK MANAGEMENT IN 64-BIT MODE CHAPTER 8 MULTIPLE-PROCESSOR MANAGEMENT 8.1 LOCKED ATOMIC OPERATIONS Guaranteed Atomic Operations Bus Locking Automatic Locking Software Controlled Bus Locking Handling Self- and Cross-Modifying Code Effects of a LOCK Operation on Internal Processor Caches MEMORY ORDERING Memory Ordering in the Intel Pentium and Intel486 Processors Memory Ordering in P6 and More Recent Processor Families Examples Illustrating the Memory-Ordering Principles Assumptions, Terminology, and Notation Neither Loads Nor Stores Are Reordered with Like Operations Stores Are Not Reordered With Earlier Loads Loads May Be Reordered with Earlier Stores to Different Locations Intra-Processor Forwarding Is Allowed Stores Are Transitively Visible Stores Are Seen in a Consistent Order by Other Processors Locked Instructions Have a Total Order Loads and Stores Are Not Reordered with Locked Instructions Fast-String Operation and Out-of-Order Stores Memory-Ordering Model for String Operations on Write-Back (WB) Memory Examples Illustrating Memory-Ordering Principles for String Operations Strengthening or Weakening the Memory-Ordering Model SERIALIZING INSTRUCTIONS MULTIPLE-PROCESSOR (MP) INITIALIZATION BSP and AP Processors MP Initialization Protocol Requirements and Restrictions MP Initialization Protocol Algorithm for Intel Xeon Processors MP Initialization Example Typical BSP Initialization Sequence Typical AP Initialization Sequence Identifying Logical Processors in an MP System INTEL HYPER-THREADING TECHNOLOGY AND INTEL MULTI-CORE TECHNOLOGY DETECTING HARDWARE MULTI-THREADING SUPPORT AND TOPOLOGY Initializing Processors Supporting Hyper-Threading Technology Initializing Multi-Core Processors Executing Multiple Threads on an Intel 64 or IA-32 Processor Supporting Hardware Multi-Threading Handling Interrupts on an IA-32 Processor Supporting Hardware Multi-Threading INTEL HYPER-THREADING TECHNOLOGY ARCHITECTURE State of the Logical Processors APIC Functionality Memory Type Range Registers (MTRR) Page Attribute Table (PAT) Machine Check Architecture Debug Registers and Extensions Performance Monitoring Counters IA32_MISC_ENABLE MSR Memory Ordering Serializing Instructions Microcode Update Resources Self Modifying Code Implementation-Specific Intel HT Technology Facilities Processor Caches Processor Translation Lookaside Buffers (TLBs) Thermal Monitor External Signal Compatibility PAGE Vol. 3A vii

8 CONTENTS 8.8 MULTI-CORE ARCHITECTURE Logical Processor Support Memory Type Range Registers (MTRR) Performance Monitoring Counters IA32_MISC_ENABLE MSR Microcode Update Resources PROGRAMMING CONSIDERATIONS FOR HARDWARE MULTI-THREADING CAPABLE PROCESSORS Hierarchical Mapping of Shared Resources Hierarchical Mapping of CPUID Extended Topology Leaf Hierarchical ID of Logical Processors in an MP System Hierarchical ID of Logical Processors with x2apic ID Algorithm for Three-Level Mappings of APIC_ID Identifying Topological Relationships in a MP System MANAGEMENT OF IDLE AND BLOCKED CONDITIONS HLT Instruction PAUSE Instruction Detecting Support MONITOR/MWAIT Instruction MONITOR/MWAIT Instruction Monitor/Mwait Address Range Determination Required Operating System Support Use the PAUSE Instruction in Spin-Wait Loops Potential Usage of MONITOR/MWAIT in C0 Idle Loops Halt Idle Logical Processors Potential Usage of MONITOR/MWAIT in C1 Idle Loops Guidelines for Scheduling Threads on Logical Processors Sharing Execution Resources Eliminate Execution-Based Timing Loops Place Locks and Semaphores in Aligned, 128-Byte Blocks of Memory MP INITIALIZATION FOR P6 FAMILY PROCESSORS Overview of the MP Initialization Process For P6 Family Processors MP Initialization Protocol Algorithm Error Detection and Handling During the MP Initialization Protocol CHAPTER 9 PROCESSOR MANAGEMENT AND INITIALIZATION 9.1 INITIALIZATION OVERVIEW Processor State After Reset Processor Built-In Self-Test (BIST) Model and Stepping Information First Instruction Executed X87 FPU INITIALIZATION Configuring the x87 FPU Environment Setting the Processor for x87 FPU Software Emulation CACHE ENABLING MODEL-SPECIFIC REGISTERS (MSRS) MEMORY TYPE RANGE REGISTERS (MTRRS) INITIALIZING SSE/SSE2/SSE3/SSSE3 EXTENSIONS SOFTWARE INITIALIZATION FOR REAL-ADDRESS MODE OPERATION Real-Address Mode IDT NMI Interrupt Handling SOFTWARE INITIALIZATION FOR PROTECTED-MODE OPERATION Protected-Mode System Data Structures Initializing Protected-Mode Exceptions and Interrupts Initializing Paging Initializing Multitasking Initializing IA-32e Mode IA-32e Mode System Data Structures IA-32e Mode Interrupts and Exceptions bit Mode and Compatibility Mode Operation Switching Out of IA-32e Mode Operation MODE SWITCHING Switching to Protected Mode Switching Back to Real-Address Mode INITIALIZATION AND MODE SWITCHING EXAMPLE Assembler Usage PAGE viii Vol. 3A

9 Vol. 3A ix CONTENTS PAGE STARTUP.ASM Listing MAIN.ASM Source Code Supporting Files MICROCODE UPDATE FACILITIES Microcode Update Optional Extended Signature Table Processor Identification Platform Identification Microcode Update Checksum Microcode Update Loader Hard Resets in Update Loading Update in a Multiprocessor System Update in a System Supporting Intel Hyper-Threading Technology Update in a System Supporting Dual-Core Technology Update Loader Enhancements Update Signature and Verification Determining the Signature Authenticating the Update Pentium 4, Intel Xeon, and P6 Family Processor Microcode Update Specifications Responsibilities of the BIOS Responsibilities of the Calling Program Microcode Update Functions INT 15H-based Interface Function 00H Presence Test Function 01H Write Microcode Update Data Function 02H Microcode Update Control Function 03H Read Microcode Update Data Return Codes CHAPTER 10 ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC) 10.1 LOCAL AND I/O APIC OVERVIEW SYSTEM BUS VS. APIC BUS THE INTEL 82489DX EXTERNAL APIC, THE APIC, THE XAPIC, AND THE X2APIC LOCAL APIC The Local APIC Block Diagram Presence of the Local APIC Enabling or Disabling the Local APIC Local APIC Status and Location Relocating the Local APIC Registers Local APIC ID Local APIC State Local APIC State After Power-Up or Reset Local APIC State After It Has Been Software Disabled Local APIC State After an INIT Reset ( Wait-for-SIPI State) Local APIC State After It Receives an INIT-Deassert IPI Local APIC Version Register HANDLING LOCAL INTERRUPTS Local Vector Table Valid Interrupt Vectors Error Handling APIC Timer TSC-Deadline Mode Local Interrupt Acceptance ISSUING INTERPROCESSOR INTERRUPTS Interrupt Command Register (ICR) Determining IPI Destination Physical Destination Mode Logical Destination Mode Broadcast/Self Delivery Mode Lowest Priority Delivery Mode IPI Delivery and Acceptance SYSTEM AND APIC BUS ARBITRATION HANDLING INTERRUPTS