Area and Power Efficient Modulo 2^n+1 Multiplier

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1 Iteratoal Joural of Moder Egeerg Research (IJMER) Vol.3, Issue.3, May-Jue. 013 pp ISSN: Area ad Power Effcet Modulo ^+1 Multpler K. Ptambar Patra, 1 Saket Shrvastava, Sehlata Sahu, 3 Sujt Kumar Patel Departmet of Electrocs & Commucato Egeerg Jaypee Uversty of Egeerg & Techology, Gua Abstract: I ths paper area-power effcet modulo +1 multpler s proposed. The result ad oe operad for the ew modulo multplers use weghted represetato, whle the other uses the dmshed- 1. By usg the radx-4 Booth recodg, the ew multplers reduce the umber of the partal products to / for eve ad (+1)/ for odd except for oe correcto term. Accordg to our algorthm, the resultg partal products are added through verted ed aroud carry save adder to two operads, whch are fally adder by a -stage -bt adder cotag :1 multplexer. By usg the purposed adder, the ew multplers reduce the area ad power. The aalytcal ad expermetal result dcates that the ew modulo +1 multplers, offer reduced power ad more compact area amog all the exstg structures. Keywords: -Stage -Bt Adder, Modulo Multpler, Resdue Number System (RNS). I. INTRODUCTION Resdue umber systems (RNS) reduce the delay of carres propagato, thus sutable for the mplemetato of hgh-speed dgtal sgal processg devces. Some arthmetc operatos, such as addto ad multplcato, ca be carred out more effcetly RNS tha covetoal two s complemet systems. RNS has bee adopted the desg of Dgtal Sgal Processors (DSP), Fte Impulse Respose (FIR) flters], mage processg uts, Dscrete Cose Trasform (DCT) processors, commucato compoets, cryptography, ad other DSP applcatos. I recet years, effcet schemes for modulo multplers have bee studed tesvely. Geerally, modulo +1 multplers ca be dvded to three categores, depedg o the type of operads that they accept ad output:. the result ad both puts use weghted represetato;. the result ad both puts use dmshed-1 represetato;. The result ad oe put use weghted represetato, whle the other put uses dmshed-1. For the frst category, Zmmerma et al. [1] used Booth ecodg to realze, but depart from the dmshed-1 arthmetc, whch leads to a complex archtecture wth large area ad delay requremets. For the secod category, Wag et al. [] proposed dmshed-1 multplers wth -bt put operads. The multplers use a o-booth recodg ad a zero partal-product coutg crcut. The ma drawback ths archtecture was hadlg of zero puts ad results were ot cosdered. Curger et al. [3] proposed ew modulo multplers by usg the thrd category. Ths archtecture use ROM based look-up methods are compettve. The ma drawback ths archtecture creasg -bt, they become feasble due to excessve memory requremets. Ja et al. [4] also proposed for the thrd category archtecture ad reduce the memory requremet ad speed up. The ew archtecture s based o -bt addto ad radx-4 booth algorthm, whch s effcet ad regular. We are replaced dmshed-1 modulo +1 adder by -stage -bt adder. The remader of the paper s orgazed as follows: mathematcal formulato of Dmshed-1 umber represetato computato of modulo multpler s preseted Secto II. The proposed structures are preseted Secto III. Hardware ad tme complexty of the proposed structures are dscussed ad compared wth the exstg structures Secto IV. Cocluso s preseted Secto V. II. DIMINISHED -1 NUMBER REPRESENTATION The modulo +1 arthmetc operatos requre (+1) bt operads. To avod (+1)-bt crcuts, the dmshed-1 umber system [15] has bee adopted. Let d[ be the dmshed-1 represetato of the ormal bary umber A [0, ], amely d () [ A I (), whe A 0, d[ [0, ],s a -bt umber, therefore (+1) -bt crcuts ca be avoded ths case. However, A 0, d[ 0] () Is a (+1) -bt umber. Ths leads to specal treatmet for d [0]. The dmshed-1 arthmetc operatos [15] are defed as d [, fd [ [0, ] () Page

2 Iteratoal Joural of Moder Egeerg Research (IJMER) Vol.3, Issue.3, May-Jue. 013 pp ISSN: d (v) [ A d d [ A (v) [ A d[ [ B B d (v) d[ k, CLS ( d[, k) (v) k d[, CLS ( d[, k) (v) Where d [ represets the oe s complemet of d[. I (v) ad (v) CLS (d[a], k) s the k -bt left-crcular shft of whch the bts crculated to the LSB are complemeted. III. PROPOSED ARCHITECTURE I the ew modulo +1 multplcato, the result ad oe put use weghted represetatos, whle the other put uses dmshed-1 represetato. Let d[=(a a -1 a 1 a 0 ) be the dmshed-1 represetato of weghted A, B=(b b - 1 b 1 b 0 ) ad P A B ( p 1 p... p0) all be weghted oe. Accordg toradx-4 booth recordg [15] the product ca be wrtte as Where Ad K PP C 0 P A B K (x) C K 1 c 0 /, eve K ( ) /, odd From (x) t s clear that the archtecture cossts of the partal products geerator (PPG), the correcto ter geerator (CTG), the verted ed-aroud-carry carry save adder (EAC CSA) ad -stage -bt adder. Based o ths archtecture, a soluto whch s more effectve s proposed. The ecodg scheme accordat wth the radx-4 Booth recodg [4], the partal product geerator (PPG) ca be costructed wth the well-kow Booth ecoder (BE) ad Booth selector (BS). The dfferet blocks used PPG ad EAC CSA are take from [4]. I ths paper, we modfed BE block whch take successve overlappg trplets ( b bb ) ad ecodes each as a elemet of the set {-,-1, 0, 1 }. Each BE block produces 3 bts: 1x, x ad Sg. The 3 bts alog wth the multplcad are used to form partal products Page

3 Iteratoal Joural of Moder Egeerg Research (IJMER) Vol.3, Issue.3, May-Jue. 013 pp ISSN: The CTG produces whch has the form (... 0x 10x... 0x1 0x0 ) wth x {0,1 }. Sce the -th bt x s 1 whe the BE block ecodes 0, otherwse x s 0, oe XNOR gate acceptg the 1x ad x bts of the block ca geerate the -th bt x. The verted EAC CSA tree ca reduce the Partal Products to two umbers. The CSA tree s usually costructed wth full adders (FA).The the fal two umbers from the tree s passed through the -stage -bt adder. The -stage -bt adder s cosstg of two rpple carry adder wth C =0 ad C =1ad oe :1 multplexer. The C out of frst -bt rpple carry adder s act as cotrol sgal to the multplexer. The two -bt sum of the rpple carry adder s gve to the multplexer. If C out =0 the the fal sum s the sum where the C =1 as show fg.(3). Fgure (a): Booth ecoder Page

4 Iteratoal Joural of Moder Egeerg Research (IJMER) Vol.3, Issue.3, May-Jue. 013 pp ISSN: Iput Output Code b +1 b b -1 Sg x 1x Fgure (b): Truth table Example: Whe, =8,Let A=(7) 10, B=(157) 10, the d[=(6) 10, A B ( Example =8,d[=( ),B=( ),a 8 =0,b 8 =0 Ecode Partal Products b ( b b )) b ( b ) PP ( b7 b PP b 3 b 7 b 5 b 4 b PP b 7 b 6 b PP CT= b Calculato ) Page

5 Iteratoal Joural of Moder Egeerg Research (IJMER) Vol.3, Issue.3, May-Jue. 013 pp ISSN: IV. RESULT AND SIMULATION The proposed archtecture has very low hardware complexty compared to [4], whch cosst of modulo +1 adder. I the proposed archtecture, we use the -stage verted -bt adder. Ad calculate the output for 8, 1, 16-bt. To estmate the tmg, area ad power formato for ASIC desg, we have used Syopsys Desg Compler to sythesze the desg to gate Level. Comparso of Syopsys result the proposed archtecture ad dmshed-1 modulo +1 archtecture s gve Table 1 ad Table respectvely. These mprovemets are reasoable. Whe compared wth Dmshed-1 modulo +1 multplers for weghted represetato; the blocks of the ew multplers are based o verted -bt adder archtecture ad use area-power effcet -bt adders. Table 1: Syopsys Result for Area Area(µm ) Multpler 8 bt 1 bt 16 bt Proposed Ja et al[4] Table : Syopsys Result for Power Power at 50Hz(µW) Multpler 8 bt 1 bt 16 bt Proposed Ja et al[4] V. CONCLUSION I ths paper, we proposed the area-power effcet a modulo +1 multpler. Ths archtecture uses -stage -bt adder, Booth recodg whch reduces the umber of the partal products to / for eve ad (+1)/ for odd, ths s the least umber of the partal products amog all modulo multplers publshed. The reducto scheme uses the well-kow verted EAC CSA tree ad the fal -stage verted -bt adder geerates the result. The crcut to hadle the zero-put case s merged to the frst Booth ecoder ad there s o extra delay to be added. The ew multplers, compared to exstg mplemetatos, offer better power whle beg more compact ad ther regular structure allows effcet VLSI mplemetatos. Refereces ( [1] R. Zmmerma, Effcet VLSI mplemetato of modulo ) addto ad multplcato, Proc. 14th IEEE Symp. Comput. Arthm., Adelade, Australa, Apr. 1999, pp [] Z.Wag, G. A. Julle, adw. C.Mller, A effcet tree archtecture for modulo ( ) multplcato, J. VLSI Sgal Process. Syst., vol.14, o. 3, pp , Dec [3] A. Curger, H. Boe berg, ad H. Kaesl, Regular VLSI archtectures for multplcato modulo ( ), IEEE J. Sold-State Crcuts,vol. 6, o. 7, pp , Jul [4] J.W.Che, R.H.Yao ad W.J.Wu, Effcet modulo ( ) multplers, IEEE Tras. VLSI systems, vol. 19, o 1, pp , Dec Page