From Math to Efficient Hardware. James C. Hoe Department of ECE Carnegie Mellon University

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1 FFT Compler: From Math to Effcet Hardware James C. Hoe Departmet of ECE Carege Mello Uversty jot wor wth Peter A. Mlder, Fraz Frachett, ad Marus Pueschel the SPIRAL project wth support from NSF ACR-3493, ITR/NGS-35687, DARPA NBCH-5,Itel The SPIRAL Project Hgh performace mplemetatos of lear DSP trasforms (DFT, DCT, DWT, flters, etc) are a mportat class of desg problems Had desg ad tug s trcy ad epesve - eeds both math ad mplemetato owledge - tme-cosumg ad tedous - eeds to repeat effort for every ew cotet SPIRAL research goal: A fleble push-butto desg geerato framewor that produces SW ad HW mplemetatos equal or better tha epert had desg Today I focus o FFT for HW Dataflow to Sythess Retrospectve, CSAIL/MIT, May 7, Slde

2 Why we ca do better tha had desg SPIRAL s oly focused o lear DSP trasforms These trasforms are hghly structured, hghly regular ad very well uderstood mathematcally Algorthmc mplemetatos of a trasform ca be eumerated followg a ow set of rules For a gve objectve fucto ad mappg target, a computer geerates a soluto at least as good as the best huma effort by tryg eough mplemetatos Dataflow to Sythess Retrospectve, CSAIL/MIT, May 7, Slde 3 Outle SPIRAL Formula Framewor SPIRAL for HW FFT cores Coclusos Dataflow to Sythess Retrospectve, CSAIL/MIT, May 7, Slde 4

3 Dataflow to Sythess Retrospectve, CSAIL/MIT, May 7, Slde 5 Lear Trasforms Lear trasform s matr-vector multplcato - computg by defto taes O(N ) operatos - the matr has structure E.g. dscrete Fourer trasform: y DFT N y y ẏj.. y N-... N-. N j e π.. N- j.. N- Dataflow to Sythess Retrospectve, CSAIL/MIT, May 7, Slde 6 Fast Algorthms a fast algorthm factors the matr to a sequece of structured, sparse matrces cheaper sparse multples O(N log(n)) operatos E.g. Cooley-Tuey Factorzato of DFT 4 Matr formula represetato ( ) ( ) m m m m m L DFT I D I DFT DFT

4 Fast Fourer Trasform Algorthms Recursvely factorze by the Cooley-Tuey rule utl oly leaf cases rema (e.g. DFT r for rad-r) DFT 8 Epoetal umber of alteratves Each ruletree correspods a dfferet algorthm All cost O(N log(n)) 8 8 ( DFT I 4 ) D ( I DFT4 ) L 8 4 ( DFT I ) D I ( DFT I ) D ( I DFT ) 4 DFT 8 DFT 4 DFT DFT DFT ( ( 4 ) 8 L L DFT 8 DFT DFT 4 DFT DFT Dataflow to Sythess Retrospectve, CSAIL/MIT, May 7, Slde 7 Formula to HW (Combatoal) Gve where s: - apply, the - s a permutato permute - apply, tmes parallel - s a dagoal scale B A A A Dataflow to Sythess Retrospectve, CSAIL/MIT, May 7, Slde 8

5 How about good HW? Matr formulas have a atural mappg to dataflow ad hece combatoal datapath However, real hardware desgs must ft a gve resource costrat sequetal datapath that reuse avalable HW - detfy repeated erels - statate erels uder resource costrats - schedule computato to reuse statated erels We wat to do the aalyss, mappg ad schedulg at formula level, wth hgh-level algorthm owledge Dataflow to Sythess Retrospectve, CSAIL/MIT, May 7, Slde 9 Regular Structure for HW Smple regular structure emboded Pease FFT Eample: Dataflow to Sythess Retrospectve, CSAIL/MIT, May 7, Slde

6 Pease DFT Eample: DFT 8 stage stage stage 3 (formula s appled from rght to left) Dataflow to Sythess Retrospectve, CSAIL/MIT, May 7, Slde Horzotal foldg p put bypass regster a basele datapath for DFT (sas bt-reverse) degree of freedom: vertcal parallelsm - parameter p Dataflow to Sythess Retrospectve, CSAIL/MIT, May 7, Slde

7 Vertcal (V-)foldg accordg to p cost latecy Fe-graed cotrol over cost/latecy tradeoff Dataflow to Sythess Retrospectve, CSAIL/MIT, May 7, Slde 3 DFTge [Mlder, et al., DAC 5, FPGA 6] fuctoalty cotrol area/latecy tradeoff resource model Dataflow to Sythess Retrospectve, CSAIL/MIT, May 7, Slde 4

8 Cost Performace Tradeoff latecy (usec) slces slces slces DFT 64 DFT 56 DFT 4 Dataflow to Sythess Retrospectve, CSAIL/MIT, May 7, Slde 5 Structures of Iterest for Parameterzed Cores Smple regular structure emboded formula Product: Horzotal foldg Tesor Product: parallelsm or streamg vertcal foldg Strde permutato: rewrg or buffer/delay Dataflow to Sythess Retrospectve, CSAIL/MIT, May 7, Slde 6

9 Applcablty to other trasforms? DFT rad DFT rad r -D DFT WHT [ L ( I DFT )] [ T ( I DFT ) L ] DP H DCT (type II) [ A L ] L L P R R / r / r [ T ( I r DFT r ) L r ] [( I r WHT r ) L r ] Dataflow to Sythess Retrospectve, CSAIL/MIT, May 7, Slde 7 Coclusos Mathematcal approach to DSP trasform mplemetato Ecapsulatg doma owledge a doma specfc tool for % automatc desg geerato ad optmzato Geeralzable to other lear DSP trasforms Tha you (Arvd) Dataflow to Sythess Retrospectve, CSAIL/MIT, May 7, Slde 8