45. Management Data Input/Output (MDIO) Interface

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1 Draft Amendment to IEEE Std. 0. January, Management Data Input/Output (MDIO) Interface Editor's notes: To be removed prior to final publication.. This clause contains all modifications to clause required by the IEEE P0.ap project. The text in this clause currently illustrates the new registers required to support AN over electrical backplanes (as referenced in Clause ) and PMD-specific functions. These changes are written as an amendment to IEEE 0.an. In some cases 0.ap needs to change the text in 0.am. Therefor all changes will proceed with an indication if it is a 0.an or 0.ap change. These changes need to be coordinated with changes from the IEEE P0.an and IEEE P0.aq projects.. Coordinate the combined registers with 0.an. Place registers to flow sequentially based on 0.REVam and any amendments to it... PMA/PMD registers This is an 0.an Rev. change: Change and insert the following registers. through. in Table - with the following: Register address Table PMA/PMD registers. through. Reserved. GBASE-KR PMD control. GBASE-KR PMD status Register name. GBASE-KR LP coefficient update. GBASE-KR LP status report. GBASE-KR LD coefficient update. GBASE-KR LD status report. through. GBASE-KR FEC corrected blocks counter Reserved. through. GBASE-KR FEC uncorrected blocks counter.0 00BASE-KX control. 00BASE-KX status. through. Reserved.0 Clause FEC capability. Clause FEC control. through. Clause FEC corrected blocks counter. through. Clause FEC uncorrected blocks counter. through.. Reserved This is an unapproved IEEE Standards Draft, subject to change page /

2 Draft Amendment to IEEE Std. 0. January, Restart training (..0) This bit maps to the state variable mr_restart_training as defined in Training enable (..) This bit maps the state variable mr_training_enable as defined in FEC Capable (..) When read as a one, this bit indicates if the GBASE-KR PHY supports Forward Error Correction (FEC). When read as a zero, the GBASE-KR PHY does not support Forward Error Correction.... Enable FEC (..) Table GBASE-KR PMD control register Bit(s) Name Description..: Reserved Value always zero, writes ignored.... Enable FEC Enable FEC Error Indication.. FEC Capable.. Training enable..0 Restart training = Read/Write, SC = self-clearing When written as a one, this bit enables the FEC for the GBASE-KR PHY. When written as a zero, FEC is disabled in the GBASE-KR PHY. This bit shall be set to zero upon execution of PHY reset.... Enable FEC Error Indication (..) A write of to this bit configures FEC decoder to indicate Error to the upper layer A write of to this bit enables FEC in the GBASE-KR PHY A read of in this bit indicates that the GBASE-KR PHY is FEC capable = Enable the GBASE-KR start-up protocol 0 = Disable the GBASE-KR start-up protocol = Reset GBASE-KR start-up protocol 0 = Normal operation This bit enables the FEC decoder to indicate decoding errors to the upper layers (PCS) through the sync bits for the GBASE-KR PHY in the Local Device. When written as a one, this bit enables indication of decoding errors through the sync bits to the PCS layer. When written as zero the error indication function is disabled. SC This is an unapproved IEEE Standards Draft, subject to change page /

3 January, 00 Draft Amendment to IEEE Std The assignment of bits in the GBASE-KR LD status report register is shown in Table. Table GBASE-KR LD status report register bit definitions Bit(s) Name Description.. Receiver ready = Read/Write... Receiver ready (..) The function and values for the receiver ready bit are defined in Coefficient (k) status (..:0) = The LD receiver has determined that training is complete and is prepared to receive data 0 = The LD receiver is requesting that training continue..: Reserved Value always 0, writes ignored..: Coefficient (+) status..: Coefficient (0) status..:0 Coefficient ( ) status = maximum 0 = minimum 0 = updated 0 0 = not_updated = maximum 0 = minimum 0 = updated 0 0 = not_updated 0 = maximum 0 = minimum 0 = updated 0 0 = not_updated The function and values for the coefficient status bits are defined in GBASE-KR FEC corrected blocks counter (Register.,.) The assignment of bits in the FEC corrected blocks counter register is shown in Table. See.. for a definition of this register. These bits shall be reset to all zeroes when the register is read by the management function or upon PHY reset. These bits shall be held at all ones in the case of overflow. Table -0 GBASE-KR FEC corrected blocks counter register bit definitions Bit(s) Name Description..:0 FEC corrected blocks lower FEC_corrected_blocks_counter[:0]..:0 FEC corrected blocks upper FEC_corrected_blocks_counter[:] = Read Only page / This is an unapproved IEEE Standards Draft, subject to change

4 Draft Amendment to IEEE Std. 0. January, GBASE-KR FEC uncorrected blocks counter (Register.,.) The assignment of bits in the FEC uncorrected blocks counter register is shown in Table. See.. for a definition of this register. These bits shall be reset to all zeroes when the register is read by the management function or upon PHY reset. These bits shall be held at all ones in the case of overflow. Table - GBASE-KR FEC uncorrected blocks counter register bit definitions Bit(s) Name Description..:0..:0 = Read Only FEC uncorrected blocks lower FEC uncorrected blocks upper... 00BASE-KX control register (Register.0)... PMD transmit disable (.0.0) FEC_uncorrected_blocks_counter[:0] FEC_uncorrected_blocks_counter[:] Table 0 00BASE-KX control register Bit(s) Name Description.0.: Reserved Value always zero, writes ignored.0.0 PMD transmit disable = Read Only, = Read/Write = Disable transmitter output 0 = Enable transmitter output This bit disables the 00BASE-KX transmitter as defined in 0... This is an unapproved IEEE Standards Draft, subject to change page /

5 January, 00 Draft Amendment to IEEE Std Clause FEC registers This is an change: Insert the following Clause FEC registers information as... and shift other subclauses. Renumber tables to flow sequentially based on and any amendments to it. The assignment of registers for Clause FEC is provided in Table.. Register Address Table Clause FEC registers.0 Clause FEC capability. Clause FEC control... Clause FEC capability register (Register.0) The assignment of bits in the Clause FEC capability register is shown in Table.... GBASE-KR FEC capable (.0.0) Register name.,. Clause FEC corrected blocks counter.,. Clause FEC uncorrected blocks counter Table Clause FEC capability register bit definitions Bit(s) Name Description.0.: Reserved Value always zero, writes ignored.0.0 GBASE-KR FEC capable = Read/Write, Read Only, SC = self-clearing A read of in this bit indicates that the GBASE-KR PHY is FEC capable When read as a one, this bit indicates if the GBASE-KR PHY supports Clause Forward Error Correction (FEC). When read as a zero, the GBASE-KR PHY does not support Forward Error Correction. page / This is an unapproved IEEE Standards Draft, subject to change

6 Draft Amendment to IEEE Std. 0. January, Clause FEC control register (Register.) The assignment of bits in the Clause FEC control register is shown in Table. Table Clause FEC control register bit definitions Bit(s) Name Description..: Reserved Value always zero, writes ignored.. Enable FEC Error Indication..0 Enable FEC = Read/Write, Read Only, SC = self-clearing... Enable FEC (..0) When written as a one, this bit enables Clause FEC for the GBASE-R PHY. When written as a zero, FEC is disabled in the GBASE-R PHY. This bit shall be set to zero upon execution of PHY reset.... Enable FEC Error Indication (..) A write of to this bit configures FEC decoder to indicate Error to the upper layer A write of to this bit enables Clause FEC A write of 0 to this bit disables Clause FEC This bit enables the Clause FEC decoder to indicate decoding errors to the upper layers (PCS) through the sync bits for the GBASE-R PHY in the Local Device. When written as a one, this bit enables indication of decoding errors through the sync bits to the PCS layer. When written as zero the error indication function is disabled.... Clause FEC corrected blocks counter (Register.,.) The assignment of bits in the Clause FEC corrected blocks counter register is shown in Table. See.. for a definition of this register. These bits shall be reset to all zeroes when the register is read by the management function or upon PHY reset. These bits shall be held at all ones in the case of overflow. Table Clause FEC corrected blocks counter register bit definitions Bit(s) Name Description..:0 FEC corrected blocks lower FEC_corrected_blocks_counter[:0]..:0 FEC corrected blocks upper FEC_corrected_blocks_counter[:] = Read Only, = Non Roll-over,, This is an unapproved IEEE Standards Draft, subject to change page /

7 Draft Amendment to IEEE Std. 0. January, Clause FEC uncorrected blocks counter (Register.,.) The assignment of bits in the Clause FEC uncorrected blocks counter register is shown in Table. See.. for a definition of this register. These bits shall be reset to all zeroes when the register is read by the managem Table Clause FEC uncorrected blocks counter register bit definitions Bit(s) Name Description..:0 FEC uncorrected blocks lower FEC_uncorrected_blocks_counter[:0]..:0 FEC uncorrected blocks upper FEC_uncorrected_blocks_counter[:] = Read Only, = Non Roll-over,, This is an unapproved IEEE Standards Draft, subject to change page /

Auto-Negotiation (AN) Overview

Auto-Negotiation (AN) Overview BRAD BOOTH, MICROSOFT ARTHUR MARRIS, CADENCE Scope Common text found in Clause 28, 37 and 73 Allows a device to advertise enhanced modes of operation it possesses to a device