Amir Sabbagh Molahosseini

Transcription

1 1 Amir Sabbagh Molahosseini: Curriculum Vitae Amir Sabbagh Molahosseini ACADEMIC POSITIONS EXPERIENCE: Assistant Professor Department of Computer Engineering Azad University of Kerman, Kerman, Iran Senior Researcher 2015 INESC-ID, Instituto Superior Tecnico (IST), University of Lisbon, Lisbon, Portugal Supervisor: Prof. Leonel Sousa Research Project: Designing Circuits and Systems for Signed Residue Number Systems EDUCATION: Ph.D.: Computer Engineering Major: Computer Architecture Azad University, Science and Research Branch, Tehran, Iran Thesis Title: High-Speed and Low-Cost VLSI Design for Residue to Binary Converters Based on New Moduli Sets Supervisor: Prof. Keivan Navi GPA: out of 20 (Thesis Grade: 20 of 20) 1 st Rank M.Sc.: Computer Engineering Major: Computer Architecture Azad University, Science and Research Branch, Tehran, Iran Thesis Title: Design of Circuits for Two-Level Residue Number System Supervisor: Prof. Keivan Navi GPA: out of 20 (Thesis Grade: 20 of 20) 1 st Rank B.Sc.: Computer Engineering Major: Hardware Shahid Bahonar University of Kerman, Kerman, Iran GPA: out of 20-3rd Rank RESEARCH INTERESTS: Deep Learning Computer Arithmetic with Special Emphasis on Residue Number Systems Arithmetic Circuits for Embedded Systems Design Alternative Computing Systems with Special Emphasis on Approximate Computing Reversible Design of Arithmetic Circuits ASIC and FPGA Design

2 2 Amir Sabbagh Molahosseini: Curriculum Vitae PUBLICATIONS: Edited Book: A.S. Molahosseini, L. Sousa and C. H. Chang, Embedded Systems Design with Special Arithmetic and Number Systems, Springer International Publishing, ISBN: , Switzerland, Mar Book Chapters: A.S. Molahosseini and L. Sousa, Introduction to Residue Number System: Structure and Teaching Methodology, Chapter 1 in the book Embedded Systems Design with Special Arithmetic and Number Systems, A.S. Molahosseini, L. Sousa and C. H. Chang (Editors), ISBN: , Springer International Publishing, Switzerland, Mar A.S. Molahosseini and K. Navi, Study of the Reverse Converters for the Large Dynamic Range Four-Moduli Sets, Chapter 16 in the Book Applications of Digital Signal Processing, C. C. Laborde (Editor), ISBN , InTech Press, Nov Journal Papers (Categorized By Publisher): IEEE: A.S. Molahosseini, A.A.E. Zarandi, P. Martins, and L. Sousa, A Multifunctional Unit for Designing Efficient RNS-based Datapaths, IEEE Access, vol. 5, pp , A.A.E. Zarandi, A.S. Molahosseini, L. Sousa, and M. Hosseinzadeh, An Efficient Component for Designing Signed Reverse Converters for a Class of RNS Moduli Sets of Composite Form {2 k, 2 P -1}, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 1, pp , S.M. Mirhosseini, A.S. Molahosseini, M. Hosseinzadeh, L. Sousa, and P. Martins, A Reduced- Bias Approach with a Lightweight Hard-Multiple Generator to Design Radix-8 Modulo 2 n +1 Multiplier, IEEE Transactions on Circuits and Systems-II: Express Briefs, vol. 64, no. 7, pp , C. H. Chang, A.S. Molahosseini, A. A. E. Zarandi, and T. F. Tay, Residue Number System: A new paradigm to datapath optimization for low-power and high-performance digital signal processing applications, IEEE Circuits and Systems Magazine, vol. 15, no. 4, pp , A.A.E. Zarandi, A.S. Molahosseini, M. Hosseinzadeh, S. Sorouri, S. Antao, and L. Sousa, Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology and Implementations, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 2, pp , K. Navi, A.S. Molahosseini, M. Esmaeildoust, How to Teach Residue Number System to Computer Scientists and Engineers, IEEE Transactions on Education, vol. 54, no. 1, pp , Feb A.S. Molahosseini, K. Navi, C. Dadkhah, O. Kavehei, S. Timarchi, Efficient Reverse Converter Designs for the New 4-Moduli Sets {2 n 1, 2 n, 2 n +1, 2 2n+1 1} and {2 n 1, 2 n +1, 2 2n, 2 2n +1} Based on New CRTs, IEEE Transactions on Circuits and Systems-I: Regular Papers, vol. 57, no. 4, pp , Apr

3 3 Amir Sabbagh Molahosseini: Curriculum Vitae Taylor & Francis: N.I. Chervyakov, A.S. Molahosseini, P.A. Lyakhov, M.G. Babenko, M.A. Deryabin, Residue-to- Binary Conversion for General Moduli Sets Based on Approximate Chinese Remainder Theorem, International Journal of Computer Mathematics, vol. 94, no. 9, pp , Springer: N. I. Chervyakov, A.S. Molahosseini, P. A. Lyakhov, M. G. Babenko, N. Lavrinenko, A. V. Lavrinenk, Comparison of modular numbers based on the Chinese remainder theorem with fractional values, Journal of Automatic Control and Computer Science, vol. 49, no. 6, pp , Elsevier: IEICE: USU: A.S. Molahosseini, K. Navi, O. Hashemipour, A. Jalali, An efficient architecture for designing reverse converters based on a general three-moduli set, Journal of Systems Architecture, vol. 54, no. 10, pp , Oct M. Esmaeildoust, M.R. Taheri, K. Navi, A.S. Molahosseini, S. Khodambashi, Efficient RNS to binary converters for the new 4-moduli set {2 n, 2 n+1-1, 2 n -1, 2 n-1-1}, IEICE Electronics Express, vol. 9, no. 1, pp. 1-7, Jul K. Navi, M. Esmaeildoust, A.S. Molahosseini, A General Reverse Converter Architecture with Low Complexity and High Performance, IEICE Transactions on Information and Systems, vol. E94-D, no. 2, pp , Feb A.S. Molahosseini, C. Dadkhah, K. Navi, M. Eshghi, Efficient MRC-Based Residue to Binary Converters for the New Moduli Sets {2 2n, 2 n 1, 2 n+1 1} and {2 2n, 2 n 1, 2 n 1 1}, IEICE Transactions on Information and Systems, vol. E92-D, no. 9, pp , Sep A.S. Molahosseini, C. Dadkhah, K. Navi, A New Five-Moduli Set for Efficient Hardware Implementation of the Reverse Converter, IEICE Electronics Express, vol. 6, no. 14, pp , Jul M. Hosseinzadeh, A.S. Molahosseini, K. Navi, An improved reverse converter for the moduli set {2 n 1, 2 n, 2 n +1, 2 n+1 1}, IEICE Electronics Express, vol. 5, no. 17, pp , Sep Others: A.S. Molahosseini, Improving the Delay of Residue-to-Binary Converter for a Four-Moduli Set, Advances in Electrical and Computer Engineering, vol. 11, no. 2, pp , May A.S. Molahosseini and A.A.E. Zarandi Towards Fast Implementation of Complex RNS Components on FPGAs, Science, Innovations and Technologies, vol. 4, pp , A.S. Molahosseini and A.A.E. Zarandi, Low-Power RNS Converter Using Modified RCA-EAC, International Journal of Computer Science Engineering, vol. 3, no. 3, pp , A.A.E. Zarandi, A.S. Molahosseini and M. Hosseinzadeh, Modern Residue Number System Moduli Sets: Efficiency vs. Complexity, Neurocomputers: Development and Application, Special Issue on High-Performance Computing, pp. 7-12, vol. 15, no. 9, 2014.

4 4 Amir Sabbagh Molahosseini: Curriculum Vitae A.S. Molahosseini, S. Jassbi, S. Sorouri, Design and FPGA Implementation of an Improved RNS Converter, Journal of Basic and Applied Scientific Research, vol. 2, no. 6, pp , A.S. Molahosseini, M.K. Rafsanjani, An Improved Five-Modulus Reverse Converter, World Applied Sciences Journal, vol. 11, no. 2, pp , Dec A.S. Molahosseini, M.K. Rafsanjani, S.H. Ghafouri, M. Hashemipour, A Reduced-Area Reverse Converter for the Moduli Set {2 2n-1 1, 2 n 1, 2 n }, International Journal of Advancements in Computing Technology, vol. 2, no. 5, pp , Dec S. Bakhshayesh, A.S. Molahosseini, K. Navi, A High Speed RNS to Binary Converter Based on Moduli Set {2 2n, 2 2n +2 n +1, 2 n 1}, International Journal of Computer Sciences and Engineering Systems, vol. 4, no. 3, pp , Jul A.S. Molahosseini, K. Navi, A High-Speed and Low-Cost Residue to Binary Converter Based on a New Moduli Set, International Journal of Automation & Systems Engineering, vol. 2, no. 1, pp , A.S. Molahosseini, M. Hosseinzadeh, K. Navi, A Multiplier-Free Residue to Weighted Converter for the Moduli set {3 n 2, 3 n 1, 3 n }, Contemporary Engineering Sciences, vol. 1, no. 2, pp , A.S. Molahosseini, K. Navi, New Arithmetic Residue to Binary Converters, International Journal of Computer Sciences and Engineering Systems, vol. 1, no. 4, pp , Oct M. Hosseinzadeh, A.S. Molahosseini, K. Navi, A Fully Parallel Reverse Converter, International Journal of Electrical, Computer, and Systems Engineering, vol. 1, no. 3, pp , Sep Conference Papers: A.S. Molahosseini, Ailin Asadpoor, A.A.E. Zarandi, L. Sousa, Towards Efficient Modular Adders Based on Reversible Circuits, in Proc. of the IEEE International Symposium on Circuits and Systems, Florence, Italy, May 27-30, A.A.E. Zarandi, A.S. Molahosseini, L. Sousa, M. Hosseinzadeh, and K. Navi, Area-Delay- Power-Aware Adder Placement Method for Designing RNS Reverse Converters, in Proc. of the IEEE Latin-America International Symposium on Circuits and Systems, Brazil, Feb. 28- Mar. 2, H. Pettenghi, R.D. Matos, and A.S. Molahosseini, RNS reverse converters for moduli sets with dynamic ranges of 9n-bit, in Proc. of the IEEE Latin-America International Symposium on Circuits and Systems, Brazil, Feb. 28-Mar. 2, A.S. Molahosseini, A.A.E. Zarandi, S.M. Mirhosseini, and M. Hosseinzadeh, Rethinking Reverse Converter Design: From Algorithms to Hardware Componenets, in Proc. of the IEEE International Symposium on Integrated Circuits (ISIC'14), Singapore, Dec , 2014 (Invited Paper). S. Jahanshahi and A.S. Molahosseini, Towards Fast Implementation of Fully Homomorphic Encryption: An RNS Approach, in Proc. of the International Conference on Parallel Computer Algebra and its Applications in New IC Systems, Stavropol, Russia, Dec , A.A.E. Zarandi, A.S. Molahosseini, M. Hosseinzadeh, High-Speed FPGA Implementation of Reverse Converters using Parallel-Prefix Adders, in Proc. of the 22 nd Iranian Conference on Electrical Engineering, Tehran, Iran, May , 2014 (In Persian, Best Paper Award).

5 5 Amir Sabbagh Molahosseini: Curriculum Vitae M. Mohammadi and A.S. Molahosseini, Efficient Design of Elliptic Curve Point Multiplication based on Fast Montgomery Modular Multiplication, in Proc. of 3 rd IEEE International Conference on Computer and Knowledge Engineering, Mashhad, Iran, Oct. 31- Nov. 1, A.S. Molahosseini, S. Sorouri, A.A.E. Zarandi, Research Challenges in Next-Generation Residue Number System Architectures, in Proc. of the 7 th IEEE International Conference on Computer Science and Education (ICCSE'12), Melbourne, Australia, Jul , A.S. Molahosseini, Efficient Residue to Binary Conversion Based on a Modified Flexible Moduli Set, in Proc. of the First Symposium on Advances in Computer Science and Applied Mathematics (a part of ICNAAM 2011), Halkidiki, Greece, Sep , A.S. Molahosseini, K. Navi, A Reverse Converter for the Enhanced Moduli Set {2 n 1, 2 n +1, 2 2n, 2 2n+1 1} Using CRT and MRC, in Proc. of IEEE Computer Society Annual Symposium on VLSI (ISVLSI 10), Kefalonia, Greece, Jul , A.S. Molahosseini, F. Teymouri, K. Navi, A New Four-Modulus RNS to Binary Converter, in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS 10), Paris, France, May 30-June 2, A.S. Molahosseini, S. Sezavar, K. Navi, A New Design of Reverse Converter for a Three- Moduli Set, in Proc. of IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 09), Kanazawa, Japan, Dec. 7-9, M. Hosseinzadeh, A.S. Molahosseini, K. Navi, A Parallel Implementation of the Reverse Converter for the Moduli Set {2 n, 2 n 1, 2 n 1 1}, in Proc. of International Conference on Computer Engineering and Technology, Oslo, Norway, Jul , A.S. Molahosseini, K. Navi, M.K. Rafsanjani, A New Residue to Binary Converter Based on Mixed-Radix Conversion, in Proc. of 3 rd International Conference on Information & Communication Technologies: From Theory to Applications (ICTTA 08), Damascus, Syria, Apr. 7-11, A.S. Molahosseini, K. Navi, M.K. Rafsanjani, Efficient Forward and Reverse Converters for a New High-Radix Moduli Set, in Proc. of 3 rd International Symposium on Information Technology (ITSim 08), Kuala Lumpur, Malaysia, Aug , A.S. Molahosseini, K. Navi, A New Residue to Binary Converter, in Proc. of 13 th National CSI Computer Conference of Iran, Kish, Iran, Mar. 9-11, 2008 (in Persian). A. S. Molahosseini, K. Navi, An Improved Residue to Binary Converter for the RNS with Pairs of Conjugate Moduli, in Proc. of International Conference on Electrical Engineering and Informatics, Bandung, Indonesia, Jun , A.S. Molahosseini, K. Navi, Two-Level Implementation of the Residue to Binary Converter for the 4-Moduli Set {2 n 1, 2 n, 2 n +1, 2 n+1 1}, in Proc. of International Conference on Electrical Engineering and Informatics, Bandung, Indonesia, Jun , More than 10 Persian papers in national conferences Technical Report: A.A.E. Zarandi, A.S. Molahosseini and L. Sousa, ASIC and FPGA Implementations of Modern 4-Moduli RNS Reverse Converters Using Distinct Configurations, Instituto de Engenharia de Sistemas e Computadores (INESC-ID) Technical Report 8/2015, Portugal, Mar

6 6 Amir Sabbagh Molahosseini: Curriculum Vitae HONORS: Co-Organizer of the Special Session on Modular Arithmetic based Circuits and Systems for Emerging Technologies and Applications: Deep Neural Networks and Cryptography in the IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, Best Researcher among faculty members in Azad University of Kerman, Sole Organizer of the Special Session on Residue Number Systems: Modern Applications and Design Techniques in the IEEE International Symposium on Integrated Circuits, Nanyang Technological University (NTU), Singapore, Ranked 1 st among Ph.D. Students (Computer Architecture Major of CE) of Department of Computer Engineering, Azad University, Science and Research Branch, Tehran, Ranked 1 st among M.Sc. Students (Computer Architecture Major of CE) of Department of Computer Engineering, Azad University, Science and Research Branch, Tehran, Ranked 3 rd among B.Sc. Students (Hardware Major of CE) of Department of Computer Engineering, Shahid Bahonar University of Kerman, Kerman, Received Full Ph.D. Scholarship from Azad University, PROFESSIONAL ACTIVITIES: Reviewer for the following Journals: IEEE Transactions on Very Large Scale Integration (VLSI) Systems IEEE Transactions on Circuits and Systems-I: Regular Papers IEEE Transactions on Circuits and Systems-II: Express Briefs IEEE Transactions on Circuits and Systems for Video Technology IEEE Transactions on Computers Springer Journal of Circuits, Systems, and Signal Processing Springer Journal of VLSI Signal Processing Systems Springer Analog Integrated Systems and Signal Processing Integration, the VLSI Journal, Elsevier International Journal of Electronics, Taylor & Francis TEACHING EXPERIENCES: Computer Arithmetic Computer Architecture Advanced Computer Architecture Advanced Topics in Computer Arithmetic PROFESSIONAL MEMBERSHIPS: Senior Member, Institute of Electrical and Electronics Engineers (IEEE)