Next Gen Infrastructure Core (NGIC) & M-CORD

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1 Next Gen Infrastructure Core (NGIC) & M-CORD Christian Maciocco Principal Engineer, Director of Telecom Systems Research Intel Labs Ashok Sunder Rajan, Kannan Babu Ramia, Sai Edupuganti, Jacob Cooper, Karla Saur Intel Labs CORD Build Event - November 7-9 th, 2017 San Jose, CA Intel Labs

2 Legal Disclaimer This presentation contains the general insights and opinions of Intel Corporation ( Intel ). The information in this presentation is provided for information only and is not to be relied upon for any other purpose than educational. Use at your own risk! Intel makes no representations or warranties regarding the accuracy or completeness of the information in this presentation. Intel accepts no duty to update this presentation based on more current information. Intel is not liable for any damages, direct or indirect, consequential or otherwise, that may arise, directly or indirectly, from the use or misuse of the information in this presentation. Intel technologies features and benefits depend on system configuration and may require enabled hardware, software or service activation. Learn more at intel.com, or from the OEM or retailer. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. Intel, the Intel logo and Xeon are trademarks of Intel Corporation in the United States and other countries. *Other names and brands may be claimed as the property of others Intel Corporation. Intel Confidential 2

3 Agenda vepc Background Next Generation Infrastructure Core (NGIC) CORD High Level View NGIC and M-CORD Summary / Next Steps Intel Labs 3

vepc Background (1/2) MME S11 Control Data SGW PGW User Data S1U Operators real traffic (San Jose, Houston, Chicago, ) Identified system s bottleneck Understanding Bottlenecks in Virtualizing

4 vepc Background (1/2) MME S11 Control Data SGW PGW User Data S1U Operators real traffic (San Jose, Houston, Chicago, ) Identified system s bottleneck Understanding Bottlenecks in Virtualizing Cellular Core Network functions, IEEE LANMAN 15 No independent control or data plane scaling Other names and brands may be claimed as the property of others Intel Labs User plane capacity reduction as control plane interference increases 4

5 vepc Background (2/2) NODE1 1GbE SW IVB SKT0 HT=1 2x12=24 LCORES IVB SKT1 2x12=24 LCORES S1MME MME HSS SGW PGW Mngt IF RAN Emulator Signaling & U/L User Plane Traffic generator enb PktGen1 GTP-U UDP/IP U/L S1MME S1U 10GbE SW S1U Mngt IF IVB SKT0 HT=1 2x12=24 LCORES NODE2 IVB SKT1 2x12=24 LCORES SGW PGW SGi 10GbE SW SGi PktGen1 IP D/L Application Load Generator App Server (Video, Web, ) App Server (Video, Web, ) App Server (Video, Web, ) App Server (Video, Web, ) PktGen4 GTP-U UDP/IP S1U SGi PktGen4 IP NODEN IVB SKT0 HT=1 2x12=24 LCORES IVB SKT1 2x12=24 LCORES Mngt IF S1U SGW EPC Setup PGW SGi User Plane Traffic Model Other names and brands may be claimed as the property of others Intel Labs User plane and control plane queue flooding 5

6 Agenda vepc Background Next Generation Infrastructure Core (NGIC) CORD High Level View NGIC and M-CORD Summary / Next Steps Intel Labs 6

7 Next Generation Infrastructure Core (NGIC) What is it? Why? Research and collaborations to understand telecom workloads behavior on Intel Architecture Research to address software/hardware platform improvements Released learnings and optimized reference software into open source community (DPDK, CORD) S/P-GW, Cuckoo Hash for optimized lookup from collaborations with industry or academic partners MME, HSS, PCRF will be released later Investigate functionality for new usage models, e.g. Connectionless IOT, Multi-Radio Access Technologies, etc NGIC is not a product and will not be a product from Intel Intel Labs 7

Next Generation Infrastructure Core (NGIC) Traditional EPC Architecture Disaggregated Architecture Control Data MME & S/PGW Control ONLY MME S11 Control Data SGW PGW SW Defined Network (Separation of

8 Next Generation Infrastructure Core (NGIC) Traditional EPC Architecture Disaggregated Architecture Control Data MME & S/PGW Control ONLY MME S11 Control Data SGW PGW SW Defined Network (Separation of Control and Data) SDN Controller User Data SGW PGW User Data Data ONLY Data ONLY S1U Operators real traffic (San Jose, Houston, Chicago, ) Identified system s bottleneck SDN based architecture Match/Action semantic data plane Understanding Bottlenecks in Virtualizing Cellular Core Network functions, IEEE LANMAN 15 Independent & scalable control & data No independent control or data scaling Intel Labs Other names and brands may be claimed as the property of others Functional EPC per operator s requirements 8

Functional EPC per Operator s Requirements - NGIC https://gerrit.opencord.

Control) ZeroMQ, OF 1.3 previously w/ Vendors Ext. Spirent RAN Emulator S1U DL UL IP Forward GTP-U Decap GTP-U Encap Rule Identif. DL Data Indic.

9 Functional EPC per Operator s Requirements - NGIC HSS MME PCRF SW to be released later MME Control Plane Intel Sprint Spirent SDN Controller IETF DMM FPC (Forwarding & Policy Control) ZeroMQ, OF 1.3 previously w/ Vendors Ext. Spirent RAN Emulator S1U DL UL IP Forward GTP-U Decap GTP-U Encap Rule Identif. DL Data Indic. Bearer Mapping Tables and Policies Charging SDF Metering Metering (SDF, APN) Charging Bearer Mapping IP Forward Rule Identif. Uplink (UL) Downlink (DL) SGi Spirent Apps Server Other names and brands may be claimed as the property of others Intel Labs Data Plane 9

10 PACKETS PER SECOND Linear Scaling Characteristics From Sprint s Presentation at NFV World Congress, May packet processing core Scaling with Number of Cores Million pps (50k subs) Million pps (500k subs) packet processing cores Million pps (50k subs) 6.5 Million pps (500k subs) All packet processing cores implement all network functions (PGW, SGW, DPI, k Subs Child Protection, k Subs 500k Subs CG-NAT, static FW & SFC) Additional (overhead) cores for C3PO EPC Data Plane Node Rx Core Tx Core Load-balancing Core Master Core Interface Core Packet processing cores are in addition to the overhead cores NUMBER OF PACKET PROCESSINGCORES 2016 Sprint. This information is subject to Sprint policies regarding use and is the property of Sprint and/or its relevant affiliates and may contain restricted, confidential or privileged materials intended for the sole use of the intended recipient. Any review, use, distribution or disclosure is prohibited without authorization. 11/9/2017 2:02 PM Version

11 Agenda vepc Background Next Generation Infrastructure Core (NGIC) CORD High Level View NGIC and M-CORD Summary / Next Steps Intel Labs 11

12 M-CORD Enabling the Programmable 5G Edge Cloud Source: Open Networking Foundation

13 M-CORD: Enabling the Programmable 5G Edge Cloud Disaggregation Cloudification Open Source Virtualization Programmability PROGRAMMABLE 5G EDGE CLOUD Source: Open Networking Foundation

Edge Cloud Wireless Access Edge Cloud Core

NFV Before with dedicated hardware Radio

14 Edge Cloud Wireless Access Edge Cloud Core PROGRAMMATICALLY instantiate slices for different use cases Virtualized RAN Control Virtualized EPC DISAGGREGATE RAN VIRTUALIZE RAN components in the Cloud SDN-ize it for PROGRAMMABILITY DISAGGREGATE Core VIRTUALIZE all components in the Cloud SDN-ize it for PROGRAMMABILITY After with SDN & NFV Before with dedicated hardware Radio enodeb EPC Source: Open Networking Foundation

15 M-CORD as the Edge Cloud HSS PCRF vpgw-c vsgw-u CU-U CU-c Low ONOS xran vmme vhss vpcrf vsgw-u vsgw-c vpgw-u vpgw-c ONOS XOS OpenStack vpgw-u Core Cloud PDN vsgw-c vmme RRU + DU M-CORD Edge Cloud Source: Open Networking Foundation

16 M-CORD Usage Models RAN and Access SD-RAN: xran + ONOS Multi-Radio (MRAT) WiFi / LTE Steering End-to-End Solution PoCs & Capabilities Multi-Access CORD End-to-End Network Slice Stitching Diversification of Hardware Choices Virtualized RAN Virtualized EPC Control Mobile Core Commercial Small Cells CBRS Spectrum Open Source EPC Infrastructure Acceleration WiFi RAN Slicing Source: Open Networking Foundation

17 Agenda vepc Background Next Generation Infrastructure Core (NGIC) CORD High Level View NGIC and M-CORD Summary / Next Steps Intel Labs 17

18 NGIC (vepc) & M-CORD

NGIC & M-CORD M-CORD XOS ONOS HSS PCRF Millions of Any-G Connections Full Mobility with Traffic Call Modeling Topology Emulation Full virtual ETSI Compliant S1-U vls Spirent Landslide

19 NGIC & M-CORD M-CORD XOS ONOS HSS PCRF Millions of Any-G Connections Full Mobility with Traffic Call Modeling Topology Emulation Full virtual ETSI Compliant S1-U vls Spirent Landslide Virtual S1-AP MME (VM) S/P-GW-c (VM) S/P-GW-u (VM) Infrastructure Virtualization (Openstack) (OvS/DPDK based) Compute Networking Storage Internet SGi Source: Open Networking Foundation

20 LOGICAL NETWORK CONNECTIVITY IN CORD S/P-GW-c (VM) CP-DP_net S/P-GW-u (VM) S11_net S1U_net SGI_net MME (VM) Emulated enb App Server

21 PHYSICAL NETWORK CONNECTIVITY Legend: A,D management MANAGEMENT B,E CP-DP_net PRIVATE C S11_net ACCESS_AGENT F S1U_net ACCESS_AGENT G SGI_net ACCESS_AGENT S/P-GW-c S/P-GW-u A B C D E F G vswitch (OVS / OVS-DPDK) Switch vls RAN + MME + App server

22 M-CORD using OvS/DPDK and Enhanced Platform Awareness networking-onos CORD-1488 XOS ONOS CORD Installer CORD-1483 CORD-1484 CORD-1486 HSS MME PCRF S/P-GW-c S/P-GW-u nova-compute CORD-1684 CORD-1485 CORD-1842 Infrastructure Virtualization (Openstack) (OvS/DPDK based) CORD-1483: Configure Nova with DPDK-enabled flavors CORD-1484: Add nova config options to juju_config.yml CORD-1485: Install OVS-DPDK through nova-compute charm CORD-1486: Set kernel commandline parameters for compute nodes CORD-1488: Add VIF details to handle VHOST_USER port type. CORD-1684: Backport libvirt driver changes, to enable memaccess=shared tag required for correct functioning of VHOST_USER CORD-1842: Replace default QEMU with patched QEMU for correct functioning of VHOST_USER

M-CORD using OvS/DPDK and Enhanced Platform Awareness L2FWD Throughput in CORD w/ OvS/DPDK vs. CORD w/ OvS (Higher is better) L2 FWD Latency in CORD w/ OvS/DPDK vs.

23 M-CORD using OvS/DPDK and Enhanced Platform Awareness L2FWD Throughput in CORD w/ OvS/DPDK vs. CORD w/ OvS (Higher is better) L2 FWD Latency in CORD w/ OvS/DPDK vs. CORD w/ OvS (Lower is better) - Features used to achieved high performance on CORD - OvS/DPDK - Enhanced Platform Awareness: - VM memory backed by Huge Pages - CPU isolation - Core pinning - vhost user data path

Modules: vepc & M-RAT (1/2) XOS ONOS Multi-RAT Control-Plane Measurements management E2E

enb Ctrl MME S/P-GW-c Internet M-RAT client LTE User Data S/P-GW-u Infrastructure

Encapsulation & Tunneling Concatenation & Fragmentation Buffering & Retransmissions LTE

24 Modules: vepc & M-RAT (1/2) XOS ONOS Multi-RAT Control-Plane Measurements management E2E Protocols Client / Session Management Data-Plane / Traffic Managements HSS PCRF Emulated enb Ctrl MME S/P-GW-c Internet M-RAT client LTE User Data S/P-GW-u Infrastructure Virtualization (Openstack) (OvS/DPDK based) Multi-RAT Data-Plane Sequencing & Splitting Encapsulation & Tunneling Concatenation & Fragmentation Buffering & Retransmissions LTE Wi-Fi Compute Networking Storage WiFi User Data Other names and brands may be claimed as the property of others

25 Modules: vepc & M-RAT (2/2)

26 Agenda vepc Background Next Generation Infrastructure Core (NGIC) CORD High Level View NGIC and M-CORD Summary / Next Steps Intel Labs 26

27 Summary / Next Steps NGIC is a functional, DPDK based, EPC operating in bare-metal, VMs, or containers and orchestrated in M-CORD Additional EPC components, MME, HSS, PCRF, will be made available to CORD over time Intel Labs 27

28 NGIC Hands-on Tutorial Next Prerequisites for Hands-on Tutorial Install Docker (1.13 or higher) and Docker Compose Docker images for NGIC control, data plane and traffic generation docker pull ngiccorddemo/ngic-cp docker pull ngiccorddemo/ngic-dp docker pull ngiccorddemo/ngic-traffic Demo folder git clone Intel Labs 28

29 Thank You Intel Labs 29

30 Intel Confidential Internal Use Only

31 Backup Intel Labs 31

32 Efficient MATCH/Action Semantic Data Plane (1/2) Match/Action : Optimized Table Lookup with Cuckoo Hashing [Pagh 01] Scalable, High Performance Ethernet Forwarding with CuckooSwitch, Dong Zhu, Bin Fan, Dave Anderson (CMU), Michael Kaminsky (Intel) H1(x) H2(x) H1(x) H2(x) H1(x) H2(x) X X X Y One Insert may move a lot of items especially at high table occupancy. Optimal multi-writer insertion using Intel TSX H1(x) H2(x) H1(x) H2(x) H1(x) H2(x) Y X Y X Y Z X collision Z Intel Labs 32

33 Efficient MATCH/Action Semantic Data Plane (2/2) Throughput vs. # of entries X Previous rte_hashhash Cuckoo Traditional hash M 2M 4M 8M 16M 32M 3, , , , , Memory bandwidth vs. # of entries Previous rte_hashash Cuckoo Inserts / Second Millions Cuckoo Hash Insert Performance per CPU Core 32M Random 8M Random 2M Random 32M Sequential M 4M 0 0% 10% 20% 30% 40% 50% 60% 70% 80% Table Load Intel Labs 33

34 Modules: vepc & M-RAT (2/2)

Mobile-CORD Enable 5G. ONOS/CORD Collaboration

Mobile-CORD Enable 5G. ONOS/CORD Collaboration Mobile-CORD Enable 5G ONOS/CORD Collaboration http://opencord.org/ M-CORD Drivers = Operator Challenges In the last 5 years 100,000% Increase in Wireless Data Traffic $50 Billion Spectrum investment (~50