Academic Course Description

Transcription

1 Academic Course Description SRM University Faculty of Engineering and Technology Department of Electronics and Communication Engineering VL2003 DSP Structures for VLSI Systems First Semester, (ODD Semester) Course (catalog) description This course enables the students to understand the fundamentals, to learn various DSP structures and their implementation and To know designing constraints of various filters. Compulsory/Elective course: Compulsory for VLSI Specialization students Credit hours: 4 credits Course coordinator(s) Dr. J. Selvakumar, Assistant Professor (S.G), Department of ECE Instructor Name of the instructor Office location Office phone Consultations Dr. J Selvakumar TP12S8 selvakumar.j@ktr.srmuniv.ac.in Relationship to other courses Pre-requisites : Knowledge in Digital Signal Processing & VLSI course Assumed knowledge : Design and analysis of DSP Synthesis block in VLSI domain Following courses : NIL References 1. K.K Parhi: VLSI Digital Signal processing, John wiley, 2nd Edition Reprint, John G.Proakis, Dimitris G.Manolakis, Digital Signal Processing, Prentice Hall of India, 1st Edition, Class schedule: Four minutes lecture sessions per week. Section Schedule A D1 = 2 nd & 5 th Hr, D4=3 rd & 5 th Hr. Professional component General - 0% Basic Sciences - 0% Engineering sciences & Technical arts - 0% Professional subject - 100% Page 1 of 5

2 Broad area: Communication Signal Processing Electronics VLSI Embedded Test Schedule Weekly Teaching Plan Session No. S. No. Test Portions Date 1 Cycle Test Session th week of Aug 14 2 Model Test Session th week of Oct 14 Topics to be covered Time (min) Study Material Reference, Text Book 1 Linear System Theory- Introduction Ref. [2], Chapter-1 2 Convolution : Introduction, Linear Convolution with a problem 3 Correlation : Introduction and mathematical expressions DFT Time Domain & Frequency Domain Analysis with a Problem FFT Problems to analyze the frequency spectrum using DIT and DIF algorithm in detail. Basic concepts in FIR Filters: basic mathematical expressions & theory of operation. Basic concepts in IIR Filters: basic mathematical expressions & theory of operation. Filter Realizations : Basic FIR filter Realization Technique: DF- I and DF-II Filter Realizations: Basic FIR filter Realization Technique: Series and parallel configuration. Representation of DSP Algorithms Block Diagram Representation of DSP Algorithms - SFG Representation of DSP Algorithms - DFG Data-Flow Graph Representations Loop Bound and Iteration Bound Algorithms for Computing Iteration Bound : Introduction Longest Path Matrix Algorithm for iteration bound Computation with a problem set. Pipelining and Parallel Processing An Introduction Ref. [1], Chapter-1, Section 1.2, Ref. [2], Chapter-2. Section 1.2 Ref. [2], Chapter-3, Session Ref. [2], Chapter-4 Session session session Ref. [2], Chapter-5, session Ref. [2], Chapter 5, session session 1.4 session 1.4 session session 2.2 session 2.3 session 2.4 session session 3.1, 3.2 Page 2 of 5

3 18 Pipelining of FIR Digital Filters Data Broadcast structure, Fine-grain pipelining. session Parallel Processing - design of parallel FIR Filter session Pipelining for Low Power session Parallel Processing for Low Power session Combining Pipelining & Parallel Processing - Introduction Ref. [1], Chapter-3 session Retiming: Definitions- Properties and problems Ref. [1], Chapter-4, session 4.1, Solving Systems of Inequalities Retiming techniques cutest retiming Ref. [1], Chapter-4, and pipelining session 4.3, Introduction of Fast Convolution techniques for VLSI DSP Implementation session Cook-Toom Algorithm- mathematical derivation for 2x2, 2x3 linear convolution session Modified Cook-Toom Algorithm ; Derivation for 2x2, 2x3 linear convolution session Comparison between cook-toom and modified cook-toom algorithm. Design of Fast Convolution Algorithm by Inspection session 8.2.3, Parallel FIR filters formation using polyphase decomposition session Fast FIR algorithms Two, Three parallel structures- Introduction Ref. [1], Chap. -9 session Two Parallel and three Parallel mathematical derivation session Parallel architectures for Rank Order filters session Odd Even Merge sort architecture session Rank Order filter architecture session Parallel Rank Order filters session Running Order Merge Order Sorter session Low power Rank Order filter session Pipeline Interleaving in Digital Filters- Introduction. session Pipeline Interleaving in Digital Filters Inefficient Single/multi- Channel interleaving session Pipeline Interleaving in Digital Filters Efficient single channel interleaving session Pipeline Interleaving in Digital Filters Efficient multi channel interleaving session Page 3 of 5

4 41 Pipelining in 1st Order IIR Digital Filters : Introduction session Pipelining in 1st Order IIR Digital Filters ; Look-Ahead pipelining technique session Pipelining in 1st Order IIR Digital Filters ; Power-of-2 Decomposition session Pipelining in Higher IIR Digital Filters - Introduction session Pipelining in Higher IIR Digital Filters session Introduction to Clustered Look Ahead Filter Design session Introduction to Stable Clustered Look Ahead Filter Design session Parallel Processing in IIR Digital Filters session Introduction to Scaling Noise : Introduction, mathematical derivation session Introduction to Round off Noise : Introduction. session State Variable Description of Digital Filters. session Scaling Computation Mathematical derivation & problem solution. session Round off Noise Computation Mathematical derivation &problem Solution. session Round off Noise Computation in pipelined IIR Filters First Order. session Round off Noise Computation in pipelined IIR Filters Second session Round off noise computation using State Variable Description 1 st session Round off noise computation using State Variable Description 2 nd session Slow down transformation technique. 59 Retiming mechanism in higher-order IIR filter design. 60 Pipelining in higher-order IIR filter design. Evaluation methods Cycle Test - 20% Model Test - 20% Term Paper/surprise test - 10% Final exam - % Page 4 of 5

5 Prepared by: Dr. J.Selvakumar, Assistant Professor (S.G), Department of ECE Dated: 25 th June 2014 Revision No.: 00 Date of revision: NA Page 5 of 5