EE 4683/5683: COMPUTER ARCHITECTURE
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1 3/3/205 EE 4683/5683: COMPUTER ARCHITECTURE Lecture 8: Interconnection Networks Avinash Kodi, Agenda 2 Interconnection Networks Performance Metrics Topology
2 3/3/205 IN Performance Metrics Network cost number of switches number of (bidirectional) links on a switch to connect to the network (plus one link to connect to the processor) width in bits per link, length of link Network bandwidth (NB) represents the best case bandwidth of each link * number of links Bisection bandwidth (BB) represents the worst case divide the machine in two parts, each with half the nodes and sum the bandwidth of the links that cross the dividing line Other IN performance issues latency on an unloaded network to send and receive messages throughput maximum # of messages transmitted per unit time # routing hops worst case, congestion control and delay Bus IN Bidirectional network switch Processor node N processors, switch ( ), link (the bus) Only simultaneous transfer at a time NB = link (bus) bandwidth * BB = link (bus) bandwidth * 2
3 3/3/205 Ring IN N processors, N switches, 2 links/switch, N links N simultaneous transfers NB = link bandwidth * N BB = link bandwidth * 2 If a link is as fast as a bus, the ring is only twice as fast as a bus in the worst case, but is N times faster in the best case Fully Connected IN N processors, N switches, N- links/switch, (N*(N-))/2 links N simultaneous transfers NB = link bandwidth * (N*(N-))/2 BB = link bandwidth * (N/2) 2 3
4 3/3/205 Crossbar (Xbar) Connected IN N processors, N 2 switches (unidirectional),2 links/switch, N 2 links N simultaneous transfers NB = link bandwidth * N BB = link bandwidth * N/2 Hypercube (Binary N-cube) Connected IN 2-cube 3-cube N processors, N switches, logn links/switch, (NlogN)/2 links N simultaneous transfers NB = link bandwidth * (NlogN)/2 BB = link bandwidth * N/2 4
5 3/3/205 2D and 3D Mesh/Torus Connected IN N processors, N switches, 2, 3, 4 (2D torus) or 6 (3D torus) links/switch, 4N/2 links or 6N/2 links N simultaneous transfers NB = link bandwidth * 4N or link bandwidth * 6N BB = link bandwidth * 2 N /2 or link bandwidth * 2 N 2/3 Fat Tree N processors, log(n-)*logn switches, 2 up + 4 down = 6 links/switch, N*logN links N simultaneous transfers NB = link bandwidth * NlogN BB = link bandwidth * 4 5
6 3/3/205 Fat Tree Trees are good structures. People in CS use them all the time. Suppose we wanted to make a tree network. A B C D Any time A wants to send to C, it ties up the upper links, so that B can't send to D. The bisection bandwidth on a tree is horrible - link, at all times The solution is to 'thicken' the upper links. More links as the tree gets thicker increases the bisection Rather than design a bunch of N-port switches, use pairs SGI NUMAlink Fat Tree 6
7 3/3/205 IN Comparison For a processor system Network bandwidth Bisection bandwidth Total # of Switches Links per switch Total # of links Bus Ring Torus 6-cube Fully connected IN Comparison For a processor system Network bandwidth Bisection bandwidth Total # of switches Links per switch Total # of links (bidi) Bus Ring 2D Torus cube Fully connected
8 3/3/205 Network Connected Multiprocessors Proc Proc Speed # Proc IN Topology SGI Origin R fat tree 800 Cray 3TE Alpha 2 300MHz 2,048 3D torus 600 Intel ASCI Red Intel 333MHz 9,632 mesh 800 IBM ASCI White Power3 375MHz 8,92 multistage Omega BW/link (MB/sec) 500 NEC ES SX-5 500MHz 0*8 0-xbar 6000 NASA Columbia IBM BG/L Intel Itanium2 Power PC 440.5GHz 52*20 fat tree, Infiniband 0.7GHz 65,536*2 3D torus, fat tree, barrier Networks of Workstations (NOWs) Clusters Clusters of off-the-shelf, whole computers with multiple private address spaces Clusters are connected using the I/O bus of the computers lower bandwidth that multiprocessor that use the memory bus lower speed network links more conflicts with I/O traffic Clusters of N processors have N copies of the OS limiting the memory available for applications Improved system availability and expandability easier to replace a machine without bringing down the whole system allows rapid, incremental expandability Economy-of-scale advantages with respect to costs 8
9 3/3/205 Commercial (NOW) Clusters Dell PowerEdge eserver IBM SP Proc Proc Speed # Proc Network P4 Xeon 3.06GHz 2,500 Myrinet Power4.7GHz 2,944 VPI BigMac Apple G5 2.3GHz 2,200 Mellanox Infiniband HP ASCI Q Alpha 22.25GHz 8,92 Quadrics LLNL Thunder Intel Itanium2.4GHz,024*4 Quadrics Barcelona PowerPC GHz 4,536 Myrinet 9
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