QoS Architecture and Its Implementation. Sueng- Yong Park, Ph.D. Yonsei University

Transcription

1 Architecture and Its Implementation Sueng- Yong Park, Ph.D. Yonsei University

2 Scheduler Deficit Round Robin (DRR) Implementation of DRR Calculation of BW 2

3 Deficit Round Robin Each queue, Q[i], has a deficit counter D[i]. D[i] increases by a fixed amount when Q[i] is visited by the scheduler. -If (length(first_pkt_in_q[i]) > D[i]) { D[i] increases by some amount } -Else { packet transmission on output link; D[i] = D[i] length(first_pkt_in_q[i]); if (Q[i] is empty) { D[i] = 0;} } 3

4 Deficit Round Robin DRR keeps track of queues that were not served in each round of scheduling phase and to compensate them in the next round. Keep an active list of indicies of all non-empty queues to reduce the cost of memory access. In real world, the determination of D[i] is difficult. DRR may be unfair within the same scheduling round. 4

5 Implementation of DRR A timing wheel slot Current Time slot being serviced Queue Of Queue pointers Ring-shaped calendar queue structure is used to implement DRR algorithm. There are 2 rings of calendar queue, 1 for real-time traffic and 1 for normal traffic. Each ring is divided by many time slots. And each time slot represents fixed time. Each time slot holds a queue of queue pointers. Queue Of Queue pointers Queue Of Queue pointers A head pointer continuously advances time slot after serving all queues in queue pointers. 5

6 Deficit Round Robin Calculation of BW Normally Queues are scheduled according to the bandwidth calculated from this formula: Queue BW = CIRqueue + (1 Aggregate_CIRactive) * EIRqueue / Aggregate_EIRactive Aggregate_CIRactive and Aggregate_EIRactive are the sum of all the CIR and EIR for the active queues If Aggregate_CIRactive is greater than the allowed_usage, we scale the CIR of each queue: Scaled_CIRqueue = Allowed_usage * CIRqueue / Aggregate_Active_CIR Based on Queue BW, the scheduler decides which time slot to put current queue pointer. 6

7 Architecture of Enterprise Router Architecture overview Router CPU Low speed module Mid- High speed module 7

8 Router Architecture Overview Router CPU Routing Table Fast Fwding Table Shared Bus Switch Fabric Line Card Mid Speed Line Card Fast Speed Line Card 8

9 Router Architecture Router CPU Switch Process Programs ACL TCAM Router CPU extracts Fast Forwarding Table Layer 2 Table (CAM) Access List Table (TCAM) CPU Board Layer 2/4 Layer 3 ASIC ASIC Statistics Engine Fast Fwding Table Shared Bus Switch Fabric 9

10 Router Architecture Module Line Card Shared Bus MAC Arbitrator MAC R7K CPU ECC DRAM RAM CPU PCI PCI Adapter 10

11 Router Architecture Mid- High Speed Module Mid-High Speed Line Card Shared Bus Co- Process or Arbitrator High Speed Internal Switching Bus External Buffer Rx/Tx Asic Schedule (DRR) s Packet Buffer 11

12 Architecture in Router Class of Service (L3 ToS, L2 CoS) Flexible model Implementation examples 12

13 Class of Service Layer 3: Type of Service (ToS ( ToS) IP Precedence (IPP) DiffServ Code Point (DSCP) IP Prec= 0 7 DSCP =

14 Class of Service Layer 2: Class of Service (CoS ( CoS) Classify using the user priority bits in an ISL or 802.1Q frame COS =

15 Flexible Model CPU Fwding (DRR) ASIC Forwarding (DRR) 15

16 Flexible Model CPU Fwding ASIC Forwarding - Each module can be dynamically en/ disabled. 16

17 Flexible Model Hardware View Each Queue has Configurable Size & threshold Packet might be marked depending on policy Scheduling For Queue & Threshold Based on COS Each Queue has Configurable Size & threshold CPU Queue 1 Classify Queue Priority Q ARB Classify Policy; Forward Rewrite; Classify Queue 2 Priority Q DRR ARB TX Classification Can be forced - L2 CoS - IP Prec - DSCP Classification - IP L3/L4 - IPX L3/L4 - L2 MAC Rewrites Internal DSCP Into p COS - IP ToS 17

18 Flexible Model Example: to CPU Fwding ASIC Forwarding 18

19 Flexible Model Details: to Each Queue has Configurable Size & threshold Packet might be marked depending on policy Queuing Based on - IP Prec - DSCP - EXP - WRED Dequeuing Based on - Shaping - WFQ - High priority Classify Queue Priority Q ARB Classify PFC2 Policy; Forward Rewrite; Classify Queue 1 Queue n Priority 1 DRR TX RR Priority n Classification Can be forced - L2 CoS - IP Prec - DSCP Classification - IP L3/L4 - IPX L3/L4 - L2 MAC Rewrites Internal DSCP Into p COS - IP ToS 19

20 Flexible Model Example: to CPU Fwding ASIC Forwarding 20

21 Queuing Based on - IP Prec - DSCP - Traffic Index - EXP Flexible Model Details: to Dequeuing Based on - Shaping Packet might be marked depending on policy Scheduling For Queue & Threshold Based on COS Each Queue has Configurable Size & threshold PFC2 Queue 1 Classify Queue 1 Queue n DRR Classify Policy; Forward Rewrite; Classify Queue 2 Priority Q DRR ARB TX Trust Modes Classification - Untrusted Can IP be Prec forced - - L2 DSCP CoS - IP Prec - DSCP Classification - IP L3/L4 Rewrites Internal DSCP Into p COS - IP ToS 21

22 Conclusion DRR (or MDRR) is a cost effect queuing algorithm. Flexible architecture is important to meet diverse demands. Network processor based solution is preferable to hardwired solution. Capacity of the network processor and the router CPU becomes bottle-neck when scalability grows. 22