IBM POWER NETWORK PROCESSOR ARCHITECTURE

Transcription

1 IBM POWER NETWORK PROCESSOR ARCITECTURE ot Chips Symposium, August 13-15, 2 Dr. Marco eddes IBM Microelectronics, RTP, NC Copyright International Business Machines Corporation, 2. All right reserved.

2 IBM POWER NETWORK PROCESSOR Network Processor igh-speed Backbone WAN CORE Central Office Central Office EDE Base Station Access Plan LAN SAN FIBRE CANNEL SERVER CUSTOMER PREMISE SOO / Consumer Enterprise / Campus SERVER ADAPTER Copyright International Business Machines Corporation, 2. All right reserved.

3 IBM POWER NETWORK PROCESSOR ARCITECTURE FLEXIBLE PROTOCOL PROCESSORS Networking forwarding / filtering applications Layer 2, IP,IPX,Vlan... Internetworking up to Layer 7 Packet classification Policing Firewall Embedded PowerPC FM, LPM, SMT algorithm External CAM Use of DRAMs for large tables, counters... PCI BUS Switching Fabric I SWITC CONNECTIVITY RIT1/3 4 bps up to 64 ports Future 1 bps up to 256 ports COPROCESSOR CAMs Security Encryption... Coprocessor EPC eppc Picoprocessors DataFlow DATA FLOW Large Data Repository (up to 192 MB) Large Number of Frames (up to 512 k) Use of Memory Slices Frame Alteration - ardware Assist (Well knwn cases) - Flexible (picocode) Frame Alteration Scheduler I PORT CONNECTIVITY RIT1/3 4 bps 1 to 4 ports Future 1 bps 1 to 1 ports SCEDULER Traffic management, QOS Differentiated Services MAC / Framers Wrap Port Mirroring Debug & Sniffing functions NETWORK INTERFACE PORTS VERSATILE NETWORK INTERFACE SUPPORT Very dense "one MAC can handle one or several ports (1)" Ethernet, POS, ATM, Fibre Channel

4 NETWORK PROCESSOR MODULE RAINIER EPC 2 x 16 Picoprocessor threads 2 internal SRAMs (328 kb) 1 External ZBT SRAM 4 to 11 External DDR DRAMs Policer: 1 k Flows 27.2 bps external memory bandwidth PCI BUS igh level of integration in single chip 2x4 bps Switching Fabric EPC eppc Picoprocessors DataFlow DATA FLOW UP: Integrated SRAM Data Store DN: External DDR DRAM Data Store 2 Slices up to 64 MB 14.4 bps bandwidth Scheduler VERSATILE NETWORK INTERFACE SUPPOR SCEDULER 2 k Flows 1 External ZBT (Calendars) MAC / Framers ETERNET 4 x 1bps 4 x 1/1 Mbps SONET 1 xoc48 4 x OC12 16 x OC3 NETWORK INTERFACE PORTS

5 Rainier Architecture D-RAM's (2 to 7) S-RAM (1) DASL DASL DASL DASL SIF SIF E-UP SDM-UP SWITC DATA MOVER SDM-DN SWITC DATA MOVER E-DN ENQUEUE DEQUEUE SCEDULIN INTERNAL S-RAM's EPC ENQUEUE DEQUEUE INTERNAL S-RAM DATA STORE EMBEDDED PROCESSORS COMPLEX TRAFFIC MT SCEDULER D-RAM's (4) PMM - UP MULTIPLEXED MAC's A B C D W PMM - DN MULTIPLEXED MAC's DATA STORE DMU BUS DMU BUS ENET PY - ATM FRAMER Copyright International Business Machines Corporation, 2. All right reserved.

6 Rainier Packet Flow S DT/PSCB x36 D x32 D1 x16 D2 /Cnt /Cnt /Cnt /Cnt x16 D3 DT/PSCB DT/PSCB DT/PSCB DT/PSCB x16 D6 eppc/p eppc/p eppc/p eppc/p x18 E-UP TB Q QCB (64 x 4 x 2) + ((M + D) x 2) BCB (2K) FCB (2K) DATA STORE (2K Buffers) Q QCB (2) TB-RIN PCB (4+W) DASL-A SIF SDM-UP Ingress Flow Control C A B PMM - UP DASL-B Internal RAMs TSE : 2K x 128 1: 2K x 36 F T 1 ARBITER D COMPL UNIT A B C D W D 27 DISPATCER P DASL-A SDM-DN-A P 1 PMM - DN SIF Power PC EPC DASL-B SDM-DN-B Egress Flow Control E-DN SCEDULER Red Red1 reen PCB (4+W+D) x 2 Q FLOW Q REASM Q RCB (3K) QCB (8) FQCB (2K) Calenders Blue (4)... TP Q PQCB (4+W+D) x 2 MCC 4K D4 FFCB PFCB CFCB EStack x32 Data Store x32 1 x32 S1 Calendars x18 PCI Bus RISC Watch, CAB Watch, & JTA SPM DMU BUS DMU BUS EEPROM ENET PY - POS FRAMER Copyright International Business Machines Corporation, 2. All right reserved.

7 Embedded Processor Complex Architecture On-Chip Memories Off-Chip Memories 45 PowerPC Core 1 2 S D D1 D2 D3 D6 TSCM Arbiter Ingress Enqueue Completion Unit Egress Enqueue Interrupts EPC Freeze Exception Debug, Interrupts & Single Step Control Policy Manager Counter Manager Ingress (Rd+Wr) Ingress DPPU Egress Egress (Rd+Wr) Instruction Memory ardware Classifier CAB Arbiter CAB Ingress (Rd) Port Config Memory Dispatcher Dispatcher Data Buffers Egress (Rd) Copyright International Business Machines Corporation, 2. All right reserved.

8 Tree Algorithms 3 DIFFERENT TREE TYPES TUNED FOR DIFFERENT APPLICATIONS: FM = FIXED MATC TREE IDENTICAL SIZE FOR ALL TE KEYS OF TE TREE SUC AS: L2 FORWARDIN, VPI/VCI LOOK-UP, IPX FORWARDIN, RSVP TRAFFIC MANAEMENT POLICY LPM = LONEST PREFIX MATC VARIABLE LENT (BUT SAME STARTIN POINT) KEYS IN TE TREE SUC AS: IP FORWARDIN, SUBNETTIN CONCEPT SMT = SOFTWARE MANAED TREE ALL POSSIBLE COMBINATIONS OF NON-CONTIUOUS BIT PATTERNS INSIDE TE KEYS OF TE TREE RANE COMPARISON (SMALLER/EQUAL/REATER) FOR EAC BIT PATTERN SUC AS: L3 FILTER RULES, L4 POLICIES Copyright International Business Machines Corporation, 2. All right reserved.

9 NO SCEDULER 2 TARET PORT QUEUES PER PORT (2 ABSOLUTE PRIORITIES) SCEDULER TRAFFIC MANAEMENT PARAMETERS PER FLOW (CAN BE COMBINED): UARANTEED BANDWIDT BEST EFFORT WIT WEITED FAIRNESS MAXIMUM CONTROLLED BANDWIDT (WIT BEST EFFORT) MAXIMUM BURSTSIZE PRIORITY (LOW LATENCY PARAMETER) Copyright International Business Machines Corporation, 2. All right reserved.

10 Scheduler Algorithm Flow Flow 1 Flow FlowID FlowID... FlowID FlowID FlowID WFQ Port WFQ Port 255 Low Latency Sustainable (LLS) Normal Latency Sustainable (NLS) Round Robin Peak Bandwidth Shaping (PBS)